JP2656546B2 - Phase locked oscillator - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a phase-locked oscillator used in communication equipment and the like, and is particularly suitable for reducing fluctuations in steady-state phase error due to variations in parts and environmental changes. The present invention relates to a phase locked oscillator.

[Conventional technology]

In a conventional phase-locked oscillator, for example, as described in JP-B-62-26607, a loop filter for converting a phase difference detected by a phase comparator into a control voltage of a voltage-controlled oscillator includes a resistor, a capacitor, and an operational amplifier. doing.

FIG. 3 is a block circuit diagram illustrating a conventional phase locked oscillator. In FIG. 3, reference numeral 1 denotes a phase comparator for detecting a phase difference between the input clock IN and the phase comparison clock CLK,
Reference numeral 2 denotes a voltage controlled oscillator 3 which comprises resistors 5, 6, 7, 8, 9, 10, capacitors 11, 12, 13, 14 and an operational amplifier 15 and removes harmonic components from the output phase difference of the phase comparator 1. A low-pass loop filter that converts to a control voltage that controls the oscillation frequency of the
Reference numeral 3 denotes a voltage-controlled oscillator that changes the oscillation frequency according to the control voltage supplied from the loop filter 2 and outputs the output clock OUT. Reference numeral 4 denotes a frequency divider that divides the frequency of the output clock OUT into a phase comparison clock CLK.

With the above configuration, the phase comparator 1 detects a phase difference between the input clock IN and the phase comparison clock CLK divided by the frequency divider 4, and outputs a pulse wave having a pulse width corresponding to the phase difference. , Output Q, the differential voltage between the loop filter 2
To supply. The loop filter 2 acts as a low-pass filter including resistors 5 to 10, capacitors 11 to 14, and an operational amplifier 15, smoothes a rectangular wave output from the phase comparator 1 to remove unnecessary harmonic components, and A DC control voltage corresponding to the phase difference between the clock IN and the phase comparison clock CLK is supplied to the voltage controlled oscillator 3 to control the oscillation frequency of the voltage controlled oscillator 3. The frequency divider 4 is an output clock of the voltage controlled oscillator 3
OUT is frequency-divided and a phase comparison clock CLK is supplied to the phase comparator 1.

The input clock IN detected by the phase comparator 1 as described above
The phase difference between the phase control clock CLK and the phase comparison clock CLK is converted into a voltage for controlling the oscillation frequency of the voltage controlled oscillator 3 by the loop filter 2, and the voltage is used to control the oscillation frequency of the voltage controlled oscillator. It operates in the direction where the frequency and phase of CLK match. Here, in order to maintain the synchronization, it is necessary to always control the voltage-controlled oscillator 3 so that the output clock OUT follows the input clock CLK. Thus, a steady phase error for controlling the voltage-controlled oscillator 3 is required. Δθ exists and this steady phase difference Δ
θ is expressed by the following equation.

Δθ = (Δi / i) / K _d · K ₀ · K [rad] (1) where Δi / i is the ratio of the input frequency variation Δi to the input frequency i, and K _d is the phase difference of the phase comparator 1 − The voltage conversion gain [V / rad], K ₀ is the input voltage of the voltage controlled oscillator 3 −
The frequency conversion gain [1 / V], K is the DC voltage gain of the loop filter 2.

[Problems to be solved by the invention]

In the prior art, the steady-state phase error Δθ fluctuates due to variations in components constituting the phase comparator 1 and the loop filter 2 of the phase-locked oscillator, and changes in environment such as temperature and power supply voltage. Since the differential voltage amplitude of the output fluctuates due to the fluctuation, the phase difference-voltage conversion gain _Kd fluctuates. In the loop filter 2, the bias voltage of the operational amplifier 15, which is a component, is fixed. Therefore, the differential input of the operational amplifier 15 depends on the fluctuation of the output voltage of the phase comparator 1 and the variation of the resistance and capacitor of the loop filter 2. There is a case where the voltage of the terminal does not become equal to the potential difference with respect to the bias voltage, and this causes a difference in the current flowing into the differential input terminal, thereby causing an offset in the output voltage of the operational amplifier 15. Voltage of the voltage controlled oscillator 15 - Frequency conversion gain K ₀ varies. Such a change in the conversion gains K _d and K ₀ changes the steady-state phase error Δθ represented by the equation (1), so that not only the frequency synchronization in the phase-locked oscillator but also the phase difference between the input clock IN and the output clock OUT is obtained. When it is necessary to limit the variation of the steady-state phase error Δθ to a certain value or less, there is a problem that it is necessary to select individual components or to adjust circuit constants.

SUMMARY OF THE INVENTION An object of the present invention is to provide a highly stable phase-locked oscillator that reduces fluctuations in steady-state phase error due to variations in components and environmental changes without selecting components to be used or adjusting circuit constants.

[Means for solving the problem]

The above object is achieved by a voltage-controlled oscillator capable of controlling an oscillation frequency by a control voltage, a frequency divider for converting an output frequency of the voltage-controlled oscillator to a phase comparison frequency, and an output of the frequency divider and an external reference input clock. In a phase-locked oscillator comprising a phase comparator for detecting a phase difference, and a loop filter for converting the output phase difference of the phase comparator into a control voltage of the voltage-controlled oscillator and supplying the same, an input voltage is applied to an input of the loop filter. An amplitude limiting element such as a diode for limiting the amplitude of the operational filter to a constant value is added, and the bias voltage of the operational amplifier constituting the loop filter is set to the midpoint voltage of the input differential voltage to generate the offset voltage of the operational amplifier. This is achieved by a phase locked oscillator provided with a suppressing circuit.

[Action]

In the above-mentioned phase locked oscillator, the input differential voltage of the loop filter is limited to a constant amplitude value by the amplitude limiting element connected to the input part of the loop filter even if the amplitude of the output differential voltage of the phase comparator fluctuates. The phase-voltage conversion gain _Kd of the phase comparator can be suppressed to a constant value by absorbing the output differential voltage fluctuation accompanying the characteristic fluctuation of the phase comparator, and the bias voltage of the operational amplifier used for the loop filter is input. Since the differential input terminal voltage of the operational amplifier has a potential difference equal to the bias voltage due to the circuit for setting the differential voltage to the midpoint voltage, no offset occurs in the output voltage of the operational amplifier. voltage of the voltage controlled oscillator by suppressing variation of - frequency conversion gain K ₀ can be a constant value, constant value steady phase error Δθ these by suppressing the output phase fluctuations of the phase locked oscillator or more Can be restricted below.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS.

FIG. 1 is a block circuit diagram of a phase locked oscillator according to the present invention. 1, the same reference numerals as those in FIG. 3 denote corresponding parts, and 1 denotes an input clock IN and a phase comparison clock CLK.
2A is a loop filter added with an amplitude limiting element of the input unit according to the present invention and a circuit for setting the bias voltage of the operational amplifier 15 to the midpoint voltage of the input differential voltage. Is a voltage controlled oscillator that changes the oscillation frequency by the control voltage supplied from the loop filter 2A and outputs the output clock OUT, and 4 is a frequency divider that divides the frequency of the output clock OUT output from the voltage controlled oscillator 3 and outputs a phase comparison clock. This is a frequency divider that generates CLK.

In FIG. 1, reference numerals 17 and 18 denote resistors connected to a power supply to keep the output voltage of the phase comparator 1 at a certain value or more, 19 and 20 denote series resistors, and 21 and 22 denote input differences of the loop filter 2A according to the present invention. It is a diode of an amplitude limiting element that limits the amplitude of the dynamic voltage. Reference numerals 23 and 24 denote resistors for forming the midpoint voltage of the differential voltage having the amplitude limited according to the present invention, reference numeral 25 denotes a resistor for setting the midpoint voltage of the differential voltage to the bias voltage of the operational amplifier 15, and reference numeral 27 denotes the amplitude limit. A capacitor that smoothes the midpoint voltage of the received differential voltage.
These constitute a circuit for setting the bias voltage of the operational amplifier 15 to the midpoint voltage of the input differential voltage. 15 is an operational amplifier, 7, 8, and 26 are resistors that determine the DC gain of the loop filter, 9 is a resistor that determines the frequency characteristics of the loop filter,
Reference numeral 13 denotes a capacitor for determining the frequency characteristic of the loop filter, and these constitute a low-pass filter.

FIG. 2 is an operation waveform diagram of an input differential voltage (Q and output of the phase comparator 1), an amplitude limiting voltage (a point and b point voltage), and a bias voltage of the loop filter 2A of FIG. Then the first
The operation of the figure will be described with reference to FIG. First, the phase comparator 1 shown in FIG. 1 detects a phase difference between a reference input clock IN input from outside and a phase comparison clock CLK, and outputs a pulse wave having a pulse width corresponding to the phase difference. The waveform of the output Q of this phase comparator 1 is shown in FIG. Output of phase comparator 1
The differential voltage between Q and Q is supplied to the loop filter 2 through the series resistors 19 and 20. The phase differential voltage of the output of the comparator 1 outputs Q as shown in FIG. 2, the "H" and the voltage V _OH when the level "L" differential voltage of the voltage V _OL when the level V _OH - V _OL . This voltage V _OH is pulled up to the power supply voltage by the resistors 17 and 18.

Here, if diodes 21 and 22 forming an amplitude limiting element connected to the input section of the loop filter 2A are diodes whose forward voltage V _AK is sufficiently smaller than the power supply voltage, the differential voltage input to the loop filter 2 can be reduced. Amplitude of diodes 21, 22
_Is limited to the forward voltage _VAK . FIG. 2 shows the waveforms of the voltage at point a and the voltage at point b at both ends of the diodes 21 and 22.
Now, if the power supply voltage or the characteristics of the phase comparator 1 fluctuate,
For example, the voltage V _OH at the “H” level of the output Q in the section A shown in FIG. 2 changes by the voltage ΔV _{OH in the} section B shown in FIG. 2 to become the voltage V _OH + ΔV _OH . the voltage V _OL + _{ΔV OL} voltage V _OL when the "L" level of is changed by a voltage ΔV _OL. That is, the differential voltage V _OH −V _OL of the output of the phase comparator 1 changes to the voltage V _OH + ΔV _OH − (V _OL + ΔV _OL ). However, the input voltage of the loop filter 2 depends on the diodes 21 and 22 in the input section.
Therefore, the amplitude limiting voltage (diode forward voltage) _VAK between the voltage at point a and the voltage at point b at both ends of the diodes 21 and 22 does not change as shown in FIG. As described above, the amplitude of the amplitude limiting voltage V _AK of the differential voltage input to the loop filter 2A is not affected by the fluctuation of the differential voltage of the output of the phase comparator 1, so that the amplitude limiting voltage of the phase comparator 1 is controlled. The phase difference-voltage conversion gain _Kd has a constant value.

The midpoint voltage of the input differential voltage of the operational amplifier 15 whose amplitude has been limited at the input of the loop
The voltage V _AK is divided into two by resistors 23 and 24 having the same resistance, and then smoothed by a capacitor 27 to be a DC voltage. The positive terminal of the differential input terminal of the operational amplifier 15 is passed through a resistor 25. And becomes the bias voltage of the operational amplifier 15. Since the differential voltage subjected to the above amplitude limitation is input to the negative and positive terminals of the differential input terminal of the operational amplifier 15 through the resistors 7 and 8, the potential difference between the differential input terminals is equal to the bias voltage. Becomes Therefore, there is no difference between the currents flowing into the differential input terminals, and no offset voltage occurs in the output voltage of the operational amplifier 15. For example, even when the voltage of the output Q of the phase comparator 1 fluctuates due to the fluctuation of the power supply voltage from the section A as in the section B shown in FIG. 2, the midpoint voltage of the amplitude-limited differential voltage V _AK That is, since only the bias voltage fluctuates and the amplitude of the differential voltage _VAK does not change, no offset voltage is generated at the output of the operational amplifier 15. Since this the control voltage of the voltage controlled oscillator 3 is controlled in response to the phase difference detected by the phase comparator 1, the voltage of the voltage controlled oscillator 3 - Frequency conversion gain K ₀ is a constant value.

Thus, the operational amplifier 15, the resistors 7, 8, 9, 26 and the capacitor
The low-pass type filter composed of 13 smoothes the amplitude-limited voltage of the pulse wave having a pulse width corresponding to the phase difference between the input clock IN and the phase comparison clock CLK detected by the phase comparator 1, and removes unnecessary harmonic components. Is supplied to the voltage-controlled oscillator 3 to control the oscillation frequency of the voltage-controlled oscillator 3. The frequency divider 4 divides the output clock OUT output from the voltage controlled oscillator 3 to generate a phase comparison clock CLK, and supplies this to the phase comparator 1.

As described above, the phase-locked oscillator according to the present embodiment uses the loop filter 2A including the amplitude limiting element for detecting the phase difference detected by the phase comparator 1 and the circuit for setting the bias voltage to the midpoint voltage of the input differential voltage. The control voltage is converted into a control voltage of the control oscillator 3, and the oscillation frequency of the voltage control oscillator 3 is controlled by the control voltage.
It operates in the direction where the frequency and phase of K match. Here, the steady phase error Δθ required to maintain the synchronization between the input clock IN and the output clock OUT is given by the equation (1). In this embodiment, the conversion gains K _d and K ₀ are components as described above. Since a constant value is maintained with respect to variations in the temperature and changes in the environment such as temperature or power supply voltage, a characteristic with high stability without fluctuation of the steady-state phase error Δθ can be obtained.

According to the present embodiment, it is possible to obtain a highly stable phase-locked oscillator having small variations in steady-state phase error due to variations in individual components constituting the phase comparator, the loop filter, and the like and changes in the environment such as temperature and power supply voltage. .

〔The invention's effect〕

According to the present invention, fluctuations in the steady-state phase error due to variations in components and changes in the environment can be reduced, so that it is necessary to limit the steady-state phase error to a certain value or less without selecting used components or adjusting circuit constants. There is an effect that a phase-locked oscillator used for a communication device or the like having a certain characteristic can be provided.

[Brief description of the drawings]

FIG. 1 is a block circuit diagram showing an embodiment of a phase locked oscillator according to the present invention, FIG. 2 is an operation waveform diagram of FIG. 1, and FIG. 3 is a block circuit diagram illustrating a conventional phase locked oscillator. 1 phase comparator 2A loop filter 3 voltage controlled oscillator 4 frequency divider 15 operational amplifier 21,22 diode (amplitude limiting element) 7,8,9,17,18,19 , 20,23,24,25,26 …… Resistance 13,27 …… Capacitor

Claims (2)

(57) [Claims] 1. A voltage controlled oscillator capable of controlling an oscillation frequency by a control voltage, a frequency divider for converting an output frequency of the voltage controlled oscillator into a phase comparison frequency, and a reference for externally inputting the output of the frequency divider A phase comparator that detects a phase difference from an input clock, a loop filter including a resistor, a capacitor, and an operational amplifier that converts an output of the phase comparator into a control voltage of the voltage-controlled oscillator and supplies the voltage to the voltage-controlled oscillator. Wherein the loop filter limits the amplitude of the phase difference voltage output from the phase comparator to the input section and suppresses the voltage fluctuation to the differential voltage input to the operational amplifier. An amplitude control element for converting, further connected to the amplitude control element and the operational amplifier to generate a midpoint voltage of the differential voltage and calculate the midpoint voltage. Phase locked oscillator, characterized in that a circuit for suppressing an offset voltage of the operational amplifier by inputting the operational amplifier as the bias voltage of the width unit. 2. The phase-locked oscillator according to claim 1, wherein said amplitude limiting element comprises a pair of diodes whose forward voltage directions are opposite to each other.