JPH0546358Y2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a phase locked circuit using a logic circuit as a phase comparator.

[Technical background of the invention]

Generally, a phase-locked circuit using a logic circuit has a third
As shown in the figure, the input signal and the voltage controlled oscillator 11
A first logic circuit 12 comprising, for example, a D-type flip-flop, compares the phase of the output signal with
The output signal of the logic circuit 12 is passed through the loop filter 13.
The signal is smoothed by the error amplifier 14 and amplified by the error amplifier 14. This error amplifier 14 has a power supply voltage Vcc divided by a resistance
Divided by R ₁ and R ₂ , reference bias voltage Vref
The output signal amplified by the error amplifier 14 is applied to the control input of the voltage controlled oscillator to achieve phase synchronization.

[Problems with background technology]

However, in such a phase comparison circuit, the output voltage DC component of the logic circuit must almost match the reference bias voltage of the amplifier. When the difference in bias voltage becomes large, the synchronization pull-in range becomes narrower and the performance deteriorates.

[Purpose of the invention]

This invention was created in view of the above problems.
The purpose of the present invention is to provide a phase locked circuit whose performance does not deteriorate due to temperature fluctuations or power supply voltage fluctuations.

[Summary of the idea]

The present invention achieves the above object by providing a second logic circuit with a fixed logic state and generating a reference bias voltage for the amplifier based on the output level of the second logic circuit.

[Example of idea]

An embodiment of the present invention will be described in detail based on the drawings of FIGS. 1 and 2.

1 and 2 show a first embodiment and other embodiments of the present invention, and parts having the same functions as those in FIG. 3 are given the same reference numerals for convenience of explanation.

1, the difference from the conventional example shown in FIG. 3 is that a second logic circuit (D flip-flop) 16, which is the same as the first logic circuit 12 and has a fixed logic state, is connected to the resistor _R1 . and this first
The logic circuit 12 and the second logic circuit 16 are kept in substantially the same thermal environment. With this second logic circuit 16 in a preset state, a high level fixed output voltage is divided by dividing resistors R ₁ and R ₂ to obtain a reference bias voltage.

In another embodiment shown in FIG. 2, a second logic circuit 16 is connected to both dividing resistors R ₁ and R ₂ .
As in the figure, the thermal environment is made almost the same as that of the first logic circuit 12. Then, as above, the second logic circuit 16 is set in a preset state, and the high level fixed output voltage and the low level fixed output voltage are divided by the resistor.
The reference bias voltage is obtained by dividing by R ₁ and R ₂ .

[Effect of idea]

As explained above, the present invention provides a second logic circuit with a fixed logic state, and generates the reference bias voltage for the amplifier based on the output level of the second logic circuit, so it is possible to avoid fluctuations in temperature and power supply voltage. Therefore, even if the high level voltage of the first logic circuit changes, the output voltage of the second logic circuit changes by almost the same amount, and the DC output voltage of the first logic circuit and the reference bias voltage match. Therefore, the synchronization pull-in range hardly changes, and the performance can be expected to be improved. In addition, if the first logic circuit and the second logic circuit are housed in the same package, the thermal environment will always be the same, making it more effective.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a first embodiment of the phase locked circuit of the present invention, FIG. 2 is a circuit diagram showing another embodiment, and FIG. 3 is a circuit diagram showing a conventional example. 11...Voltage controlled oscillator, 12...First logic circuit, 13...Loop filter, 14...Error amplifier, 16...Second logic circuit, _R1 , _R2 ...Division resistor, Vcc... Power-supply voltage.

Claims (1)

[Scope of utility model registration request] a voltage controlled oscillator; a first logic circuit that outputs a signal corresponding to a phase difference between an input signal and an output signal of the voltage controlled oscillator; and amplifying a signal obtained based on the output of the first logic circuit. and an amplifier added as a control input of the voltage controlled oscillator, a second logic circuit which is the same as the first logic circuit and whose logic state is fixed to a predetermined logic state is provided, A phase synchronized circuit generating a reference bias voltage for the amplifier based on the output level of the second logic circuit.