JPS60172441U - Phase-locked oscillator circuit - Google Patents

Phase-locked oscillator circuit

Info

Publication number
JPS60172441U
JPS60172441U JP6120384U JP6120384U JPS60172441U JP S60172441 U JPS60172441 U JP S60172441U JP 6120384 U JP6120384 U JP 6120384U JP 6120384 U JP6120384 U JP 6120384U JP S60172441 U JPS60172441 U JP S60172441U
Authority
JP
Japan
Prior art keywords
phase
oscillator circuit
voltage
locked oscillator
limiting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6120384U
Other languages
Japanese (ja)
Inventor
山田 芳弘
Original Assignee
日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気株式会社 filed Critical 日本電気株式会社
Priority to JP6120384U priority Critical patent/JPS60172441U/en
Publication of JPS60172441U publication Critical patent/JPS60172441U/en
Pending legal-status Critical Current

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  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来のPLL回路の回路図、第2図は本考案の
実施例の回路図である。 主要部分の符号の説明、1・・・位相比較器、2・・・
VCO14,5・・・LPF、6・・・制御電圧制限面
路、DI、D2・・・電圧制限用ダイオード、OF2・
・・低インピーダンス出力のオペアンプ。
FIG. 1 is a circuit diagram of a conventional PLL circuit, and FIG. 2 is a circuit diagram of an embodiment of the present invention. Explanation of symbols of main parts, 1... Phase comparator, 2...
VCO14, 5...LPF, 6...Control voltage limiting plane, DI, D2...Voltage limiting diode, OF2...
...Low impedance output operational amplifier.

Claims (2)

【実用新案登録請求の範囲】[Scope of utility model registration request] (1)電圧制御型発振手段の制御電圧範囲を制限する電
圧制限手段を有する位相同期式発振回路であって、前記
電圧制限手段の電圧制限素子のバイアスを一定に維持す
るための定電圧発生手段を具備してなることを特徴とす
る位相同期式発振回路。
(1) A phase-locked oscillation circuit having a voltage limiting means for limiting the control voltage range of the voltage controlled oscillating means, the constant voltage generating means for maintaining a constant bias of a voltage limiting element of the voltage limiting means. A phase-locked oscillator circuit comprising:
(2)前記定電圧発生手段は、低インピーダンス出力特
性を有する演算増幅器からなることを特徴とする実用新
案登録請求の範囲第1項記載の位相同期式発振回路。
(2) The phase-locked oscillator circuit according to claim 1, wherein the constant voltage generating means comprises an operational amplifier having low impedance output characteristics.
JP6120384U 1984-04-25 1984-04-25 Phase-locked oscillator circuit Pending JPS60172441U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6120384U JPS60172441U (en) 1984-04-25 1984-04-25 Phase-locked oscillator circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6120384U JPS60172441U (en) 1984-04-25 1984-04-25 Phase-locked oscillator circuit

Publications (1)

Publication Number Publication Date
JPS60172441U true JPS60172441U (en) 1985-11-15

Family

ID=30589260

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6120384U Pending JPS60172441U (en) 1984-04-25 1984-04-25 Phase-locked oscillator circuit

Country Status (1)

Country Link
JP (1) JPS60172441U (en)

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