JPS5921528Y2 - variable frequency oscillator - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a variable frequency oscillator whose oscillation frequency can be changed.

Conventionally, a Clapp oscillator shown in FIG. 1, whose oscillation frequency is controlled by voltage, has been known.

In the Clapp oscillator shown in FIG. 1, a variable capacitance diode 2 is connected via a capacitor 3 to a capacitor 1 that forms part of an LC tuning circuit that is a feedback circuit, so as to be in parallel with this capacitor 1. There is.

A control voltage is applied to the variable capacitance diode 2 from the capacitance adjustment power supply 15 via the input terminal 18 and the resistor 4.
The oscillation frequency is controlled by the change in the capacitance value of the variable capacitance diode 2 at this time.

Note that the Clapp oscillator described above is known to have a higher stability of oscillation frequency than conventional oscillators.

In the Clapp oscillator shown in FIG. 1, the amplifier composed of the transistor 10 and bias resistors 5 and 6°7 operates as an emitter follower.
The output as an oscillator is taken out from an output terminal 17 connected to the emitter of the transistor 10.

However, in the wrap oscillator shown in Fig. 1, assuming that the variable capacitance range of the variable capacitance diode 2 is several hundred to several thousand PF, only a very narrow oscillation frequency variable range of a few tenths of a percent is obtained around IKHz. It's something that doesn't exist.

The present invention was devised in view of such problems, and includes a transistor, two capacitors connected in series between the base of this transistor and a first reference potential point (for example, earth potential), and the above-mentioned capacitor. a resistor connected between the emitter of the transistor and the first reference potential point;
A Clapp oscillator, each comprising a coil and a capacitor connected in series between the base of the transistor and the first reference potential point, and the emitter of the transistor and the connection point of the two capacitors are connected. In the variable frequency oscillator configured as above, the collector of the transistor and the second reference potential point (for example, the power supply voltage V.

0) and by supplying a bias to the base of the transistor, the transistor performs a saturation amplification operation, whereby the oscillation frequency of the Clapp oscillator can be changed in accordance with the amount of bias. That's what I do.

With this configuration, it is possible to widen the variable range of the oscillation frequency while maintaining the advantage of the conventional Clapp oscillator that the oscillation frequency is highly stable.
Since the oscillation frequency can be changed simply by changing the bias amount without using a variable capacitance diode or the like, a low-mounted device with excellent temperature stability can be obtained.

The present invention will be explained below with reference to examples and FIGS. 2 to 4.

FIG. 2 shows a Clapp oscillator to which the present invention is applied.

In the Clapp oscillator shown in FIG. 2, like the conventional Clapp oscillator shown in FIG. 1, resistors 5 and 6 are connected to the base of the transistor 10, and a resistor 7 is connected to the emitter for biasing. In addition to
A resistor 8 is also connected for bias between the collector of the transistor 10 and the power supply voltage VCC.

Note that if the resistor 8 is not connected, the oscillation frequency cannot be changed even if the base bias amount is changed.

These transistors 10 and resistors 5°6, 7
．． The amplifier constituted by 8 constitutes a saturation amplifier capable of performing saturation amplification operation.

Note that whether the saturation amplification operation or the linear amplification operation is performed is determined by the bias current supplied to the base of the transistor 10, as will be described later.

The capacitors 12, 13, 14 and the coil 11 constitute an LC tuning circuit as a feedback circuit.

The base of the transistor 10 is grounded through a series circuit of a capacitor 12 and a coil 11, and a series circuit of a capacitor 13 and a capacitor 14, respectively.

Further, the emitter of the transistor 10 is connected to the connection point between the capacitor 13 and the capacitor 14.

A bias adjustment power supply 15 is connected to the base of the transistor 10.
A bias current is supplied from the input terminal 18 and the resistor 4 through the input terminal 18 and the resistor 4.

This bias current can be changed by adjusting the power supply 15.

Note that the output of the Clapp oscillator shown in FIG. 2 can be taken out from either the output terminal 16 connected to the collector of the transistor 10 or the output terminal 17 connected to the emitter of the transistor 10.

Next, the operation of the Clapp oscillator shown in FIG. 2 having the configuration described above will be explained.

When the bias current supplied to the base of the transistor 10 is only the bias current DC1 supplied by the resistors 5 and 6 and the bias current from the power supply 15 is zero, the transistor 10 performs a linear amplification operation. .

At this time, the oscillator shown in FIG. 2 operates as the well-known glue/lap oscillator shown in FIG. 1, and the base current IBI,
Collector voltage E.

1 changes as shown in FIG.

At this time, the base current IB□ is a current obtained by superimposing the alternating current AC fed back through the series circuit of the coil 11 and the capacitor 12 and the series circuit of the capacitor 14 and the capacitor 13, and the bias current DC1 mentioned above. flows.

Note that the first quadrant in FIG. 3 is the collector voltage E.

The second quadrant is the collector voltage EC and collector current I.

The load line representing the relationship between
Each quadrant indicates a temporal change in base current IB.

When a bias current DC2 is supplied from the power supply 15 via the resistor 4, this bias current DC2 flows to the base of the transistor 10 superimposed on the above-mentioned alternating current AC and bias current DC1.

The base current and collector voltage at this time are the third
IB2 and E shown in the figure.

It becomes 2. The base current Ie corresponds to the base current IBI increased by the bias current DC2.

In this case, the transistor 10 performs the saturation amplification operation at time t1 when the base current ■8□ reaches the saturation level S.

When the transistor 10 performs the saturation amplification operation in this way,
As the oscillation conditions change and the oscillation weakens, the feedback reduces the alternating current AC supplied to the base of transistor 10.

This decrease in the alternating current AC means a decrease in the base current IB2, and the transistor 10 is returned from the saturation amplification operation region to the linear amplification operation region and continues to oscillate.

As a result, the collector voltage of the transistor 10 becomes the collector voltage E mentioned above.

Voltage E with period T2 shorter than on period 1.

Obtained as 2. If the bias current DC3 is further superimposed on the base current ■8□ by adjusting the power supply 15 to make the voltage of the power supply 15 larger than in the above case, the base current IB3 of the transistor 10 becomes as shown in FIG. It becomes like this.

In this case, the base current IB3 reaches the saturation level S even earlier than the base current IB2 described above, so the collector voltage Ec3 at this time is equal to the collector voltage E described above.

The memorization period T3 is longer than the period T2 of 2.

In the oscillator shown in FIG. 2, the collector voltage E obtained as described above.

may be derived from the output terminal 16 as an oscillation output, or the emitter voltage of the transistor 10 may be derived from the output terminal 17 as an oscillation output.

The oscillator shown in FIG. 2 has the following features.

That is, the variable range of the oscillation frequency is very wide even in a low frequency band.

Specifically, the power supply voltage■. When 0 is 5■, 3K
A variable range of ±11% is obtained near H2.

This variable range is the power supply voltage V. It is possible to make it even larger by increasing the variable range of the base current of the transistor 10 by increasing 0.

Furthermore, since the oscillation frequency can be changed simply by changing the amount of bias without using a variable capacitance diode or the like as in the conventional example shown in FIG. 1, it has excellent temperature stability and is low-mounted.

Taking advantage of these characteristics, the Clapp oscillator shown in FIG. 2 can be applied to a variable frequency oscillator 20 of a locked oscillator, as shown in FIG.

The locked oscillator shown in FIG. 4 obtains a signal synchronized with the power supply frequency for operating a power supply synchronized sweep oscillator or the like.

A normal commercial power supply contains noise, and equipment synchronized with the power supply will malfunction due to this noise, so the circuit shown in FIG. 4 is designed to obtain a signal that does not contain noise and is synchronized with the power supply frequency.

In the circuit shown in FIG. 4, the flip-flop 21
, the commercial power frequency, for example 60H, is input from the input terminal 19.
2 signal is supplied, and this signal is converted into a rectangular wave by this flip-flop 21.

flip flop 23 as a gate signal.

The signal gated by this gate signal is transmitted to the integrator circuit 2.
This is the output of 7.

The integrating circuit 27 integrates the output of a frequency divider 26, which will be described later, to obtain a sawtooth wave.

The level when this sawtooth wave is gated by the gate signal which is the output of the differentiating circuit 22 is the level of the DC hold circuit 24.
is held by

The hold value held by this DC hold circuit 24 is supplied as a control signal to the input terminal 18 of the variable frequency oscillator 20, so that the oscillation operation of this oscillator is performed as described above.

Note that the output of this variable frequency oscillator 20 is 3.84KH2
It is set to have a nearby frequency.

The output of this variable frequency oscillator 20 is frequency-divided by a frequency divider 26 to become a signal around 60 Hz.

The output of the frequency divider 26 is led out from an output terminal 28 and is also supplied to an integrating circuit 27, where a sawtooth wave is generated as described above.

The output frequency of the variable frequency oscillator 20 decreases and the frequency divider 2
If the period of the output of 6 becomes longer, or the input terminal 19
When the frequency of the commercial power supply supplied to the differential circuit 27 decreases and the period of the output of the differentiating circuit 22 becomes shorter, the higher level of the sawtooth wave that is the output of the integrating circuit 27 becomes the differential signal that is the output of the differentiating circuit 22. gated by.

Therefore, a high level is held in the DC hold circuit, which increases the oscillation frequency of the variable frequency oscillator 20.

Conversely, if the output frequency of the variable frequency oscillator 20 increases and the period of the output of the frequency divider 26 becomes shorter, or if the commercial power frequency supplied to the input terminal 19 increases and the differentiating circuit 2
When the period of the output of 2 becomes longer, the low level of the sawtooth wave output from the integrating circuit 27 is gated by the differential signal output from the differentiating circuit 22.

Therefore, a low level is held in the DC hold circuit, and therefore the oscillation frequency of the variable frequency oscillator 20 is lowered.

In this way, in the circuit shown in FIG. 4, a signal locked to the commercial power frequency supplied from the output terminal 28 to the input terminal 19 is obtained.

Even if the commercial power supply frequency fluctuates by 60H2±10%, the output of the variable frequency oscillator 20 is 3.84 KHz.
It can be sufficiently tracked by changing within a range of ±10%.

Note that this frequency variable range can be further expanded by increasing the power supply voltage for operating the variable frequency oscillator 20 as described above.

As described above, according to the present invention, by connecting a resistor between the collector of the transistor and the second reference potential point and supplying a bias to the base of the transistor, the transistor performs a saturation amplification operation. As a result, the oscillation frequency of the Clapp oscillator can be changed in accordance with the above bias amount, so the variable range of the oscillation frequency can be widened while maintaining the advantage of the conventional Clapp oscillator of high oscillation frequency stability. In addition, since the oscillation frequency can be changed simply by changing the bias amount without using a variable capacitance diode or the like, a low-mounted device with excellent temperature stability can be obtained.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing a conventionally known Clapp oscillator;
4 to 4 show examples of the present invention, FIG. 2 is a circuit diagram showing a Clapp oscillator to which the present invention is applied, and FIG. 3 is a waveform for explaining the operation of the circuit shown in FIG. 2. Figure, 4th
This figure is a block diagram showing a locked oscillator using the Clapp oscillator shown in FIG. 2 as a variable frequency oscillator. In addition, in the symbols used in the drawings, 4゜5, 6
．． 7. 8 is a resistor, 10 is a transistor, 12゜13
, 14 is a capacitor, 15 is a power supply for bias adjustment, 2
0 is a variable frequency oscillator.

Claims (1)

[Scope of utility model registration request] a transistor, two capacitors connected in series between the base of the transistor and a first reference potential point, and a resistor connected between the emitter of the transistor and the first reference potential point; and a coil and a capacitor connected in series between the base of the transistor and the first reference potential point, and the emitter of the transistor and the connection point of the two capacitors are connected. In a variable frequency oscillator having a Clapp oscillator configuration, a resistor is connected between the collector of the transistor and a second reference potential point, and a bias is supplied to the base of the transistor to cause the transistor to perform a saturation amplification operation; A variable frequency oscillator characterized in that the oscillation frequency of the Clapp oscillator can be changed according to the bias amount.