JPS59195846U - Input circuit of frequency divider circuit - Google Patents
Input circuit of frequency divider circuitInfo
- Publication number
- JPS59195846U JPS59195846U JP8961683U JP8961683U JPS59195846U JP S59195846 U JPS59195846 U JP S59195846U JP 8961683 U JP8961683 U JP 8961683U JP 8961683 U JP8961683 U JP 8961683U JP S59195846 U JPS59195846 U JP S59195846U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- frequency divider
- signal
- input
- inverter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Superheterodyne Receivers (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図〜第３図は分周回路の入力回路の従来例を示す回
路図、第４図は従来例の電圧利得特性を示す特性図、第
５図は従来例の理想的な入力電圧特性を示す特性図、第
６図〜第８図は従来例を説明するための波形図、第９図
は従来例の実際の入力電圧特性を示す特性図、第１０図
は本考案の実施例を示す回路図、第１１図及び第１２図
は本実施例の第１及び第２のインバータ段の各々の電圧
利得特性を示す特性図、第１３図は本実施例の入力電圧
特性を示す特性図である。
主な図番の説明、１，７・・・入力端子、２，４゜５、
１０． １３． １４．２３・・・インバータ、６・
・・分周回路、８・・・帰還抵抗、９・・・増幅回路、
１１・・・第１のインバータ段、１２第２のインバータ
段、１５・・・遮断回路、１９・・・ＮＯＲゲート。Figures 1 to 3 are circuit diagrams showing conventional examples of input circuits of frequency divider circuits, Figure 4 is a characteristic diagram showing voltage gain characteristics of the conventional example, and Figure 5 is ideal input voltage characteristics of the conventional example. FIGS. 6 to 8 are waveform diagrams for explaining the conventional example, FIG. 9 is a characteristic diagram showing the actual input voltage characteristics of the conventional example, and FIG. 10 is a characteristic diagram showing the actual input voltage characteristics of the conventional example. 11 and 12 are characteristic diagrams showing the voltage gain characteristics of each of the first and second inverter stages of this embodiment, and FIG. 13 is a characteristic diagram showing the input voltage characteristics of this embodiment. It is. Explanation of main drawing numbers, 1, 7...input terminal, 2, 4゜5,
10. 13. 14.23... Inverter, 6.
...Frequency divider circuit, 8...Feedback resistor, 9...Amplification circuit,
DESCRIPTION OF SYMBOLS 11... 1st inverter stage, 12... 2nd inverter stage, 15... Cutoff circuit, 19... NOR gate.
Claims (1)
接続された第１のインバータ段と、前記増幅回路の出力
端に接続され前記第１のインバータ段とは電圧利得の周
波数特性が異なる第２のインバータ段と、前記信号に応
じて前記第１及び第２のインバータ段のいずれか一方の
インバータ段における信号の伝達を遮断する遮断回路と
、前記第１及び第２のインバータ段の出力を入力し出力
信号を分周回路の入力信号として印加する論理回路とよ
り構成したことを特徴とする分周回路の入力回路。An amplifier circuit that amplifies an input signal, a first inverter stage connected to the output end of the amplifier circuit, and the first inverter stage connected to the output end of the amplifier circuit have different voltage gain frequency characteristics. a second inverter stage; a cutoff circuit that interrupts signal transmission in one of the first and second inverter stages according to the signal; and outputs of the first and second inverter stages. What is claimed is: 1. An input circuit for a frequency divider circuit, comprising a logic circuit that inputs a signal and applies an output signal as an input signal to the frequency divider circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8961683U JPS59195846U (en) | 1983-06-10 | 1983-06-10 | Input circuit of frequency divider circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8961683U JPS59195846U (en) | 1983-06-10 | 1983-06-10 | Input circuit of frequency divider circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59195846U true JPS59195846U (en) | 1984-12-26 |
| JPH0445305Y2 JPH0445305Y2 (en) | 1992-10-26 |
Family
ID=30219515
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8961683U Granted JPS59195846U (en) | 1983-06-10 | 1983-06-10 | Input circuit of frequency divider circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59195846U (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5177040U (en) * | 1974-12-12 | 1976-06-17 | ||
| JPS57138220A (en) * | 1981-02-20 | 1982-08-26 | Hitachi Ltd | Data input equipment for logical circuit |
-
1983
- 1983-06-10 JP JP8961683U patent/JPS59195846U/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5177040U (en) * | 1974-12-12 | 1976-06-17 | ||
| JPS57138220A (en) * | 1981-02-20 | 1982-08-26 | Hitachi Ltd | Data input equipment for logical circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0445305Y2 (en) | 1992-10-26 |
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