JPS6072018U - Differential amplifier negative feedback circuit - Google Patents

Differential amplifier negative feedback circuit

Info

Publication number
JPS6072018U
JPS6072018U JP16273483U JP16273483U JPS6072018U JP S6072018 U JPS6072018 U JP S6072018U JP 16273483 U JP16273483 U JP 16273483U JP 16273483 U JP16273483 U JP 16273483U JP S6072018 U JPS6072018 U JP S6072018U
Authority
JP
Japan
Prior art keywords
negative feedback
differential amplifier
stage
feedback circuit
amplifier negative
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16273483U
Other languages
Japanese (ja)
Inventor
木本 雄二
Original Assignee
三洋電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三洋電機株式会社 filed Critical 三洋電機株式会社
Priority to JP16273483U priority Critical patent/JPS6072018U/en
Publication of JPS6072018U publication Critical patent/JPS6072018U/en
Pending legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の差動増幅器の負帰還回路、第2図及び第
3図は本考案の同回路の実施例を示す。 主な図番の説明、1.L L 2UJLLl−0,31
,3え・・・差動対、4.5.4’ 、 5’・・・入
力端子、6,7・・・エミッタフォロア段、8,9・・
・出力端子、1011.18.几51,51・・・フィ
ルタ回路、11・・・差動段。
FIG. 1 shows a conventional negative feedback circuit for a differential amplifier, and FIGS. 2 and 3 show an embodiment of the same circuit according to the present invention. Explanation of main figure numbers, 1. L L 2UJLLl-0,31
, 3... Differential pair, 4.5.4', 5'... Input terminal, 6, 7... Emitter follower stage, 8, 9...
・Output terminal, 1011.18.几51, 51...filter circuit, 11...differential stage.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 複数の差動対を縦続接続し、後段より前段に負帰還を施
す負帰還ループを設けた差動増幅器において、2段目以
降の差動対の入力側と3段目以降の差動対又は増幅段の
出力側との間に負帰還ループ用のフィルタ回路を接続し
、前記構成素子を同一集積回路上に設けたことを特徴と
する差動増幅器の負帰還回路。
In a differential amplifier that connects multiple differential pairs in cascade and provides a negative feedback loop that provides negative feedback from the subsequent stage to the previous stage, the input side of the second stage differential pair and the third stage differential pair or 1. A negative feedback circuit for a differential amplifier, characterized in that a filter circuit for a negative feedback loop is connected between an output side of an amplification stage, and the constituent elements are provided on the same integrated circuit.
JP16273483U 1983-10-20 1983-10-20 Differential amplifier negative feedback circuit Pending JPS6072018U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16273483U JPS6072018U (en) 1983-10-20 1983-10-20 Differential amplifier negative feedback circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16273483U JPS6072018U (en) 1983-10-20 1983-10-20 Differential amplifier negative feedback circuit

Publications (1)

Publication Number Publication Date
JPS6072018U true JPS6072018U (en) 1985-05-21

Family

ID=30357271

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16273483U Pending JPS6072018U (en) 1983-10-20 1983-10-20 Differential amplifier negative feedback circuit

Country Status (1)

Country Link
JP (1) JPS6072018U (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62127113U (en) * 1986-02-03 1987-08-12
JP2011155368A (en) * 2010-01-26 2011-08-11 Hitachi Ltd Peaking circuit, peaking circuit control method, waveform measurement apparatus, and information processing apparatus

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5847305A (en) * 1981-09-16 1983-03-19 Toshiba Corp Multistage differential amplifying circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5847305A (en) * 1981-09-16 1983-03-19 Toshiba Corp Multistage differential amplifying circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62127113U (en) * 1986-02-03 1987-08-12
JP2011155368A (en) * 2010-01-26 2011-08-11 Hitachi Ltd Peaking circuit, peaking circuit control method, waveform measurement apparatus, and information processing apparatus

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