JPH0445305Y2 - - Google Patents

Description

[Detailed explanation of the invention] (a) Industrial application field The present invention relates to an input circuit of a frequency divider circuit, for example.
The present invention relates to an input circuit suitable for a programmable divider of a PLL synthesizer. (b) Prior art Figures 1 to 3 show input circuits of conventional frequency divider circuits, with Figure 1 showing an example of a logic level configuration, Figure 2 an example of a CMOS configuration, and Figure 3. is an example of an EDMOS configuration consisting of an enhancement type driver MOS and a depletion type load MOS. As shown in the figure, the first stage inverter 2 connected to the input terminal 1 has a built-in feedback resistor 3 to amplify the input analog signal, and is used with self-biasing and capacitive coupling. Thereafter, the signal is guided to a frequency dividing circuit 6 via several stages of inverters 4 and 5 for amplification and waveform shaping. In this conventional input circuit, the voltage gain characteristic with respect to the frequency of the input signal is approximately constant up to a high frequency band, as shown in FIG. 4, and thereafter the gain decreases as the frequency increases. Therefore, in order to operate the frequency divider circuit 6 normally, it is sufficient to apply an input signal so that the input voltage characteristics shown in FIG. 5 are obtained. However, in reality, noise jumps into the input circuit's power supply and signal path, so the input voltage characteristics are
It is not enough just to do as shown in the diagram. for example,
In Figures 6 to 8, 2sin is used as the input signal.
Suppose that a sine wave S of (ωt + θ), sin (ωt + θ), sin2 (ωt + θ) is input, and after a time delay of θ, pulse noise with an amplitude υ _O based on the logic signal R jumps into the input signal. In FIG. 6, since the noise amplitude υ _O does not reach the threshold voltage V _T of the input circuit, it has no effect on the amplified and shaped signal P _O. However,
As shown in Fig. 7, when the input amplitude is small even if the frequencies are equal, the noise amplitude υ _O reaches the threshold voltage V _T , so a spike occurs in the amplified and shaped signal P _O , and therefore, The frequency divider circuit malfunctions. Furthermore, as shown in FIG. 8, when the input amplitude is equal but the frequency is high, the noise amplitude υ _O does not reach the threshold voltage _VT , so the signal after amplification and shaping is not affected. In this way, input circuits and frequency divider circuits with good high frequency characteristics of voltage gain will malfunction due to pulse noise in the low frequency range, so in order for the frequency divider circuit to actually operate normally, it is necessary to
Input voltage must be increased. By the way, in a radio receiver using a PLL synthesizer, the local oscillation frequency is 65 to 120 MHz for the FM band and 2 to 26 MHz for the SW band.
is required, and if the input circuit of the programmable divider is used for both the FM band and the SW band, the frequency range used will be quite wide, from 2 to 120 MHz. Therefore, in order to maintain good characteristics up to the high frequency range around 120MHz, in the low frequency range below a few + MHz, the input voltage characteristics must be set as shown in Figure 9 in order to avoid the effects of pulse noise etc. as mentioned above. There were some unavoidable flaws. (c) Purpose of the invention The purpose of the invention is to prevent deterioration of input voltage characteristics in the low frequency range and to realize an input circuit for a frequency divider circuit that has good input voltage characteristics over a wide frequency range. When applied to a PLL radio receiver, it allows the use of a common input circuit for different bands. (d) Configuration of the invention: an amplifier circuit that amplifies an input signal; a first inverter stage connected to the output end of the amplifier circuit; and a first inverter stage connected to the output end of the amplifier circuit. a second inverter stage having different gain frequency characteristics; a cutoff circuit that cuts off signal transmission in either one of the first and second inverter stages according to a control signal; This circuit is constructed of a logic circuit which inputs the outputs of the two inverter stages and commonly applies an output signal based on either one of the first and second inverter stages as an input signal to the frequency dividing circuit. (E) Embodiment FIG. 10 is a circuit diagram showing an embodiment in which the input circuit of the frequency divider circuit according to the present invention is configured using EDMOS. An amplifier circuit 9 consisting of the following is connected, and the output signal of this amplifier circuit 9 is transmitted to an inverter 10 at the next stage. Two systems of inverter stages 11 and 12 are connected to the output end of the inverter 10, and the signals transmitted here are divided. In this embodiment, the first and second inverter stages 1
1 and 12 are connected to one stage of inverters 13 and 14, respectively.
These inverter stages have different voltage gain frequency characteristics.
That is, the voltage gain of the first inverter stage 11 is set to have good high frequency characteristics as shown in FIG. 11, and the frequency characteristics of the voltage gain of the second inverter stage 12 are set as shown in FIG. , is set lower than that of the first inverter stage 11 . Specifically, the frequency characteristics of the inverter 14 may be made lower than those of the inverter 13 by increasing the impedance of the MOSFET constituting the inverter 14 or by adding a capacitance to its gate. By the way, in Fig. 10, 15 is connected to the output terminal of each inverter stage 13 and 14.
Consisting of MOSFETs 16 and 17 and an inverter 18, the inverter 13
and 14 output signals at a predetermined level to cut off signal transmission to the inverter stage. Further, 19 indicates MOSFETs 20 and 21 that input the output signals of the first and second inverter stages 11 and 12 , respectively, and a load MOSFET 22.
The output signal of the NOR gate 19 is input to the frequency dividing circuit via the inverter 23 connected later. Incidentally, when comparing the scope of the utility model registration claim and FIG. Correspondingly,
The first of MOSFETs 20, 22 and inverter 23
The second inverter stage 12 corresponds to the second next stage amplifier circuit, and the MOSFETs 21,
22 and inverter 23 constitute a second output circuit. Next, a case will be described in which this embodiment is used as an input circuit of a frequency dividing circuit of a PLL radio receiver. First, in order to receive the SW band, the control signal is
When FM is set to “L”, the cutoff circuit 15
MOSFET 17 is turned off and MOSFET 16 is turned on, so the transmission of the output signal of inverter 13 is cut off, and it becomes "L" level, and NOR gate 1
MOSFET 20 of No. 9 is always turned off in this state. Therefore, the output signal of the inverter 14 is
It is led out to the frequency dividing circuit via the MOSFET 21 of the NOR gate 19 and the inverter 23. Here, although the frequency band of the SW band is lower than that of the FM band, the frequency characteristics of the voltage gain of the second inverter stage 12 are set low as shown in FIG. Even if it occurs, it will be removed by the inverter stage 12 . Therefore, unlike the conventional example shown by the broken line a in FIG.
As shown by the solid line c, the input voltage characteristics are good even in the low frequency range. Here, when receiving the FM band, if the second inverter stage 12 is used, it is necessary to have input voltage characteristics as shown by the broken line b in FIG.
When receiving the FM band, MOSFET 1 of the cutoff circuit 15 is set to "H" for the control signal FM.
6 is turned off and MOSFET 17 is turned on. Therefore, the output signal of the inverter 14 is cut off and fixed at the "L" level, and the output signal of the NOR gate 19 is
MOSFET 21 is always off in this state. Therefore, the output signal of inverter 13 is NOR
MOSFET 20 of gate 19 and inverter 23
It will be led out to the frequency dividing circuit via. In this case, the frequency characteristics of the voltage gain in the first inverter stage 11 are set to have good high frequency characteristics as shown in FIG. Becomes good. In this manner, when applied to a PLL radio receiver, if the control signal is switched depending on the band, the input circuit of the frequency divider circuit can be used for different bands. By the way, in this embodiment, the first and second
Although the inverter stage is configured with one stage inverter, it is also possible to use multiple stages of inverters. Furthermore, an even number of inverter stages may be inserted between the cutoff circuit 15 and the NOR gate 19 . Furthermore, inverters 10 and 23 are not necessarily required and can be omitted. (f) Effects of the invention The input circuit of the frequency divider circuit according to the invention divides the inverter stage that amplifies and shapes the input signal into two systems, and selects the inverter stage according to the control signal, so it can handle a wide range of frequencies. Good input voltage frequency characteristics can be obtained over a range, and when applied to a radio receiver, in different bands,
The input circuit of the frequency divider circuit can be shared.

[Brief explanation of the drawing]

Figures 1 to 3 are circuit diagrams showing conventional examples of input circuits of frequency divider circuits, Figure 4 is a characteristic diagram showing voltage gain characteristics of the conventional example, and Figure 5 is ideal input voltage characteristics of the conventional example. FIGS. 6 to 8 are waveform diagrams for explaining the conventional example, FIG. 9 is a characteristic diagram showing the actual input voltage characteristics of the conventional example, and FIG. 10 is a characteristic diagram showing the actual input voltage characteristics of the conventional example. 11 and 12 are characteristic diagrams showing the voltage gain characteristics of each of the first and second inverter stages of this embodiment, and FIG. 13 is a characteristic diagram showing the input voltage characteristics of this embodiment. It is. Explanation of main drawing numbers, 1, 7...Input terminal, 2,
4, 5, 10, 13, 14, 23... Inverter, 6... Frequency divider circuit, 8... Feedback resistor, 9... Amplifier circuit, 11 ... First inverter stage, 12 ...
Second inverter stage, 15 ... Cutoff circuit, 19 ...
…NOR gate.

Claims (1)

[Scope of utility model registration request] an input terminal to which a first signal having a first local oscillation frequency or a second signal having a second local oscillation frequency different from the first local oscillation frequency is commonly applied; and an input terminal connected to the input terminal; a first-stage amplifier circuit that includes a feedback resistor and commonly amplifies the first signal or the second signal; and a first-stage amplifier circuit that is connected to the output side of the first-stage amplifier circuit, and that the first signal is applied to the input terminal. a first next-stage amplifier circuit for removing noise superimposed on the amplified signal of the first-stage amplifier circuit; and a first next-stage amplifier circuit connected to the output of the first next-stage amplifier circuit; A first output circuit that outputs an amplified signal is connected to the output side of the first stage amplifier circuit, and eliminates noise superimposed on the amplified signal of the first stage amplifier circuit when the second signal is applied to the input terminal. connected to a second next-stage amplifier circuit for removing and an output of the second next-stage amplifier circuit,
a second output circuit that outputs the amplified signal of the second next-stage amplifier circuit; and a second output circuit that is connected to the outputs of the first next-stage amplifier circuit and the second next-stage amplifier circuit, and that outputs the amplified signal of the second next-stage amplifier circuit; a cutoff circuit to which a control signal for selecting the second signal is applied, and the first next-stage amplifier circuit has a voltage gain frequency characteristic according to a local oscillation frequency of the first signal. The second next-stage amplifier circuit has a voltage gain frequency characteristic according to the local oscillation frequency of the second signal, and the cutoff circuit has a voltage gain frequency characteristic for selecting the first signal. When a control signal is applied, the output path of the second next-stage amplifier circuit is cut off, the second output circuit is made inactive, and a control signal is applied for selecting the second signal. When the first
An input circuit for a frequency divider circuit, characterized in that the output path of the next-stage amplifier circuit is cut off, and the first output circuit is rendered inoperable.