JPS5919288A - 仮想記憶制御方式 - Google Patents

仮想記憶制御方式

Info

Publication number
JPS5919288A
JPS5919288A JP57127877A JP12787782A JPS5919288A JP S5919288 A JPS5919288 A JP S5919288A JP 57127877 A JP57127877 A JP 57127877A JP 12787782 A JP12787782 A JP 12787782A JP S5919288 A JPS5919288 A JP S5919288A
Authority
JP
Japan
Prior art keywords
address
segment
virtual address
type
virtual
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57127877A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0320777B2 (enExample
Inventor
Masaharu Nozaki
野崎　正治
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP57127877A priority Critical patent/JPS5919288A/ja
Publication of JPS5919288A publication Critical patent/JPS5919288A/ja
Publication of JPH0320777B2 publication Critical patent/JPH0320777B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP57127877A 1982-07-22 1982-07-22 仮想記憶制御方式 Granted JPS5919288A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57127877A JPS5919288A (ja) 1982-07-22 1982-07-22 仮想記憶制御方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57127877A JPS5919288A (ja) 1982-07-22 1982-07-22 仮想記憶制御方式

Publications (2)

Publication Number Publication Date
JPS5919288A true JPS5919288A (ja) 1984-01-31
JPH0320777B2 JPH0320777B2 (enExample) 1991-03-20

Family

ID=14970847

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57127877A Granted JPS5919288A (ja) 1982-07-22 1982-07-22 仮想記憶制御方式

Country Status (1)

Country Link
JP (1) JPS5919288A (enExample)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60204048A (ja) * 1984-03-28 1985-10-15 Hitachi Ltd 仮想記憶方式
JPS621048A (ja) * 1985-06-04 1987-01-07 Nec Corp 仮想記憶システム
JPS62237547A (ja) * 1986-04-09 1987-10-17 Hitachi Ltd アドレス変換方式

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60204048A (ja) * 1984-03-28 1985-10-15 Hitachi Ltd 仮想記憶方式
JPS621048A (ja) * 1985-06-04 1987-01-07 Nec Corp 仮想記憶システム
JPS62237547A (ja) * 1986-04-09 1987-10-17 Hitachi Ltd アドレス変換方式

Also Published As

Publication number Publication date
JPH0320777B2 (enExample) 1991-03-20

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