JPS59192838U - semiconductor equipment - Google Patents

semiconductor equipment

Info

Publication number
JPS59192838U
JPS59192838U JP1983087831U JP8783183U JPS59192838U JP S59192838 U JPS59192838 U JP S59192838U JP 1983087831 U JP1983087831 U JP 1983087831U JP 8783183 U JP8783183 U JP 8783183U JP S59192838 U JPS59192838 U JP S59192838U
Authority
JP
Japan
Prior art keywords
semiconductor device
metal
semiconductor equipment
semiconductor
supporting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1983087831U
Other languages
Japanese (ja)
Inventor
保敏 栗原
皆川 忠
八野 耕明
和久井 陽行
大上 三千男
Original Assignee
株式会社日立製作所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社日立製作所 filed Critical 株式会社日立製作所
Priority to JP1983087831U priority Critical patent/JPS59192838U/en
Publication of JPS59192838U publication Critical patent/JPS59192838U/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612Auxiliary members for layer connectors, e.g. spacers

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図ないし第3図は本考案の一実施例の混成ICのそ
れぞれ斜視図、系統図、断面図、第4図は本考案と従来
のヒートサイクル数と熱抵抗の関係を示すグラフ、第5
図は本考案の他の実施例の要部断面図、第6図a、  
bは本考案に係る金属部材の変形例を示す斜視図である
1 to 3 are respectively a perspective view, a system diagram, and a sectional view of a hybrid IC according to an embodiment of the present invention. FIG. 4 is a graph showing the relationship between the number of heat cycles and thermal resistance of the present invention and the conventional one. 5
The figures are sectional views of main parts of other embodiments of the present invention, Fig. 6a,
b is a perspective view showing a modification of the metal member according to the present invention;

Claims (1)

【実用新案登録請求の範囲】 半導体基体の支持用金属支持部材と、この金属部材上に
金属ろうを用いて接着された前記半導体基体とを含む半
導体装置において、 前記金属ろう中に埋設されるようにループ状金属部材を
介装させたことを特徴とする半導体装置。
[Claims for Utility Model Registration] A semiconductor device including a metal supporting member for supporting a semiconductor substrate, and the semiconductor substrate bonded onto the metal member using a metal solder, wherein the semiconductor device is embedded in the metal solder. A semiconductor device characterized in that a loop-shaped metal member is interposed in the semiconductor device.
JP1983087831U 1983-06-10 1983-06-10 semiconductor equipment Pending JPS59192838U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1983087831U JPS59192838U (en) 1983-06-10 1983-06-10 semiconductor equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1983087831U JPS59192838U (en) 1983-06-10 1983-06-10 semiconductor equipment

Publications (1)

Publication Number Publication Date
JPS59192838U true JPS59192838U (en) 1984-12-21

Family

ID=30217744

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1983087831U Pending JPS59192838U (en) 1983-06-10 1983-06-10 semiconductor equipment

Country Status (1)

Country Link
JP (1) JPS59192838U (en)

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