JPS59191197A - Memory tester - Google Patents

Abstract

PURPOSE:To conduct a simple test taking the data polarity in the memory element in consideration by providing an exclusive logical circuit to which readout data from a memory for data scramble and data from a data generator are inputted. CONSTITUTION:Data outputted from a data generator 21 are of N bits. A data scramble file 22 is constituted of an RAM and can store two words of data in which one word is one bit. Output data (one bit) from the data scramble file 22 and corresponding data from the data generator 21 are inputted to each of exclusive logical sum circuits 23-1-23-N. Output data from the exclusive logical sum circuit 23-1 and corresponding bit from the data generator 21 are inputted to a multiplexer 24, and one of the data is outputted from the multiplexer 24 according to a controlling input. An output from the multiplexer 24 becomes input data Din and expected value data.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a memory tester that can easily test a memory by taking into account data polarity of the memory.

[Prior art and problems]

Dynamic memory differs from static memory in the structure of its memory cells, and is basically composed of one transistor and one capacitor. Since data is determined by the amount of charge in the capacitor, data may be destroyed due to leakage. Therefore, the dynamic memory requires rewriting two rows of 51J flashes within a certain period of time. Because of this cell structure, tests that take into account interference between cells are required. When performing such a test, it is necessary to create a test pattern that matches the internal topology of the memory.

Internal topology includes memory array, address
Includes decoding, data polarity, etc.

Next, the internal topology of the memory will be briefly explained with reference to FIGS. 1 to 5. FIG. 1 shows the arrangement of chips and memory cells when bin 1 of the dual-in package is placed at the upper right. In FIG. 1, the ROW decoder is placed on the left side of the cell, and the COLUMN decoder is placed parallel to the cell. Figure 2 shows the address
This shows decoding. Therefore, A, (ROW)
Adjacent cells will not be selected sequentially even if they are addressed consecutively using a binary address with A7 (COLUMN) as the least significant bit and A7 (COLUMN) as the most significant bit. In FIG. 2, as shown in FIG. 3, A. (ROW) is the least significant bit, AO(C
The order in which cells are addressed when sequentially addressed using binary addresses with OLUMN) as the most significant bit is shown. In the memory of FIG. 2, the sense amplifier is placed in the center of the bit line, so that half of the data in the memory matrix is inverted with respect to the external data. FIG. 4 is a diagram showing the relationship among addresses, input data, memory cell data, and output data. When performing a test with all cells of the memory in a charged state of "1", it is necessary to refer to the data polarity shown in FIG. FIG. 5 shows the actual layout of cells within the memory.

When testing for interference between adjacent cells, it is necessary to refer to the layout of FIG. 5.

Conventional memory testers have an address scrambling function that takes address decoding topology into consideration and converts external addresses into actual physical addresses. However, when performing tests that take data polarity into consideration, It was necessary to provide an input section conversion circuit and an output section inverse conversion circuit.6 Figures 6 to 8 explain conventional tests that take data polarity into consideration. FIG. 7 is a diagram showing an example of a polarity conversion circuit, FIG. 7 is a diagram showing an input part inversion circuit, and FIG. 8 is a diagram showing an output part inversion circuit. 6 to 1, 11 to 15 indicate exclusive OR circuits. Output data from the tester is added to the input section inverse conversion circuit in FIG. 7, and from the input section inversion circuit. The output data of is input to the memory element as input data Din to the memory element.The output data Dout from the memory element is input to the output section inversion circuit shown in FIG. is the input data to the tester.The tester compares the output data from the tester with the input data to the tester.

Perform memory tests.

In the conventional test method as explained in FIGS. 6 to 8, it is necessary to change the input section inverse conversion circuit and the output direction inversion circuit every time the data polarity conversion circuit inside the memory element changes.

[Purpose of the invention]

The present invention is based on the above considerations.

It is an object of the present invention to provide a memory tester capable of performing a test considering one data polarity without changing the hardware configuration even when data polarity conversion circuits in a memory element are different.

[Structure of the invention]

Therefore, the memory tester of the present invention includes an address generator, a data generator, and an address generator for converting the address data output from the address generator.
In a memory tester equipped with a memory for scrambling, the address and
It is characterized by providing a memory for data scrambling into which data is input as an address signal, and an exclusive OR circuit into which data read from the memory for data scrambling and data from the data generator are input. That is.

[Embodiments of the invention]

Hereinafter, the present invention will be explained with reference to the drawings.

FIG. 9 is a block diagram of one embodiment of the present invention, and FIG. 10 is a flowchart illustrating a test using the memory tester of the present invention.

In FIG. 9, 16 is an address generator, 17 is an X scramble file, 18 is a Y scramble file, 19 and 20 are multiplexers, 21 (l''j: data generator, 22 is a data scramble file, 23
-1 to 23-N indicate exclusive OR circuits, and 24 indicates a multiplexer, respectively.

The address data output from the address generator 16 consists of n bits, of which the upper n/2 bits (X address) are input to the X scramble file 17, and the lower n/2 bits (X address ) is input to the X scramble file 18. X scramble
The file 17 and the Y scramble O file 18 each consist of 3 AM, and one word is n/
It can accommodate 2n/2 words of 2-bit data. The contents of the X scramble file 17 and the X scramble file 18 can be rewritten.
The X scramble refile 17 converts the X address output from the address generator 16 into an actual physical X address in the memory, and the X scramble file 1
8 converts the X address output from the address generator 16 into an actual physical X address of the memory. X address data from the address generator 16 and address data output from the X scramble file 17 are input to the multiplexer 19, and either one of them is output from the multiplexer +j19 according to the control input Output.

Similarly, the multiplexer 18 receives the X address data from the address generator 16 and the address data output from the It is output from 20. Note that the X address corresponds to the COL UMN address, and the
It may be considered that it corresponds to an OW address.

The data output from the data generator 21 is Nbi, l-/
It is of the following configuration. The data scramble file 22 is composed of a RAM and can accommodate 2n words of data each word having 1 bit. The contents of the data scramble file 22 can be rewritten. The data scramble file 22 corresponds to the exclusive OR circuit 13 in FIG. Each of the exclusive OR circuits 23-1 to 23-N receives output data (
1 bit) and the corresponding bit from data generator 21 are input. The multiplexer 24 receives the output data from the exclusive OR circuit 23-1 and the corresponding bit from the data generator 22.

Then, one of the data is outputted from the multiplexer 24 according to the control input. multiplexer 2
The output from 4 becomes input data Din and expected value data to the memory element.

FIG. 10 is a flowchart illustrating the memory test of the present invention. When testing the memory, check whether it is necessary to consider data polarity or not. If no, the data as created by the program, that is, the output data of the data generator 21, is stored as is in the memory. This is input data to the element. If Yes, create a data conversion daple and dump it into the data scramble file 22. Then, the data scramble file 22 and exclusive OR circuit (EXR circuit)
Input data Din and expected value data are created by , and these are given to the pin electronics section.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, it is possible to easily perform a test that takes into account the data polarity of a memory element.

[Brief explanation of drawings]

Figure 1 shows the arrangement of chips and memory cells;
3 shows the relationship between cell numbers, column addresses, and row addresses. FIG. 4 shows the relationship between addresses, input data, memory cell data, and output data. Figure 5 is a diagram showing the layout of cells;
Figure 6 shows an example of the data polarity conversion circuit in the memory register, Figure 7 shows the input part conversion circuit, and Figure 8 shows the output part inverse conversion circuit. FIG. 9 is a block diagram of one embodiment of the present invention, and FIG. 10 is a flowchart illustrating a test using the inventive memory tester. 11 to 15... Exclusive OR circuit, 16... Address generator, 17... X scramble file,
18...X scramble file% 19 and 20.
...Multiplexer, 21...Data generator%22.
...Data scramble file %23-i 23-N...Exclusive OR circuit, 24...Multiplexer. Patent Applicant Usatsuk Electronic Industry Co., Ltd. Representative Patent Attorney Kyotani 4 Departments 1 Elderly and Young 1 Figure 3 Figure 4 Figure 5 Figure 6 Off Figure '''X'8 Figure Output Type Dout

Claims (1)

[Claims] In a memory tester equipped with an address generator, a data generator, and an address scramble memory for converting the address data output from the address generator, the address data from the address generator is The present invention is characterized by providing a memory for data scrambling which is input as an address signal, and an exclusive OR circuit to which data read from the memory for data scrambling and data from the data generator are input. memory tester.