JPS59189234U - Jig for semiconductor manufacturing - Google Patents

Jig for semiconductor manufacturing

Info

Publication number
JPS59189234U
JPS59189234U JP8375583U JP8375583U JPS59189234U JP S59189234 U JPS59189234 U JP S59189234U JP 8375583 U JP8375583 U JP 8375583U JP 8375583 U JP8375583 U JP 8375583U JP S59189234 U JPS59189234 U JP S59189234U
Authority
JP
Japan
Prior art keywords
jig
semiconductor manufacturing
semiconductor
semiconductor wafer
thickness
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8375583U
Other languages
Japanese (ja)
Inventor
杉本 良樹
Original Assignee
日本電気ホームエレクトロニクス株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気ホームエレクトロニクス株式会社 filed Critical 日本電気ホームエレクトロニクス株式会社
Priority to JP8375583U priority Critical patent/JPS59189234U/en
Publication of JPS59189234U publication Critical patent/JPS59189234U/en
Pending legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

す    第1図は従来のサセプタの要部の平面図であ
る。 第2図は第1図のサセプタの■−■線に沿う断面図であ
る。第3図はこの考案の一実施例のサセプタの要部断面
図である。 1・・・・・・サセプタ本体、2・・・・・・炭化シリ
コン層、3・・・・・・凹所、4・・・・・・半導体ウ
ェーハ、5・・・・・・エピタキシャル層、6・・・・
・・オリエンテーションフラッ)OF、7・・・・・・
隙間、9・・・・・・多結晶(シリコン)層。
FIG. 1 is a plan view of the main parts of a conventional susceptor. FIG. 2 is a cross-sectional view of the susceptor shown in FIG. 1 taken along the line ■-■. FIG. 3 is a sectional view of a main part of a susceptor according to an embodiment of this invention. DESCRIPTION OF SYMBOLS 1... Susceptor main body, 2... Silicon carbide layer, 3... Recess, 4... Semiconductor wafer, 5... Epitaxial layer , 6...
...Orientation flash) OF, 7...
Gap, 9... Polycrystalline (silicon) layer.

Claims (1)

【実用新案登録請求の範囲】 半導体ウェーハを載置し、この半導体ウェーハ上に気相
成長によって成膜を行なう半導体製造用治具において、 その表面に成膜予定の半導体材料より多結晶層を30μ
以上の厚さに形成したことを特徴とする半導体製造用治
具。
[Claims for Utility Model Registration] In a jig for semiconductor manufacturing in which a semiconductor wafer is placed and a film is formed on the semiconductor wafer by vapor phase growth, a polycrystalline layer of 30 μm from the semiconductor material to be deposited is formed on the surface of the jig.
A jig for semiconductor manufacturing, characterized in that the jig is formed to a thickness of at least the above thickness.
JP8375583U 1983-05-31 1983-05-31 Jig for semiconductor manufacturing Pending JPS59189234U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8375583U JPS59189234U (en) 1983-05-31 1983-05-31 Jig for semiconductor manufacturing

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8375583U JPS59189234U (en) 1983-05-31 1983-05-31 Jig for semiconductor manufacturing

Publications (1)

Publication Number Publication Date
JPS59189234U true JPS59189234U (en) 1984-12-15

Family

ID=30213713

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8375583U Pending JPS59189234U (en) 1983-05-31 1983-05-31 Jig for semiconductor manufacturing

Country Status (1)

Country Link
JP (1) JPS59189234U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0855803A (en) * 1994-07-28 1996-02-27 Applied Materials Inc Thin film preparation

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0855803A (en) * 1994-07-28 1996-02-27 Applied Materials Inc Thin film preparation

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