JPS59186358A - Semiconductor device with built-in resistor - Google Patents
Semiconductor device with built-in resistorInfo
- Publication number
- JPS59186358A JPS59186358A JP6111683A JP6111683A JPS59186358A JP S59186358 A JPS59186358 A JP S59186358A JP 6111683 A JP6111683 A JP 6111683A JP 6111683 A JP6111683 A JP 6111683A JP S59186358 A JPS59186358 A JP S59186358A
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- film
- nitride film
- substrate
- oxide film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 12
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 11
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 11
- 229920005591 polysilicon Polymers 0.000 claims description 10
- 239000012535 impurity Substances 0.000 abstract description 8
- 238000009792 diffusion process Methods 0.000 abstract description 6
- 229910052796 boron Inorganic materials 0.000 abstract description 4
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 4
- 238000005229 chemical vapour deposition Methods 0.000 abstract description 3
- 238000010438 heat treatment Methods 0.000 abstract description 3
- 150000004767 nitrides Chemical class 0.000 abstract 3
- 238000000151 deposition Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 abstract 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- HXNZTJULPKRNPR-UHFFFAOYSA-N borinine Chemical compound B1=CC=CC=C1 HXNZTJULPKRNPR-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
【発明の詳細な説明】
(イ)産業上の利用分野
本発明は抵抗体内蔵半導体装置、特にポリシリコン抵抗
体を内蔵した半導体装置の改良に関する。DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to improvements in semiconductor devices with built-in resistors, particularly semiconductor devices with built-in polysilicon resistors.
(ロ)従来技術
従来の抵抗体内蔵半導体装置は第1図の如く、N型の半
導体基板(1)と、基板(1)表面に2重拡散して形成
したP型のベース領域(2)とN 型のエミッタ領域(
3)と、基板(1)表面を被覆するシリコン酸化膜(4
)と、シリコン酸化膜(4)上に付着されたポリシリコ
ン層より成る抵抗体(5)と、抵抗体(5)および各領
域(2)(3)を接続する、蒸着アルミニウムの電極(
6)より構成されている。(B) Prior art As shown in Figure 1, a conventional semiconductor device with a built-in resistor has an N-type semiconductor substrate (1) and a P-type base region (2) formed by double diffusion on the surface of the substrate (1). and N type emitter region (
3) and a silicon oxide film (4) covering the surface of the substrate (1).
), a resistor (5) consisting of a polysilicon layer deposited on a silicon oxide film (4), and electrodes (of vapor-deposited aluminum) connecting the resistor (5) and the regions (2) and (3).
6).
斯る半導体装置は半導体基板(1)に拡散抵抗を形成す
る構造に比べてPN接合分離に依らないので。Such a semiconductor device does not rely on PN junction separation, compared to a structure in which a diffused resistor is formed in the semiconductor substrate (1).
寄生効果が少なく安定した抵抗体を任意に形成できる利
点を有する。It has the advantage that a stable resistor with few parasitic effects can be formed arbitrarily.
しかしながら下地のシリコン酸化膜(4)には不純物拡
散によるリンやボロンが含まれ、これがトランジスタや
ICの製造中の熱処理でポリシリコン層内に入り込み、
抵抗値変動を発生する。However, the underlying silicon oxide film (4) contains phosphorus and boron due to impurity diffusion, which enters the polysilicon layer during heat treatment during the manufacture of transistors and ICs.
Generates resistance value fluctuations.
(ハ)発明の目的
本発明は斯点に鑑みてなされ、従来の欠点を除去した抵
抗体内蔵半導体装置を提供することにある。(c) Object of the Invention The present invention has been made in view of the above, and an object of the present invention is to provide a semiconductor device with a built-in resistor that eliminates the conventional drawbacks.
に)発明の構成
本発明に依る抵抗体内蔵半導体装置は第2図の如く、半
導体基板(ロ)と、基板(ロ)に形成された回路素子(
6)と、基板α力表面を被覆するシリコン酸化膜00と
、シリコン酸化膜(ト)上を被覆するシリコン窒化膜θ
→と、シリコン窒化膜αQ上に設けたボリンリコンより
成る抵抗体Q7)と、抵抗体θカおよび回路素子θ■を
接続する電極θ杓より構成されている。B) Structure of the Invention The semiconductor device with a built-in resistor according to the present invention, as shown in FIG.
6), a silicon oxide film 00 covering the surface of the substrate α, and a silicon nitride film θ covering the silicon oxide film (G).
→, a resistor Q7 made of borin silicon provided on a silicon nitride film αQ, and an electrode θ which connects the resistor θ and the circuit element θ■.
(−+→ 実施例
半導体基板OI)としてN型シリコン半導体基板を用い
、基板(11)に選択拡散によりP型のベース領域03
およびN 型のエミッタ領域04)を二重拡散して回路
素子(2)を形成する。なお回路素子(6)は上記した
トランジスタの他に集積回路でも良い。基板の)表面は
拡散等の熱処理で形成されるシリコン酸化膜qので被覆
されており、このシリコン酸化膜αつにはリンやボロン
等の不純物が含まれている。/リコン酸化膜(l上には
CVD法により約80OA厚のノリコン窒化膜OQが付
着され、更にその上にはCVD法により約400 OA
厚のポリシリコン層を付着する。ポリシリコン層は不純
物をトープしたものを用いるがあるいは後からイオン注
入して不純物をドープする。具体的には比抵抗を200
〜IKΩの範囲になる様にドープ量を設定する。Using an N-type silicon semiconductor substrate as (-+→ Example semiconductor substrate OI), a P-type base region 03 is formed on the substrate (11) by selective diffusion.
and N type emitter region 04) are double diffused to form a circuit element (2). Note that the circuit element (6) may be an integrated circuit other than the above-mentioned transistor. The surface (of the substrate) is covered with a silicon oxide film q formed by heat treatment such as diffusion, and this silicon oxide film q contains impurities such as phosphorus and boron. / Silicon oxide film (L) A silicon nitride film OQ with a thickness of about 80 OA is deposited on it by the CVD method, and a silicon nitride film OQ with a thickness of about 400 OA is deposited on it by the CVD method.
Deposit a thick polysilicon layer. The polysilicon layer is doped with impurities, or is doped with impurities by ion implantation later. Specifically, the specific resistance is 200
The doping amount is set to be in the range of ~IKΩ.
ポリシリコン層は所望の抵抗体形状にエツチングされ抵
抗体θηを形成する。電極(ト)はアルミニウムの蒸着
により形成し、ベースおよびエミッタ領域(1■α4)
上のコンタク(・孔を介してオーミック接触し、シリコ
ン窒化膜a#5上を延在させて抵抗体θ′7)の端部と
接続する。The polysilicon layer is etched into a desired resistor shape to form a resistor θη. The electrode (G) is formed by vapor deposition of aluminum, and the base and emitter regions (1■ α4)
The upper contact is connected to the end of the resistor θ'7 by making ohmic contact through the hole and extending over the silicon nitride film a#5.
斯上した構造に依ればシリコン酸化膜oOとポリシリコ
ンの抵抗体(17)とをシリコン窒化膜αGで分離する
ので、シリコン酸化膜α均に含まれていイ)リンおよび
ボロンの不純物は抵抗体α力中に入り込むおそれはない
。According to the above structure, the silicon oxide film oO and the polysilicon resistor (17) are separated by the silicon nitride film αG. There is no danger of it entering the body's alpha power.
(へ)効果
本発明に依ればポリシリコンの抵抗体α71は不純物に
よる抵抗値の変動を完全に防止でき、安定した抵抗値を
得られる。特に高抵抗の場合に不純物のドープ量が小さ
いので有効である。(f) Effects According to the present invention, the resistance value of the polysilicon resistor α71 can be completely prevented from changing due to impurities, and a stable resistance value can be obtained. This is particularly effective in the case of high resistance because the amount of impurity doped is small.
更にシリコン窒化膜◇Qで基板(ロ)表面を被覆してい
るので、基板(ロ)に組み込んだ回路素子(6)の安定
化も図れる。Furthermore, since the surface of the substrate (b) is coated with the silicon nitride film ◇Q, it is possible to stabilize the circuit element (6) incorporated in the substrate (b).
第1図は従来例を説明する断面図、第2図は本発明を説
明する断面図である。
主な図番の説明
α力は半導体基板、 (6)は回路素子、 (lF9は
シリコン酸化膜、αQはシリコン窒化膜、α力はポリシ
リコン層の抵抗体、 (至)は電極である。
第1図
第2図FIG. 1 is a sectional view illustrating a conventional example, and FIG. 2 is a sectional view illustrating the present invention. Explanation of main figure numbers α: semiconductor substrate, (6): circuit element, (IF9: silicon oxide film, αQ: silicon nitride film, α: polysilicon layer resistor, (to): electrode. Figure 1 Figure 2
Claims (1)
素子と前記基板表面を被覆するシリコン酸化膜と該シリ
コン酸化膜上に設けたシリコン窒化膜と該、ンリコン窒
化膜上に設けたポリシリコン抵抗体と該抵抗体と前記回
路素子を接続する電極とを具備することを特徴とする抵
抗体内蔵半導体装置。(]) - A conductive type semiconductor substrate, a circuit element formed on the substrate, a silicon oxide film covering the surface of the substrate, a silicon nitride film provided on the silicon oxide film, and a silicon nitride film provided on the silicon nitride film. 1. A semiconductor device with a built-in resistor, comprising a polysilicon resistor and an electrode connecting the resistor and the circuit element.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6111683A JPS59186358A (en) | 1983-04-06 | 1983-04-06 | Semiconductor device with built-in resistor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6111683A JPS59186358A (en) | 1983-04-06 | 1983-04-06 | Semiconductor device with built-in resistor |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS59186358A true JPS59186358A (en) | 1984-10-23 |
JPH0522393B2 JPH0522393B2 (en) | 1993-03-29 |
Family
ID=13161780
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6111683A Granted JPS59186358A (en) | 1983-04-06 | 1983-04-06 | Semiconductor device with built-in resistor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59186358A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0228364A (en) * | 1988-06-13 | 1990-01-30 | Matsushita Electron Corp | Manufacture of semiconductor device |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5552253A (en) * | 1978-10-11 | 1980-04-16 | Nec Corp | Semiconductor device |
-
1983
- 1983-04-06 JP JP6111683A patent/JPS59186358A/en active Granted
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5552253A (en) * | 1978-10-11 | 1980-04-16 | Nec Corp | Semiconductor device |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0228364A (en) * | 1988-06-13 | 1990-01-30 | Matsushita Electron Corp | Manufacture of semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
JPH0522393B2 (en) | 1993-03-29 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPS6322070B2 (en) | ||
JPH0630359B2 (en) | Bipolar transistor manufacturing method | |
JPS623576B2 (en) | ||
JP2605030B2 (en) | Quadrature bipolar transistor | |
JPH06318676A (en) | Manufacture of semiconductor device | |
JPS6135705B2 (en) | ||
GB1310412A (en) | Semiconductor devices | |
US4167804A (en) | Integrated circuit process compatible surge protection resistor | |
JPS59186358A (en) | Semiconductor device with built-in resistor | |
JP2752431B2 (en) | Method for manufacturing semiconductor device | |
US4772568A (en) | Method of making integrated circuit with pair of MOS field effect transistors sharing a common source/drain region | |
US3959810A (en) | Method for manufacturing a semiconductor device and the same | |
JP2000252290A (en) | Semiconductor device and its manufacture | |
JPS63133569A (en) | Semiconductor device | |
JPS63211760A (en) | Semiconductor device and manufacture thereof | |
JPS6058651A (en) | Semiconductor device | |
TWI270144B (en) | Semiconductor device and manufacturing method thereof | |
JPS6244430B2 (en) | ||
JPS5934145Y2 (en) | semiconductor equipment | |
JPS6084824A (en) | Manufacture of semiconductor device | |
JPS6020570A (en) | Manufacture of semiconductor device | |
JPH11251604A (en) | Semiconductor device | |
JPS6022828B2 (en) | Manufacturing method of semiconductor device | |
JPS588142B2 (en) | Semiconductor integrated circuit device and its manufacturing method | |
JPS5826177B2 (en) | Manufacturing method of semiconductor device |