JPS59186358A - Semiconductor device with built-in resistor - Google Patents

Semiconductor device with built-in resistor

Info

Publication number
JPS59186358A
JPS59186358A JP6111683A JP6111683A JPS59186358A JP S59186358 A JPS59186358 A JP S59186358A JP 6111683 A JP6111683 A JP 6111683A JP 6111683 A JP6111683 A JP 6111683A JP S59186358 A JPS59186358 A JP S59186358A
Authority
JP
Japan
Prior art keywords
resistor
film
nitride film
substrate
oxide film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6111683A
Other languages
Japanese (ja)
Other versions
JPH0522393B2 (en
Inventor
Tadahiko Tanaka
田中 忠彦
Tsutomu Nozaki
勉 野崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokyo Sanyo Electric Co Ltd
Sanyo Electric Co Ltd
Sanyo Denki Co Ltd
Original Assignee
Tokyo Sanyo Electric Co Ltd
Sanyo Electric Co Ltd
Sanyo Denki Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Sanyo Electric Co Ltd, Sanyo Electric Co Ltd, Sanyo Denki Co Ltd filed Critical Tokyo Sanyo Electric Co Ltd
Priority to JP6111683A priority Critical patent/JPS59186358A/en
Publication of JPS59186358A publication Critical patent/JPS59186358A/en
Publication of JPH0522393B2 publication Critical patent/JPH0522393B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0688Integrated circuits having a three-dimensional layout

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

PURPOSE:To prevent P and B impurities from entering into an Si resistor by a method wherein an Si oxide film and a poly Si resistor are isolated by an Si nitride film. CONSTITUTION:A circuit element 12 is formed by selectively performing a double diffusion of a P type base region 13 and an N<+> type emitter region 14 on an Si semiconductor substrate 11. An Si oxide film 15 which will be formed by performing a heat treatment such as a diffusion and the like is covered on the surface of the substrate 11, an Si nitride film is adhered on the film 15 by performing a CVD method, and a poly Si layer is adhered thereon. At this time, said poly Si layer is etched into the desired shape and a resistor 17 is formed. An electrode 18 is formed by vapor-depositing Al, an ohmic contact is obtained through the intermediaries of the contact holes of the base and emitter regions 13 and 14, it is connected to the end part of the resistor by extending it on an Si nitride film 11. As a result, the film 15 and the resistor 17 are isolated by the film 16, thereby enabling to prevent the P and B impurities contained in the film 15 from entering into the resistor 17.

Description

【発明の詳細な説明】 (イ)産業上の利用分野 本発明は抵抗体内蔵半導体装置、特にポリシリコン抵抗
体を内蔵した半導体装置の改良に関する。
DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to improvements in semiconductor devices with built-in resistors, particularly semiconductor devices with built-in polysilicon resistors.

(ロ)従来技術 従来の抵抗体内蔵半導体装置は第1図の如く、N型の半
導体基板(1)と、基板(1)表面に2重拡散して形成
したP型のベース領域(2)とN 型のエミッタ領域(
3)と、基板(1)表面を被覆するシリコン酸化膜(4
)と、シリコン酸化膜(4)上に付着されたポリシリコ
ン層より成る抵抗体(5)と、抵抗体(5)および各領
域(2)(3)を接続する、蒸着アルミニウムの電極(
6)より構成されている。
(B) Prior art As shown in Figure 1, a conventional semiconductor device with a built-in resistor has an N-type semiconductor substrate (1) and a P-type base region (2) formed by double diffusion on the surface of the substrate (1). and N type emitter region (
3) and a silicon oxide film (4) covering the surface of the substrate (1).
), a resistor (5) consisting of a polysilicon layer deposited on a silicon oxide film (4), and electrodes (of vapor-deposited aluminum) connecting the resistor (5) and the regions (2) and (3).
6).

斯る半導体装置は半導体基板(1)に拡散抵抗を形成す
る構造に比べてPN接合分離に依らないので。
Such a semiconductor device does not rely on PN junction separation, compared to a structure in which a diffused resistor is formed in the semiconductor substrate (1).

寄生効果が少なく安定した抵抗体を任意に形成できる利
点を有する。
It has the advantage that a stable resistor with few parasitic effects can be formed arbitrarily.

しかしながら下地のシリコン酸化膜(4)には不純物拡
散によるリンやボロンが含まれ、これがトランジスタや
ICの製造中の熱処理でポリシリコン層内に入り込み、
抵抗値変動を発生する。
However, the underlying silicon oxide film (4) contains phosphorus and boron due to impurity diffusion, which enters the polysilicon layer during heat treatment during the manufacture of transistors and ICs.
Generates resistance value fluctuations.

(ハ)発明の目的 本発明は斯点に鑑みてなされ、従来の欠点を除去した抵
抗体内蔵半導体装置を提供することにある。
(c) Object of the Invention The present invention has been made in view of the above, and an object of the present invention is to provide a semiconductor device with a built-in resistor that eliminates the conventional drawbacks.

に)発明の構成 本発明に依る抵抗体内蔵半導体装置は第2図の如く、半
導体基板(ロ)と、基板(ロ)に形成された回路素子(
6)と、基板α力表面を被覆するシリコン酸化膜00と
、シリコン酸化膜(ト)上を被覆するシリコン窒化膜θ
→と、シリコン窒化膜αQ上に設けたボリンリコンより
成る抵抗体Q7)と、抵抗体θカおよび回路素子θ■を
接続する電極θ杓より構成されている。
B) Structure of the Invention The semiconductor device with a built-in resistor according to the present invention, as shown in FIG.
6), a silicon oxide film 00 covering the surface of the substrate α, and a silicon nitride film θ covering the silicon oxide film (G).
→, a resistor Q7 made of borin silicon provided on a silicon nitride film αQ, and an electrode θ which connects the resistor θ and the circuit element θ■.

(−+→ 実施例 半導体基板OI)としてN型シリコン半導体基板を用い
、基板(11)に選択拡散によりP型のベース領域03
およびN 型のエミッタ領域04)を二重拡散して回路
素子(2)を形成する。なお回路素子(6)は上記した
トランジスタの他に集積回路でも良い。基板の)表面は
拡散等の熱処理で形成されるシリコン酸化膜qので被覆
されており、このシリコン酸化膜αつにはリンやボロン
等の不純物が含まれている。/リコン酸化膜(l上には
CVD法により約80OA厚のノリコン窒化膜OQが付
着され、更にその上にはCVD法により約400 OA
厚のポリシリコン層を付着する。ポリシリコン層は不純
物をトープしたものを用いるがあるいは後からイオン注
入して不純物をドープする。具体的には比抵抗を200
〜IKΩの範囲になる様にドープ量を設定する。
Using an N-type silicon semiconductor substrate as (-+→ Example semiconductor substrate OI), a P-type base region 03 is formed on the substrate (11) by selective diffusion.
and N type emitter region 04) are double diffused to form a circuit element (2). Note that the circuit element (6) may be an integrated circuit other than the above-mentioned transistor. The surface (of the substrate) is covered with a silicon oxide film q formed by heat treatment such as diffusion, and this silicon oxide film q contains impurities such as phosphorus and boron. / Silicon oxide film (L) A silicon nitride film OQ with a thickness of about 80 OA is deposited on it by the CVD method, and a silicon nitride film OQ with a thickness of about 400 OA is deposited on it by the CVD method.
Deposit a thick polysilicon layer. The polysilicon layer is doped with impurities, or is doped with impurities by ion implantation later. Specifically, the specific resistance is 200
The doping amount is set to be in the range of ~IKΩ.

ポリシリコン層は所望の抵抗体形状にエツチングされ抵
抗体θηを形成する。電極(ト)はアルミニウムの蒸着
により形成し、ベースおよびエミッタ領域(1■α4)
上のコンタク(・孔を介してオーミック接触し、シリコ
ン窒化膜a#5上を延在させて抵抗体θ′7)の端部と
接続する。
The polysilicon layer is etched into a desired resistor shape to form a resistor θη. The electrode (G) is formed by vapor deposition of aluminum, and the base and emitter regions (1■ α4)
The upper contact is connected to the end of the resistor θ'7 by making ohmic contact through the hole and extending over the silicon nitride film a#5.

斯上した構造に依ればシリコン酸化膜oOとポリシリコ
ンの抵抗体(17)とをシリコン窒化膜αGで分離する
ので、シリコン酸化膜α均に含まれていイ)リンおよび
ボロンの不純物は抵抗体α力中に入り込むおそれはない
According to the above structure, the silicon oxide film oO and the polysilicon resistor (17) are separated by the silicon nitride film αG. There is no danger of it entering the body's alpha power.

(へ)効果 本発明に依ればポリシリコンの抵抗体α71は不純物に
よる抵抗値の変動を完全に防止でき、安定した抵抗値を
得られる。特に高抵抗の場合に不純物のドープ量が小さ
いので有効である。
(f) Effects According to the present invention, the resistance value of the polysilicon resistor α71 can be completely prevented from changing due to impurities, and a stable resistance value can be obtained. This is particularly effective in the case of high resistance because the amount of impurity doped is small.

更にシリコン窒化膜◇Qで基板(ロ)表面を被覆してい
るので、基板(ロ)に組み込んだ回路素子(6)の安定
化も図れる。
Furthermore, since the surface of the substrate (b) is coated with the silicon nitride film ◇Q, it is possible to stabilize the circuit element (6) incorporated in the substrate (b).

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来例を説明する断面図、第2図は本発明を説
明する断面図である。 主な図番の説明 α力は半導体基板、 (6)は回路素子、 (lF9は
シリコン酸化膜、αQはシリコン窒化膜、α力はポリシ
リコン層の抵抗体、 (至)は電極である。 第1図 第2図
FIG. 1 is a sectional view illustrating a conventional example, and FIG. 2 is a sectional view illustrating the present invention. Explanation of main figure numbers α: semiconductor substrate, (6): circuit element, (IF9: silicon oxide film, αQ: silicon nitride film, α: polysilicon layer resistor, (to): electrode. Figure 1 Figure 2

Claims (1)

【特許請求の範囲】[Claims] (])−導電型の半導体基板と該基板に形成された回路
素子と前記基板表面を被覆するシリコン酸化膜と該シリ
コン酸化膜上に設けたシリコン窒化膜と該、ンリコン窒
化膜上に設けたポリシリコン抵抗体と該抵抗体と前記回
路素子を接続する電極とを具備することを特徴とする抵
抗体内蔵半導体装置。
(]) - A conductive type semiconductor substrate, a circuit element formed on the substrate, a silicon oxide film covering the surface of the substrate, a silicon nitride film provided on the silicon oxide film, and a silicon nitride film provided on the silicon nitride film. 1. A semiconductor device with a built-in resistor, comprising a polysilicon resistor and an electrode connecting the resistor and the circuit element.
JP6111683A 1983-04-06 1983-04-06 Semiconductor device with built-in resistor Granted JPS59186358A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6111683A JPS59186358A (en) 1983-04-06 1983-04-06 Semiconductor device with built-in resistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6111683A JPS59186358A (en) 1983-04-06 1983-04-06 Semiconductor device with built-in resistor

Publications (2)

Publication Number Publication Date
JPS59186358A true JPS59186358A (en) 1984-10-23
JPH0522393B2 JPH0522393B2 (en) 1993-03-29

Family

ID=13161780

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6111683A Granted JPS59186358A (en) 1983-04-06 1983-04-06 Semiconductor device with built-in resistor

Country Status (1)

Country Link
JP (1) JPS59186358A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0228364A (en) * 1988-06-13 1990-01-30 Matsushita Electron Corp Manufacture of semiconductor device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5552253A (en) * 1978-10-11 1980-04-16 Nec Corp Semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5552253A (en) * 1978-10-11 1980-04-16 Nec Corp Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0228364A (en) * 1988-06-13 1990-01-30 Matsushita Electron Corp Manufacture of semiconductor device

Also Published As

Publication number Publication date
JPH0522393B2 (en) 1993-03-29

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