JPS6084824A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6084824A
JPS6084824A JP58192378A JP19237883A JPS6084824A JP S6084824 A JPS6084824 A JP S6084824A JP 58192378 A JP58192378 A JP 58192378A JP 19237883 A JP19237883 A JP 19237883A JP S6084824 A JPS6084824 A JP S6084824A
Authority
JP
Japan
Prior art keywords
film
sic
resistance
beo
ion implantation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58192378A
Other languages
Japanese (ja)
Inventor
Teruo Kato
加藤 照男
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP58192378A priority Critical patent/JPS6084824A/en
Publication of JPS6084824A publication Critical patent/JPS6084824A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate

Abstract

PURPOSE:To enable composition of high-resistance SiC as an insulating film or a protective film and to prevent generation of a crystal defect by thermal expansion coefficient of that and further to enable thickening of the film by implanting BeO, BN or the like in the SiC formed in advance by ion implantation method. CONSTITUTION:A low-resistance SiC polycrystalline film 2a formed on a main surface of an Si single crystal substrate 1 by ion implantation is doped with BeO so as to make the film insulating, i.e. high-resistance. For the ion implantation, a solid source of BeO as an ion source is used or a solid surce of Be and a gas source of O are used together to perform a heat treatment. Next, after the SiC film 2 is selectively removed by etching, impurity such as arsenic is doped in the main surface of the exposed Si substrate 1 to form a buried layer 3, on which an epitaxial layer 4 is formed and n and p type impurities are selectively diffused. As thermal expansion coefficients of the high-resistance SiC film 2 and the Si substrate 1 are equal, stress is not generated in the Si single crystal even if the SiC films 2 and 6 are formed to be thick.

Description

【発明の詳細な説明】 〔技術分野〕 本発明は絶縁膜や保l!!@に電気絶縁性の炭化ケイ素
膜を使用して特性の向上等を達成できる半導体装置の製
造方法に関するものである。
[Detailed Description of the Invention] [Technical Field] The present invention relates to an insulating film and an insulation film. ! The present invention relates to a method of manufacturing a semiconductor device that can improve characteristics by using an electrically insulating silicon carbide film.

〔背景技術〕[Background technology]

シリコン等の半導体基板の主面上に回路素子を形成して
なる半導体装置では、素子間の絶縁を行なうアイソレー
ション膜や上下層l7)4体層間σ)絶縁を行なう層間
絶縁膜、更には素子を外気、水分から保獲するためのバ
、ソシペーション膜等種々の膜が必要とされる。従来こ
の穏σ)膜とし℃シリコン酸化膜(Sin、膜)が利用
されている。5in2膜はシリコンと熱膨張係数が異な
って体積膨張が太きいため、しばしばシリコン基板内(
単結晶内)に応力を生じさせ結晶欠陥を発生する原因と
なっている。このため、Sin、膜を厚く形成すること
は好しくな(SiO,@が薄いことKよって増大される
配線容量によって素子の高速度化が阻害されるという問
題が生じている。また・結晶欠陥σ)発生により素子の
微細化、すなわち高集積化が阻害されるという問題も生
じている。
In a semiconductor device in which circuit elements are formed on the main surface of a semiconductor substrate such as silicon, an isolation film that provides insulation between the elements, an interlayer insulation film that provides insulation between upper and lower layers, and furthermore, A variety of membranes are required, such as a vacuum membrane and a sociation membrane, to trap water from outside air and moisture. Conventionally, a silicon oxide film (Sin film) has been used as the moderate σ film. The 5in2 film has a different coefficient of thermal expansion than silicon and has a large volumetric expansion, so it often grows inside the silicon substrate (
This causes stress in the single crystal (within the single crystal) and causes crystal defects. For this reason, it is not preferable to form a thick SiO film (SiO, which is thin and has a problem in that the interconnect capacitance increases due to K and hinders the high speed of the device. Also, crystal defects There is also a problem in that the occurrence of σ) impedes the miniaturization of elements, that is, higher integration.

こQ)ようなことから、本発明者&!SiO,膜に代わ
る種々の材質について検討を加え、その一つとして炭化
ケイ素(SiC)に着目した。すなわち、特開昭56−
66086号、57−2591号に記載されているよう
に酸化ベリリウム(Bed)や窒化ボロン(BN)等の
不純物を数多含有するSiCは絶縁物としての高抵抗を
有すると共に、熱膨張係数がシリコンに略等しくしかも
熱伝導率が極めて高く、これを前述した絶縁膜や保護膜
に使用すれば結晶欠陥の発生を防止する等前述の問題点
を解消し得ることが考えられる。しかしながら、この電
気絶縁性のSiCは粉末材料をホットプレス法によって
形成した焼結体として得られるものであるため、これを
半導体基板上に形成することは事実上不可能であり、問
題解決の実現は困難である。
Q) Because of this, the inventor &! We investigated various materials to replace SiO and films, and focused on silicon carbide (SiC) as one of them. That is, JP-A-56-
As described in No. 66086 and No. 57-2591, SiC, which contains many impurities such as beryllium oxide (Bed) and boron nitride (BN), has high resistance as an insulator and has a thermal expansion coefficient similar to that of silicon. Moreover, it has extremely high thermal conductivity, and it is thought that if it is used in the above-mentioned insulating film or protective film, the above-mentioned problems such as preventing the occurrence of crystal defects can be solved. However, since this electrically insulating SiC is obtained as a sintered body made by hot-pressing powder material, it is virtually impossible to form it on a semiconductor substrate, and it is difficult to realize a solution to the problem. It is difficult.

なお、モノシラン(SiH4)とプロパン(CsHa)
の化学反応を利用してシリコン基板上にSiC膜を形成
し発光素子等を構成するものが第41回応用物理学会(
昭和55年秋、19PM8等)に提案されているが、こ
のSiCは半導体、すなわち低抵抗体であり、絶縁膜と
して利用することは不可能である。
In addition, monosilane (SiH4) and propane (CsHa)
At the 41st Annual Meeting of the Japan Society of Applied Physics, SiC films are formed on silicon substrates using chemical reactions to form light-emitting devices, etc.
However, this SiC is a semiconductor, that is, a low resistance material, and cannot be used as an insulating film.

〔発明の目的〕[Purpose of the invention]

本発明の目的は半導体装置の絶縁膜、保護膜等に電気絶
縁性のSiC膜の形成を可能とし、これにより結晶欠陥
等の発生を防止して特性の向上はもとより高速度化、高
集積化を達成できる半導体装置の製造方法を提供するこ
とにある。
The purpose of the present invention is to enable the formation of an electrically insulating SiC film as an insulating film, a protective film, etc. of a semiconductor device, thereby preventing the occurrence of crystal defects, etc., and improving characteristics as well as increasing speed and integration. An object of the present invention is to provide a method for manufacturing a semiconductor device that can achieve the following.

本発明の前記ならびにそのほかの目的と新規な特徴は、
本明細書の記述および添付図面からあきらかになるであ
ろう。
The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.

〔発明の概要〕[Summary of the invention]

本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、下記のとおりである。
A brief overview of typical inventions disclosed in this application is as follows.

すなわち、先に形成さ引たSiC[BeO+B N等を
イオン打込法等によって含有させることによりこれを高
抵抗化するものであり、これにより電気絶縁性(高抵抗
) SiCを絶縁膜や保護膜として構成でき、その熱膨
張係数によって結晶欠陥の発生を防止しかつその厚膜化
を可能とし、これにより特性の向上に加えて高速度化、
高集積化が達成できるO 〔実施例〕 i(1図へ)〜0は本発明をバイポーラトランジスタに
適用した実施例をその製造工程順に示すものである。
In other words, it is made to have high resistance by incorporating previously formed SiC [BeO+BN etc. by ion implantation method etc., and this makes it possible to make electrically insulating (high resistance) SiC into an insulating film or a protective film. Its thermal expansion coefficient prevents the occurrence of crystal defects and makes it possible to increase the thickness of the film.
O that can achieve high integration [Embodiment] i (see Figure 1) to 0 show embodiments in which the present invention is applied to bipolar transistors in the order of their manufacturing steps.

先ず同図六】σ)ように(i o o)面、P型で20
〜50Ω・備 の抵抗率のシリコン(Si)単結晶基板
1の主面に高抵抗のSiC膜2を適宜厚さに形成してい
る。この5iCf1%2は5iCVcBeOを不純物と
して含んだもので・電気抵抗率は1d0Ω・画板上の高
抵抗で殆んど絶縁体であり、また熱膨張係数は3X10
1℃程度でシリコン基板lの熱膨張係数2〜3x101
℃と殆んど等しい。更に熱伝導率kt O,5Cai/
 e=s・S・℃程度で金属と同等以上である。
First, as shown in Fig. 6), the (i o o) plane is 20 in P type.
A high resistance SiC film 2 is formed to an appropriate thickness on the main surface of a silicon (Si) single crystal substrate 1 having a resistivity of ~50 Ω. This 5iCf1%2 contains 5iCVcBeO as an impurity, has an electrical resistivity of 1d0Ω, has a high resistance on the drawing board, and is almost an insulator, and has a thermal expansion coefficient of 3X10.
Thermal expansion coefficient of silicon substrate l at around 1°C is 2 to 3 x 101
Almost equal to °C. Furthermore, the thermal conductivity kt O,5Cai/
e=s・S・℃, which is equivalent to or higher than that of metals.

前記Sac膜2は化学反応による化学蒸着法およびイオ
ン打込法によって形成している0すなわち1Si病、 
5in2. Cf1.、 、5iHCら等ノシランカス
トCH,、C,■I6. C,八、C,H,等の水素化
炭素ガスとを主反応ガスとし、11. 、 He 等σ
)キャリアガスを流しながら所定の温度に加熱したシリ
コン基板1上で化学反応させ、SiC多結晶膜2aを被
着する。
The SAC film 2 is formed by a chemical vapor deposition method using a chemical reaction and an ion implantation method.
5in2. Cf1. , , 5iHC et al. Nosilancast CH, , C, ■I6. Hydrogenated carbon gas such as C, 8, C, H, etc. is used as the main reaction gas, 11. , He etc.σ
) A chemical reaction is caused on the silicon substrate 1 heated to a predetermined temperature while flowing a carrier gas, and a SiC polycrystalline film 2a is deposited.

加熱温度は混合ガスの種類によって異なるが、数百度か
ら子鹿程度である。このようにして形成された半導体特
性、すなわち低抵抗σls+c多結晶膜2aにイオン打
込法によってBeOを添加し℃これを絶縁化、すなわち
高抵抗化する。イオン打込法としては、イオン源として
のBeOの固体ソースを使用して直接BeOを打込むか
、またはBeの固体ソースとOの気体ソースとを併用し
、しかる後数百度から子鹿の温度で熱処理してBeOを
形成する方法がある。
The heating temperature varies depending on the type of gas mixture, but ranges from several hundred degrees to about 100 degrees Fahrenheit. BeO is added by ion implantation to the thus formed polycrystalline film 2a having semiconductor characteristics, that is, low resistance, σls+c, to insulate it, that is, to make it high in resistance. As for the ion implantation method, BeO is directly implanted using a solid BeO source as an ion source, or a solid Be source and an O gas source are used together, and then the ion implantation is performed at temperatures ranging from several hundred degrees to fawn temperature. There is a method of forming BeO by heat treatment.

次に同図(B)nようにSiC膜2を選択的にエツチン
グ除去した後、露呈されたシリコン基板1の主面にヒ素
等の不純物をイオン打込等によってドープさせ埋込層3
を形成する。その上でエピタキシャル成長を行ない、同
図1cIのようにn型のエピタキシャル層4を形成する
Next, after selectively etching away the SiC film 2 as shown in FIG.
form. Thereafter, epitaxial growth is performed to form an n-type epitaxial layer 4 as shown in FIG. 1cI.

次いでこのエピタキシャル層4の主面に常法によってn
型、p型の不純物を選択的に拡散させろことによりへ同
図(Dのようにエピタキシャル層4をコレクタCとし%
p型層をベースB 、 n+層をエミッタEとするバイ
ポーラトランジスタQBを構成できる。5はコVクタコ
ンタクト、6は前述と同様にSingの被着とBeOの
イオン打込みにより形成した高抵抗SiC膜であり、層
間絶縁膜として構成される。7はAJ 配置gである。
Next, the main surface of this epitaxial layer 4 is coated with n by a conventional method.
By selectively diffusing type and p-type impurities, the same figure (as shown in D, epitaxial layer 4 is used as collector C)
A bipolar transistor QB can be constructed in which the p-type layer serves as the base B and the n+ layer serves as the emitter E. Reference numeral 5 designates a contact V contact, and reference numeral 6 designates a high-resistance SiC film formed by Sing deposition and BeO ion implantation in the same manner as described above, and is configured as an interlayer insulating film. 7 is AJ configuration g.

このようにして構成さり、た半導体装置によれば、高抵
抗のSiC膜2の熱膨張係数が前述のようにシリコン基
板1の熱膨張係数に殆んど等しいため。
According to the semiconductor device constructed in this manner, the coefficient of thermal expansion of the high-resistance SiC film 2 is almost equal to the coefficient of thermal expansion of the silicon substrate 1, as described above.

SiCPM2 、6を厚く形成してもシリコン単結晶内
に応力を発生させることはなく結晶欠陥を発生させるこ
とはない。これにより、結晶欠陥がないので素子の微細
化、つまり高集積化を可能とし、また厚膜に形成できる
ので配線容量を低減して素子の高速化が達成できる。更
に、熱伝導率が高いので素子表面σ)放熱性が向上でき
るという利点もある。
Even if SiCPMs 2 and 6 are formed thickly, no stress is generated in the silicon single crystal, and no crystal defects are generated. As a result, since there are no crystal defects, it is possible to miniaturize the device, that is, to increase its integration, and since it can be formed into a thick film, the wiring capacitance can be reduced and the speed of the device can be increased. Furthermore, since the thermal conductivity is high, there is also the advantage that the element surface σ) heat dissipation can be improved.

〔実施例2〕 第2図(5)〜動は本発明をMO8型電界効果トランジ
スタに適用した実施例をその製造工程順に示すものであ
る。
[Embodiment 2] FIGS. 2(5) to 2D show an embodiment in which the present invention is applied to an MO8 type field effect transistor in the order of its manufacturing steps.

先ず、同図囚のように(100)面・p型で1〜5Ω・
箔の抵抗率のシリコン基板11の表面にSin、膜12
を形成しかつこれを所定の形状にパターニングした後に
、このSin、膜12を今度はマスクとしてシリコン基
板110表面を選択エツチングし・同図β)のように凹
部13を形成する。
First, as shown in the figure, it is (100) plane, p type, 1~5Ω,
Sin, film 12 on the surface of the silicon substrate 11 of the resistivity of the foil
After forming and patterning it into a predetermined shape, the surface of the silicon substrate 110 is selectively etched using this Sin film 12 as a mask to form a recess 13 as shown in FIG.

次いで・同図1c)のように前記凹部13を埋める程度
の厚さに高抵抗のSiC膜14を全面にデポジションし
、その後凸状に形成された部外のSiC膜14を選択エ
ツチングすることにより・同図(DJのようにSiC醜
14を素子間分離絶縁膜とした基板に構成される。
Next, as shown in FIG. 1c), a high-resistance SiC film 14 is deposited on the entire surface to a thickness sufficient to fill the recess 13, and then the SiC film 14 formed in a convex shape outside is selectively etched. According to the same figure (like the DJ), it is constructed on a substrate using SiC 14 as an inter-element isolation insulating film.

前記SiC膜14は、前例と同様にSiC多結晶膜(低
抵抗)を形成した上で・イオン源としてBNの固体ソー
スを使用して直接BNを打込むか・またはBの固体ソー
スとNの気体ソースとを併用してイオン打込みし、しか
る後熱処理してBNを形成せしめている。このSiC膜
141Cおいても絶縁体としての高抵抗、シリコンに等
しい熱膨張率。
The SiC film 14 is formed by forming a SiC polycrystalline film (low resistance) as in the previous example, and then directly implanting BN using a solid source of BN as an ion source, or by implanting a solid source of B and a solid source of N. Ion implantation is performed using a gas source, and then heat treatment is performed to form BN. This SiC film 141C also has high resistance as an insulator and a coefficient of thermal expansion equal to that of silicon.

高い熱伝導率を有する点は同じである。They also have high thermal conductivity.

次いで同図C)のようrcsiO,膜15をゲート絶縁
膜として形成した上でポリシリコンによるゲー)16、
N型不純物の基板へのイオン打込みによるソース層17
.ドレイン層18を夫々形成することによりMO8型電
界効果トランジスタ籟ヲ栴成できる。図中・19はPF
3G等の眉間絶縁膜。
Next, as shown in Figure C), after forming the rcsiO film 15 as a gate insulating film, a polysilicon gate film 16,
Source layer 17 formed by ion implantation of N-type impurities into the substrate
.. By forming the drain layers 18, an MO8 type field effect transistor can be formed. In the figure, 19 is PF
Glabella insulating film such as 3G.

20はAll配線である。20 is an All wiring.

本実施例においても素子間分離用の絶縁膜を電気絶縁性
の5iCIILにて形成しているので・その熱膨張係数
がシリコン基板に等しくて結晶欠陥の発生を防止し素子
の高集積化を実現できる一方、厚膜に形成できることか
ら配線容量を低減して高速度化を達成できる。また、高
熱伝導率によって放熱効果を向上できることはいうまで
もない。
In this example as well, since the insulating film for isolation between elements is formed of electrically insulating 5iCIIL, its thermal expansion coefficient is equal to that of the silicon substrate, preventing the occurrence of crystal defects and achieving high integration of elements. On the other hand, since it can be formed into a thick film, wiring capacitance can be reduced and high speed can be achieved. Moreover, it goes without saying that the heat dissipation effect can be improved by the high thermal conductivity.

なお、第3図に示すようにSiCの半導体基板を使用す
る場合には、SiC基板の主面忙選択的にイオン打込法
によってBeO+BNを含有させることにより、絶縁膜
を基板に一体形成することもできる。また、8i基板の
主面KBeO+C+BN上ρtp m 4rIbh a
r −1”r I J−) L l# F / m f
iAh、# tk抗SiCを形成するようにしてもよい
As shown in FIG. 3, when using a SiC semiconductor substrate, an insulating film can be integrally formed on the substrate by selectively incorporating BeO+BN into the main surface of the SiC substrate by ion implantation. You can also do it. Also, ρtp m 4rIbh a on the main surface KBeO+C+BN of the 8i substrate
r −1”r I J−) L l# F / m f
iAh, #tk anti-SiC may be formed.

〔効 果〕〔effect〕

(1) 低抵抗(半導体)のSi(、cイオン打込法等
によってBeO+BNを含有させて高抵抗化させている
ので、微細パターンの絶R膜や保賎膜な容易に形成でき
る。
(1) Low resistance (semiconductor) Si (C) is made to contain BeO+BN by ion implantation method or the like to increase resistance, so it can be easily formed into a finely patterned R film or a protective film.

(21形成された高抵抗SICの膜はシリコンの熱膨張
係数に等しいので、熱変化によってもSiC膜が原因と
される応力がシリコン結晶内に生じることはなく、結晶
欠陥を防止して素子の特性の向上と高集積化が達成でき
る。
(Since the high-resistance SIC film formed in 21 has a coefficient of thermal expansion equal to that of silicon, stress caused by the SiC film will not occur in the silicon crystal due to thermal changes, preventing crystal defects and improving the device performance.) Improved characteristics and higher integration can be achieved.

(335iCI[rcよる結晶゛欠陥がないのでSiC
膜を厚く形成することが可能になり、配線容量の低減を
図って素子の高速度化を達成できる。
(335iCI [crystal due to rc] Since there are no defects, SiC
It becomes possible to form a thick film, reduce wiring capacitance, and achieve higher speed of the element.

以上本発明者によってなされた発明を実施例にもとづき
具体的に説明したが1本発明は上記実施例に限定される
ものではなく、その要旨を逸脱しない範囲で種々変更可
能であることはいうまでもない。たとえば、高抵抗Si
Cを)(ツシペーション膜やキャパシタの誘電体に利用
する場合でも同様に形成することができる。
Although the invention made by the present inventor has been specifically described above based on examples, it goes without saying that the present invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist thereof. Nor. For example, high resistance Si
C can be formed in the same way even when used as a tsipation film or a dielectric of a capacitor.

〔利用分野〕[Application field]

以上の説明では主として本発明者によってなされた発明
をその背景となった利用分野であるトランジスタに適用
した場合について説明した力l、これに限定されるもの
ではな(、IC、LSIはもとよりダイオードや大電力
用整流素子にも同様に第1図(5)〜ρ)は本発明の第
1実施例を製造工程順に示す断面図、 第2図四〜胆)は第2実施例の製造工程断面図である。
The above explanation mainly describes the case where the invention made by the present inventor is applied to transistors, which is the background field of application, but is not limited to this (ICs, LSIs, diodes, etc.). Similarly, for the rectifying element for high power, Fig. 1 (5) to ρ) are cross-sectional views showing the first embodiment of the present invention in the order of manufacturing steps, and Fig. 2 4 to ρ) are cross-sectional views of the manufacturing process of the second embodiment. It is a diagram.

1・・・シリコン基板、2・・・高抵抗5iCJli、
3・・・埋込層、4・・・エピタキシャル層、6・・・
高抵抗SiC膜・11・・・シリコン基板、12・・・
8i0.膜、16・・・ゲ−)、17・・・ソース層、
1g・・・ドレイン層、19・・・PSG膜。
1... Silicon substrate, 2... High resistance 5iCJli,
3... Buried layer, 4... Epitaxial layer, 6...
High resistance SiC film・11...Silicon substrate, 12...
8i0. film, 16... game), 17... source layer,
1g...Drain layer, 19...PSG film.

代理人 弁理士 高 橋 明 夫 天 鳴 \−\J へ へ 剋 QAgent: Patent Attorney Akio Takahashi heavenly sound \-\J To To To Q

Claims (1)

【特許請求の範囲】 1、炭化ケイ素にBeOまたはBNを添加して電気絶縁
性炭化ケイ素のP3m膜を形成することを特徴とする半
導体装置の製造方法。 2、BeOの添加はBeαまたはBe およびOをイオ
ン打込法により行なってなる特許請求の範囲第1項記載
の半導体装置の製造方法。 3、BNの添加はBN、またはBおよびNをイオン打込
法により行なってなる特許請求の範囲第1項記載の半導
体装置の製造方法。 4、炭化ケイ素はシランガスと水素ガスとを化学反応形
成してなる特許請求の範囲第1項記載の半導体装置の製
造方法。
[Claims] 1. A method for manufacturing a semiconductor device, which comprises adding BeO or BN to silicon carbide to form an electrically insulating P3m film of silicon carbide. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the addition of BeO is performed by ion implantation of Beα or Be and O. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the addition of BN is performed by ion implantation of BN or B and N. 4. The method of manufacturing a semiconductor device according to claim 1, wherein silicon carbide is formed by a chemical reaction of silane gas and hydrogen gas.
JP58192378A 1983-10-17 1983-10-17 Manufacture of semiconductor device Pending JPS6084824A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58192378A JPS6084824A (en) 1983-10-17 1983-10-17 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58192378A JPS6084824A (en) 1983-10-17 1983-10-17 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS6084824A true JPS6084824A (en) 1985-05-14

Family

ID=16290292

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58192378A Pending JPS6084824A (en) 1983-10-17 1983-10-17 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6084824A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01283838A (en) * 1988-05-10 1989-11-15 Toshiba Corp Semiconductor device
CN111584497A (en) * 2020-05-21 2020-08-25 长江存储科技有限责任公司 Memory manufacturing method and memory

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01283838A (en) * 1988-05-10 1989-11-15 Toshiba Corp Semiconductor device
CN111584497A (en) * 2020-05-21 2020-08-25 长江存储科技有限责任公司 Memory manufacturing method and memory
CN111584497B (en) * 2020-05-21 2021-07-20 长江存储科技有限责任公司 Memory manufacturing method and memory

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