JPS61203633A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS61203633A
JPS61203633A JP4437985A JP4437985A JPS61203633A JP S61203633 A JPS61203633 A JP S61203633A JP 4437985 A JP4437985 A JP 4437985A JP 4437985 A JP4437985 A JP 4437985A JP S61203633 A JPS61203633 A JP S61203633A
Authority
JP
Japan
Prior art keywords
germanium
layer
silicon
semiconductor
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4437985A
Other languages
Japanese (ja)
Other versions
JPH0666262B2 (en
Inventor
Hitoshi Ishii
仁 石井
Tsuneo Takahashi
庸夫 高橋
Junichi Murota
室田　淳一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP4437985A priority Critical patent/JPH0666262B2/en
Publication of JPS61203633A publication Critical patent/JPS61203633A/en
Publication of JPH0666262B2 publication Critical patent/JPH0666262B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE:To prevent the disconnection in a through hole portion and to improve an yield of wiring, by providing a process wherein an insulating film is formed partially and then is processed in a gas containing a gas having germanium as a component element and thereby a germanium layer is formed selectively on the surface of a semiconductor or a metal. CONSTITUTION:An oxide film is formed on a silicon substrate 5 exposing a (100) face, and a part of the film is removed by photolithography and etching, so as to make the surface of the silicon substrate be exposed. The sample thus prepared is put in a CVD reaction furnace and processed in the atmosphere of a germane gas at a substrate temperature of 450 deg.C or below. Then germanium is not deposited on the silicon oxide film 6, and a germanium layer 7 is formed selectively only on an exposed silicon surface not covered with the silicon oxide film on the silicon substrate 5. By utilizing this selective deposition of germanium, a semiconductor device in which a germanium layer serves as a connecting layer between a metal layer and a silicon substrate can be obtained with ease.

Description

【発明の詳細な説明】 〔概　要〕 半導体或いは金属の表面に部分的Ｃ絶縁膜を形成し、ゲ
ルマニウム層を選択成長せしめることにより各種半導体
装置を製造する。[Detailed Description of the Invention] [Summary] Various semiconductor devices are manufactured by forming a partial C insulating film on the surface of a semiconductor or metal and selectively growing a germanium layer.

〔産業上の利用分野〕[Industrial application field]

本発明は半導体上或いは金員上ＣＭ択的に下地基板との
反応がほとんどなくゲルマニウム層を形成する方法を用
いた半導体装置の製造方法に関するものである。The present invention relates to a method of manufacturing a semiconductor device using a method of forming a germanium layer selectively on a semiconductor or metal layer with almost no reaction with an underlying substrate.

〔従来の技術〕[Conventional technology]

従来、半導体装置の電極・配線の形成には、第８図Ｃ示
す如く、下Ｉ−竜極・配［７１１上ｇ二絶縁層２および
スルーホール３を形成しく第８図（α））、次にスパッ
タ法あるいは真空蒸着法等により、金属層４（第８図（
し））を形成する方法が用いられてきた。Conventionally, in the formation of electrodes and wiring of a semiconductor device, as shown in FIG. Next, a metal layer 4 (see FIG.
A method of forming a )) has been used.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

しかし、半導体装置の微細化Ｃ二伴いスルーホールが微
小化し、真空蒸着法やスパッタ法等を用いた場合には第
９図に示す如く、スルーホール側壁部（二金属が堆積さ
れず、下層電極・配線との接続がとれないという欠点が
あった。これを改善するためＣ二六フッ化タングステン
（ｖＦ６）等の金属フッ化物を用いてスルーホール部を
金属で選択的Ｃ二埋め込む方法が提案されているが下地
基板との反応があり、また高選択性が得られないという
欠点があった◎ 一方、ＭＯＳ型半導体装置をスケールダワン則に従い微
細化してゆくと拡散層が浅くなり、ソースおよびドレイ
ンの直列寄生抵抗値が増大しＭＯＳ型半導体装置の高速
動作を妨げるという欠点があつた。However, with the miniaturization of semiconductor devices, through-holes have become smaller, and when vacuum evaporation, sputtering, etc. are used, as shown in FIG.・There was a drawback that it was not possible to connect with the wiring.To improve this, a method of selectively filling the through-hole with metal using a metal fluoride such as tungsten hexafluoride (vF6) was proposed. ◎ On the other hand, as MOS semiconductor devices are miniaturized according to the scale down rule, the diffusion layer becomes shallower and the source and This has the disadvantage that the series parasitic resistance value of the drain increases, which impedes high-speed operation of the MOS type semiconductor device.

〔問題点を解決するための手段〕 本発明はこれらの欠点を解決するため（ニゲルマン（Ｇ
ｍＨ４）等のゲルマニウムを構成元素とするガスを用い
て絶縁層に囲まれた半導体上あるいは金属上（二下地基
板との反応がほとんどないゲルマニウム層を形成して利
用するものである。[Means for Solving the Problems] In order to solve these drawbacks, the present invention
It is used by forming a germanium layer on a semiconductor surrounded by an insulating layer or on a metal (2) which hardly reacts with the underlying substrate using a gas containing germanium as a constituent element such as mH4).

〔作　用〕[For production]

第１図（α）（ｂ）の実施例を採って説明すると、図（
α）でシリコン基板５の上Ｃ二酸化膜（シリコン酸化膜
）６が部分的（二形成されている。そして、ＣＶＤ反応
炉内で４５０℃以下の基板温度でゲルマンガス雰囲気中
で処理すると、第１図（Ａ）のよう（二酸化膜６上ぽ二
はゲルマニウムは堆積せず、シリコン基板５上の酸化膜
６Ｃ二被覆されていないシリコン露出面上１：のみゲル
マニウム層７が選択的ｆ二形成される。Taking the example of FIG. 1(α)(b) and explaining it, FIG.
In α), a carbon dioxide film (silicon oxide film) 6 is partially formed on the silicon substrate 5. Then, when it is processed in a germane gas atmosphere at a substrate temperature of 450°C or less in a CVD reactor, As shown in Fig. 1 (A) (no germanium is deposited on the oxide film 6, only the germanium layer 7 is selectively formed on the uncovered silicon exposed surface of the oxide film 6C on the silicon substrate 5). be done.

第２図に、本発明（二おける方法を用いてシリコン基板
上に４１０℃を二で形成したゲルマニウム層のオージェ
電子分光分析！＝よる深さ分析の結果を示す。FIG. 2 shows the results of depth analysis by Auger electron spectroscopy of a germanium layer formed at 410° C. on a silicon substrate using the method of the present invention.

′ｉ！１１２図から明らかなように、ゲルマニウムｆ二
相当する曲線の立下り、シリコンに相当する曲線の立上
りが急峻であることから、ゲルマニウム層はシリコンと
の界面で下地シリコンとあまり反応していないと考えら
れる。つまり、本発明によれば、ゲルマニウム層と下地
基板に影響を与えずに良好な接続をとることができる。'i! As is clear from Figure 112, the fall of the curve corresponding to germanium f2 and the rise of the curve corresponding to silicon are steep, so it is thought that the germanium layer does not react much with the underlying silicon at the interface with silicon. It will be done. In other words, according to the present invention, a good connection can be made without affecting the germanium layer and the underlying substrate.

また、シリコン基板に本発明により形成したゲルマニウ
ム層がエビタキンヤル層であることを利用して、シリコ
ンとゲルマニウムの層状構造のＳｉ／Ｇａへテロ界面≦
二後に詳述するようＣ二高移動度の正孔を閉じ込めるこ
とができ、ＨＥＭＴ　（高電子移動度トランジスタ）類
似の構造を形成することかできる。その他、本発明は各
種半導体装置の製造ζ二適用される。Further, by utilizing the fact that the germanium layer formed on the silicon substrate according to the present invention is an Evita Kinyal layer, the Si/Ga hetero interface of the layered structure of silicon and germanium ≦
As will be detailed later, C2 can confine high-mobility holes and form a structure similar to a HEMT (high electron mobility transistor). In addition, the present invention is applicable to the manufacture of various semiconductor devices.

〔実施例〕〔Example〕

第１図は本発明の実施例である。（１００）　面を出し
たシリコン基板５上ｌ二酸化膜を形成し、その一部をフ
ォトリングラフィとエツテングにより除去し、シリコン
基板面を露出させる（第１図（α））。FIG. 1 shows an embodiment of the invention. (100) A carbon dioxide film is formed on the exposed silicon substrate 5, and a portion of it is removed by photolithography and etching to expose the silicon substrate surface (FIG. 1 (α)).

そしてＣＶＤ反応炉に試料を入れ、４５０℃以下の基板
温度でゲルマンガス雰囲気中で処理すると、シリコン酸
化膜６上Ｃ二はゲルマニウムは堆積せず、シリコン基板
５上のシリコン酸化膜に被覆されていないンリコン露出
面上Ｃ二のみゲルマニウム層７が選択的Ｃ二形成される
（第１図（ｂ））。ゲルマンガス雰囲気での処理条件は
、ゲルマンガス分圧ヲ５．ＯＸ　１００−５ＡＴ　カら
４．ＯＸ　１０−’　ＡＴＭとし、水素ガス（Ｈｚ＞−
ｗキャリヤーガスとして全圧４．ＯＸ　１０−”ＡＴＭ
とした。′ｓ５図（二本実施例（二おけるゲルマニウム
のシリコン（ｉｏｏ）基板上への堆積速度の堆積温度依
存性を示す。４５０℃以下の温度では上記処理条件で、
シリコン基板上のみ（ニゲルマニウムが選択的【二堆積
する。ゲルマニウムの選択的堆積はゲルマニウム原子が
ゲルマニウム自身やシリコンとは結会しやすいが、シリ
コン酸化膜とは結合しＣ二くいこと（二由釆するものと
考えられる。また、４５０℃より高温領域で選択性が失
われる場合がある。Then, when the sample is placed in a CVD reactor and treated in a germane gas atmosphere at a substrate temperature of 450° C. or less, no germanium is deposited on the silicon oxide film C2, but it is covered with the silicon oxide film on the silicon substrate 5. A germanium layer 7 is selectively formed only on the exposed surface of the silicon (FIG. 1(b)). The processing conditions in the germane gas atmosphere are as follows: germane gas partial pressure. OX 100-5AT 4. OX 10-' ATM, hydrogen gas (Hz>-
wTotal pressure as carrier gas4. OX 10-”ATM
And so. Figure 's5 shows the dependence of the deposition rate of germanium on a silicon (IOO) substrate on the deposition temperature in the second embodiment. At temperatures below 450°C, under the above processing conditions,
Only on the silicon substrate (Nigermanium is selectively deposited).The selective deposition of germanium is because germanium atoms tend to bond with germanium itself and silicon, but they bond with silicon oxide film and are difficult to bond with (two reasons). In addition, selectivity may be lost at temperatures higher than 450°C.

これは、基板周囲、たとえば基板支持治具等に二堆積し
たゲルマニウムが高温Ｃｇいてゲルマニウムあるいはゲ
ルマニウム化合物として気化し、シリコン酸化膜上Ｃ二
付着してしまうためである。したがって、あらかじめ基
板周囲のゲルマニウム層堆積する部分をシリコン酸化膜
等で覆うなどの処置を施してゲルマニウムの堆積を防げ
ば、たとえば６００℃でもゲルマニウムの選択的堆積は
容易Ｃ二起こる。さらに、ゲルマニウムの選択的堆積は
キャリヤーガスをヘリウムガス等の不活性ガスＣ二して
も起こることを確認している。以上説明したゲルマニウ
ムの選択的堆積は、シリコン（ｉｏｎ）基板以外の他の
面な出したシリコン等の半導体、あるいはアルミニウム
、モリブデン、白金等の金属を基板とし、金属酸化物を
絶縁層としても起こるものと考えられる。This is because germanium deposited around the substrate, for example, on a substrate support jig, is exposed to high temperature Cg and vaporizes as germanium or a germanium compound, resulting in C2 depositing on the silicon oxide film. Therefore, if the area around the substrate where the germanium layer is to be deposited is covered in advance with a silicon oxide film or the like to prevent the deposition of germanium, selective deposition of germanium can easily occur even at, for example, 600°C. Furthermore, it has been confirmed that selective deposition of germanium occurs even when the carrier gas is an inert gas such as helium gas. The selective deposition of germanium described above also occurs when a semiconductor other than a silicon (ion) substrate, such as exposed silicon, or a metal such as aluminum, molybdenum, or platinum is used as a substrate, and a metal oxide is used as an insulating layer. considered to be a thing.

〔ゲルマニウム接続層〕[Germanium connection layer]

本発明Ｃ二よるゲルマニウムの選択的堆積を利用丁れば
、ゲルマニウム層を金属層とシリコン基板の接続層とす
る半導体装置を容易Ｃ二得られる。その実施例を第４図
（二示す。シリコン基板５（二酸化膜６を形成し、スル
ーホール５の窓開けを行なう（第４図（α））。これを
以上説明したよう（ニゲルマンガス雰囲気中で処理する
と、スルーホール３（二のみゲルマニウム層７（第４図
（ｂ））が形成される。By utilizing the selective deposition of germanium according to the present invention C2, it is possible to easily obtain a semiconductor device C2 in which a germanium layer is used as a connection layer between a metal layer and a silicon substrate. An example of this is shown in FIG. When processed, through holes 3 (only two germanium layers 7 (FIG. 4(b)) are formed.

これ（二金属層形成の工程を施せば第４図（Ｃ）のよう
（：金属層４が形成され、第９図（二示した従来技術Ｃ
二よる欠点を克服しゲルマニウム層′４ｒ：接続層とす
る半導体装置が得られる。If the process of forming two metal layers is performed, the metal layer 4 is formed as shown in FIG.
A semiconductor device can be obtained in which the two drawbacks are overcome and the germanium layer '4r is used as a connection layer.

ＣＭＯＳ型Ｏ８型半！Ｊ サラ（二他の実施例Ｃ二ついて記す。従来のＭＱＳｊｌ
半導体装置では、微細化Ｃ二伴い拡散層が薄層化するた
めソースおよびドレインの直列寄生抵抗値が高抵抗値を
持ち、その結果ＭＯＳ型半導体装置の高速動作を妨げる
欠点があった。本発明を用いれば上記の欠点を解決する
ことが可能である。すなわちＭＯＳ型半導体装置製造の
工程Ｃ二おいて、第５図（α）の如きソース・ドレイン
の拡散層８が露出した構造を通常の工程Ｃ二で形成した
後、ゲルマンガス雰囲気中で処理すると、第５図（ｂ）
（二示す如く拡散層８上のみＣニゲルマニウム層７を形
成できる（第５図（ｂ））。このゲルマニウム層７は先
（二第２図で示したよう（；下地半導体との反応が少な
い。つまり本実施例シニよればゲルマニウム層と下地基
板Ｃ二影響を与えずに良好な接続ｔとることができる。CMOS type O8 type and a half! J Sara (Two other examples C are described. Conventional MQSjl
In semiconductor devices, as the diffusion layer becomes thinner with miniaturization, the series parasitic resistance value of the source and drain has a high resistance value, and as a result, there is a drawback that high-speed operation of the MOS type semiconductor device is hindered. Using the present invention, it is possible to overcome the above-mentioned drawbacks. That is, in step C2 of manufacturing a MOS type semiconductor device, after forming a structure in which the source/drain diffusion layer 8 is exposed as shown in FIG. , Figure 5(b)
(As shown in Figure 2, the C nigermanium layer 7 can be formed only on the diffusion layer 8 (Figure 5 (b)). In other words, according to this embodiment, a good connection can be made without affecting the germanium layer and the underlying substrate C.

ゲルマニウム層の抵抗を低減するためには、ゲルマニウ
ム層堆積の際にゲルマンガスとともＣ二、アルシン（Ａ
ｚＨ，）　、ホスフィンＣＰＨ３）あるいはジボラン（
Ｅ　ｔ　Ｈａ　）ガス等を流し、ヒ素（ＡＪ）　　、リ
ン＜ｐ＞あるいはホウ素ＣＢ）ドープのゲルマニウムと
する方法、あるいは、ゲルマニクム層形成後Ｃ二ヒ素（
ＡＪ）、リン（Ｐ）、ホウ素ＣＢ）等のＶ族あるいはＩ
族の不純物乞公知のイオン注入技術ｔもってゲルマニク
ム層Ｃ二添加する方法のどちらかを用いれば良い。In order to reduce the resistance of the germanium layer, C2, arsine (A
zH, ), phosphine CPH3) or diborane (
Alternatively, after forming a germanium layer, C diarsenic (
Group V or I such as AJ), phosphorus (P), boron CB)
Either of the methods of doping germanium layer C2 using known ion implantation techniques may be used.

〔ゲルマニウム抵抗体〕[Germanium resistor]

また本発明Ｃ二よって形成したゲルマニウム層、は前記
のように低抵抗電極・配線として用いることができるば
かりでなく、ゲルマニウム層それ自体を抵抗体として用
いることも可能である。Further, the germanium layer formed according to the present invention C2 can not only be used as a low resistance electrode/wiring as described above, but also the germanium layer itself can be used as a resistor.

丁なわち、スルーホールの深さや径を適当Ｃ２選ぺば、
ゲルマニウム層を加工することなく、たとえば第４図（
Ｃ）の如くゲルマニウム層の抵抗体を形成することかで
きる。In other words, if you choose the depth and diameter of the through hole appropriately,
For example, without processing the germanium layer, as shown in Fig. 4 (
A germanium layer resistor can be formed as shown in C).

（ＨＨＭＴ構造〕 さらＣ二、シリコン基板上に本発明を用いて形成したゲ
ルマニウム層がエビタキンヤル層であることを利用して
公知のＨＥＭＴ　（高電子移動度トランジスタＨｉｇｈ
　　Ｅｌｅｃｔｒｏｎ　Ｍｏｂｉｌｉｔｙ　Ｔｒａｎｓ
ｉｓｔｏｒ）構造と類似のＨＨＭＴ（高正孔移動度トラ
ンジスタＨｚｇｈ　Ｈｏ１ａ　Ｍｏｂｓムｔｙ　Ｔｒａ
ｒｂｚ＊ｚｔｏｒ）構造を得ることができる。すなわち
、第６因【二おいて、シリコン基板上５　に本発明を持
ってゲルマニウム層１０を形成する。(HHMT structure) Furthermore, C2, a known HEMT (high electron mobility transistor
Electron Mobility Trans
HHMT (High Hole Mobility Transistor) structure similar to
rbz*ztor) structure can be obtained. That is, in the sixth factor [2], the germanium layer 10 is formed on the silicon substrate 5 according to the present invention.

引き続いてシラン（Ｓ＊Ｈ，）等のシラン系ガスで処理
すること（−よってシリコンエビタキンヤル層１１を形
成して、シリコンーゲルマニクムーンリコン層状構造を
得る。この際、シリコンエピタキシャル層１１とゲルマ
ニウムエピタキシャル層１０のへテロ界面のエネルギー
バンドの構造は第７図の様になる。Ｓｉと０１の電子親
和力はほぼ近い値をもつので、公知のＨＥＭＴ構造の場
合と同様（二＄７図のＡのエネルギー位置Ｃ二２次元正
孔ガスをとじこめることができる。この際ＨＥＭＴの場
合と同様１ニシリコン工ビタキシヤル層１１の一部ｔ：
Ｐ　型２与える様な不純物全添加しておき、ゲルマニウ
ムエピタキシャル層１０の正孔ガスｔとじこめる領域を
高純度ゲルマニウム層とすること（二より、高移動度の
２次元正孔ガスをとじ込めることができる。Subsequently, the silicon epitaxial layer 11 is formed by treatment with a silane-based gas such as silane (S*H, ) to obtain a silicon-germanic moon recon layered structure. The structure of the energy band at the heterointerface of the germanium epitaxial layer 10 is as shown in Fig. 7.Since the electron affinities of Si and O1 have almost similar values, it is similar to the case of the known HEMT structure (Fig. It is possible to trap the two-dimensional hole gas at the energy position C of A.In this case, as in the case of HEMT, a part of the silicon bitaxial layer 11 t:
All impurities that give P-type 2 are added, and the region of the germanium epitaxial layer 10 that traps the hole gas t is made into a high-purity germanium layer. can.

さら（二、このンリコンーゲルマニウムーシリコン層状
構造では、シリコンエピタキシャル層１１上に安定なシ
リコン酸化膜を形成でき、ゲート絶縁膜を有する構造を
とらせることもでき、従来のＲＥＮＴと比べて、ゲート
リーク電流の低減ができ、エンハンスメント型トランジ
スタとしての使用条件が広がる等の利点を有する構造と
なる。Furthermore, in this silicon-germanium-silicon layered structure, a stable silicon oxide film can be formed on the silicon epitaxial layer 11, and a structure with a gate insulating film can be formed, compared to conventional RENT. This structure has the advantage of reducing gate leakage current and expanding the conditions for use as an enhancement type transistor.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明の適用によりスルーホール
部へのゲルマニウムの埋め込みが可能となり、スルーホ
ール部での配線の断線を防ぐことができ、配線歩留まり
を向上させることができる。As described above, by applying the present invention, germanium can be embedded in the through-hole portion, and disconnection of the wiring in the through-hole portion can be prevented, and the wiring yield can be improved.

さらにソース拳ドレイン拡散層上へ低抵抗ゲルマニウム
を堆積することによってソース・ドレイン直列寄生抵抗
を低減することができるという利点かある。また逆にゲ
ルマニウム層を抵抗体として用いる適用も考えられる。Furthermore, there is the advantage that the source-drain series parasitic resistance can be reduced by depositing low-resistance germanium on the source-drain diffusion layer. Conversely, it is also possible to use a germanium layer as a resistor.

或いは本発明−二より高正孔移動度トランジスタ構造を
作ることが可能となり、素子の高性能化を図ることがで
きる。Alternatively, according to the present invention-2, it is possible to create a high hole mobility transistor structure, and it is possible to improve the performance of the device.

【図面の簡単な説明】[Brief explanation of drawings]

第１図（α）（ｂ）は本発明による半導体装置製造方法
の一実施例の工程の断面図、 ＠２図は本発明によって堆積したゲルマニウム層のオー
ジェ゛磁子分光による深さ分析の結果を示す一例の線図
、 第５図はゲルマニウムのシリコン基板上へノ堆積速度の
温度依存性を示す図、 第４図（α）〜（ｃ）は本発明の池の実施例の工程の断
面図でゲルマニウム層をンリコン基板と金属層の接続層
とする半導体装置の製造方法を示した図、ｆ＃Ｉｌｓ図
（α）（ｈ）は本発明の更（：池の実施例の工程の断面
図ではソース・ドレイン直列寄生抵抗の低減を図るため
ソース・ドレイン拡散層上１ニゲルマニウム層を形成し
た構造を持つＭＯＳ型半導体装置を得る工程の一部を示
した因、 第６図はシリコン−ゲルマニウム−シリコン層状構造な
示す図であり、第７因はそのへテロ界面のエネルギーバ
ンド構造図、 第８図（α）（ｂ）は従来法によるスルーホール埋め込
み工程を示す断面図、 第９因は微細なスルーホールの埋め込みＣ二従来法を用
いた場合の断面図。 １・・・下層電極・配線層、２・・・絶縁層、３・・・
スルーホール、４・・・金属層、５・・・シリコン基板
、６・・・シリコン酸化膜、７・・・ゲルマニウム層、
８・・・拡散層、９・・・ポｙシリコンゲート、１０・
・・ゲルマニウム（エビタキンヤル）層、１１・・・ン
ジコン（エビタキンヤル）層 特許出願人　　日本電信電話公社 代理人　弁理士　玉蟲久五部（外２名）本発明の実施イ
列の工程の断面図 第　１　　図 本発明の実施例の工程図 本発明の実施例の工程図 第５図 シリコン−ゲルマニウム−シリコン層状構造を示す口笛
　６　　図 ５ｉ−Ｇｅヘテロ界面のエネルギパン臼清造口笛　７　
図Figures 1 (α) and (b) are cross-sectional views of steps in an embodiment of the semiconductor device manufacturing method according to the present invention, and Figure 2 is the result of depth analysis by Auger magneton spectroscopy of the germanium layer deposited according to the present invention. FIG. 5 is a diagram showing the temperature dependence of the deposition rate of germanium on a silicon substrate. FIG. The figure shows a method for manufacturing a semiconductor device using a germanium layer as a connection layer between a silicon substrate and a metal layer. The figure shows a part of the process of obtaining a MOS type semiconductor device having a structure in which one nigermanium layer is formed on the source/drain diffusion layer in order to reduce the source/drain series parasitic resistance. This figure shows the germanium-silicon layered structure, and the seventh factor is an energy band structure diagram of its hetero interface. 1 is a cross-sectional view when using the conventional method of embedding fine through holes. 1... Lower electrode/wiring layer, 2... Insulating layer, 3...
Through hole, 4... Metal layer, 5... Silicon substrate, 6... Silicon oxide film, 7... Germanium layer,
8... Diffusion layer, 9... Polysilicon gate, 10.
...Germanium (Evitakinyar) layer, 11...Njicon (Evitakinyar) layer Patent applicant: Nippon Telegraph and Telephone Public Corporation agent Patent attorney: Gobe Tamamushi (2 others) Cross-sectional diagram of the process of implementing the present invention No. 1 Fig. 5 Process diagram of an embodiment of the present invention Process diagram of an embodiment of the present invention Fig. 5 A whistle showing a silicon-germanium-silicon layered structure 6 Fig. 5 I-Ge heterointerface energy-pan Usashizo whistle 7
figure

Claims (5)

【特許請求の範囲】[Claims] （１）半導体或いは金属の表面に部分的に絶縁膜を形成
し、 その後、ゲルマニウムを構成元素とするガスを含むガス
中で処理し、前記半導体又は金属の表面に選択的にゲル
マニウム層を形成する工程を含むことを特徴とする半導
体装置の製造方法。(1) Forming an insulating film partially on the surface of a semiconductor or metal, and then treating it in a gas containing a gas containing germanium as a constituent element to selectively form a germanium layer on the surface of the semiconductor or metal. 1. A method of manufacturing a semiconductor device, the method comprising the steps of: （２）前記半導体又は金属が電極層であることを特徴と
する特許請求の範囲第１項記載の半導体装置の製造方法
。(2) The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor or metal is an electrode layer. （３）前記半導体がＭＯＳ型半導体装置のｎ型或いはｐ
型の半導体層であることを特徴とする特許請求の範囲第
１項記載の半導体装置の製造方法。(3) The semiconductor is an n-type or p-type of a MOS type semiconductor device.
2. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor layer is a molded semiconductor layer. （４）前記ゲルマニウム層が抵抗体となされることを特
徴とする特許請求の範囲第１項記載の半導体装置の製造
方法。(4) The method of manufacturing a semiconductor device according to claim 1, wherein the germanium layer is a resistor. （５）前記半導体がシリコンであり、前記ゲルマニウム
層またはその界面に高移動度の２次元正孔ガスをとじ込
めるようになされることを特徴とする特許請求の範囲第
１項記載の半導体装置の製造方法。(5) The semiconductor device according to claim 1, wherein the semiconductor is silicon and is configured to trap a high-mobility two-dimensional hole gas in the germanium layer or its interface. Production method.
JP4437985A 1985-03-06 1985-03-06 Method for manufacturing semiconductor device Expired - Lifetime JPH0666262B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4437985A JPH0666262B2 (en) 1985-03-06 1985-03-06 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4437985A JPH0666262B2 (en) 1985-03-06 1985-03-06 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPS61203633A true JPS61203633A (en) 1986-09-09
JPH0666262B2 JPH0666262B2 (en) 1994-08-24

Family

ID=12689867

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4437985A Expired - Lifetime JPH0666262B2 (en) 1985-03-06 1985-03-06 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JPH0666262B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03150874A (en) * 1989-11-07 1991-06-27 Nec Corp Semiconductor device
JPH03150875A (en) * 1989-11-07 1991-06-27 Nec Corp Semiconductor device
US8815714B2 (en) 2012-03-02 2014-08-26 Tokyo Electron Limited Method of forming a germanium thin film

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03150874A (en) * 1989-11-07 1991-06-27 Nec Corp Semiconductor device
JPH03150875A (en) * 1989-11-07 1991-06-27 Nec Corp Semiconductor device
US8815714B2 (en) 2012-03-02 2014-08-26 Tokyo Electron Limited Method of forming a germanium thin film

Also Published As

Publication number Publication date
JPH0666262B2 (en) 1994-08-24

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