1270144 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種半導體元件，詳言之，係關於一種具 有橫向構造之半導體元件及其製造方法。 【先前技術】 於類比積體電路中，使用具有射極、集極與基極鄰接形 成於水平方向之構造之橫向PNP電晶體。使用於橫向pNp 電晶體之半導體元件，例如包含N-型之基極區域、形成於 基極區域表面區域之P+型之射極區域、以與射極區域離間 之方式形成於基極區域表面區域之P+型之集極區域、包夾 集極區域且與射極區域相對之位置上與射極區域離間形成 的N+型之基極接觸區域及形成於基極區域之表面區域且使 元件間電性分離之P +型之隔離區域。 使電流流到具有如此構造之半導體元件，則來自射極區 域的電流不僅流向集極區域，亦分散流向基極接觸區域及 隔離區域。因此，電晶體作動時產生漏電流（洩漏電流"電 晶體之電流放大率降低。於是，為了防止洩漏電流的產生， 專利文獻1提出了以集極區域包圍射極區域周圍之構造的 橫向PNP電晶體。 專利文獻1所示之橫向PNP電晶體的集極區域，因係與射 極區域離間同時包圍射極區域之構造，故由射極區域流出 之電流之大部分流入集極區域44。此結果，可以防止於電 晶體作動時洩漏電流之產生。 且說，欲以高電流位準使用橫向PNP電晶體，同時某程 98267.doc 1270144 度維持電流放大率時，必須並聯連接橫向pNp電晶體，或 加長射極周圍長度。惟，並聯連接橫向PNP電晶體，則隨 著輸出電流之增加，平行連接之橫向PNP電晶體的數目變 夕，使得電路尺寸變大。另一方面，加長射極周圍長度， 則射極面積之比例變大，導致電流放大率的降低。 採用如此之元件構造的橫向PNP電晶體，具備射極區域 之側面部的電晶體及射極區域之底面部的電晶體。因底面 部之電晶體的基部幅寬較側面部之電晶體大，故一般底面 部之電晶體的電流放大率較側面部之電晶體的電流放大率 低相當多。由於底面部之電晶體的電流放大率較側面部 低，故橫向PNP電晶體整體的電流放大率降低。究其原因， 例如側面部之電晶體的電流放大率作為1〇〇，底面部之電晶 體的電流放大率作為1〇。於等效電路中因由於電晶體為並 排，電流變為1/2，故側面部之電晶體的電流放大率變為 50,底面部之電晶體的電流放大率變為5。因此，橫向pNp 電晶體整體之電流放大率為55。如此，由於有基部幅寬長 的底面部之電晶體，而造成橫向PNp電晶體整體之電流放 大率降低。 專利文獻1 :特開平10-270458號公報 【發明内容】 [發明欲解決之課題] 本發明係鑑於上述之實情所完成者，以提供可以提高電 流放大率之半導體元件為目的。 此外，本發明以提供可以抑制由射極區域之底面流至集 98267.doc 1270144 極區域之電流的半導體元件為目的。 再者，本發明以提供即使相對於射極周圍長之射極面積 之比例變大，電流放大率亦不易降低之半導體元件為目的。 [解決課題之手段] 為達成上述之目的，有關本發明第丨觀點之半導體元件之 特徵在於具備·· 第1導電型之第1半導體區域； 、第2導電型之第2半導體區域，其形成於前述第丨半導體區 域之表面區域； 、第2導電型之第3半導體區域，其以與前述第2半導體區離 域之方式般形成於前述第i半導體區域之表面區域；及 電流抑制區域，其以覆蓋前述第2半導體區域之至少底面 之方式形成於前述第1半導體區域與前述第2半導體區域之 間，抑制經由前述第丨半導體區域而由前述第2半導體區域 之底面流至前述第3半導體區域之電流。 前述電流抑制區域為雜質濃度較前述第丨半導體區域高 之第1導電型之半導體區域亦可。 前述電流抑制區域由絕緣體所構成亦可。 前述電流抑制區域之絕緣體為以〇2亦可。 月述第3半導體區域為環狀，以包圍前述第2半導體區域 之方式形成亦可。 有關本叙明之第2觀點之半導體元件之特徵在於具備： 第1導電型之第1半導體區域； 第2V電型之第2半導體區域，其形成於前述第丨半導體區 98267.doc 1270144 域之表面區域； 第2導電型之第3半導體區域，其以與前述第2半導體區域 離間同時包圍該第2半導體區域之方式形成於前述第i半導 體區域之表面區域；及 、電流抑制區域’其以覆蓋前述第2半導體區域之底面之方 式形成於前述第1半導體區域與前述第2半導體區域之間， 抑制經由前述第1半導體區域而由前述第2半導體區域之底 面流至前述第3半導體區域之電流。 一 刚述電流抑制區域為雜質濃度較前述第1半導體區域高 之第1導電型之半導體區域亦可。 前述電流抑制區域由絕緣體所構成亦可。 前述電流抑制區域之絕緣體為以〇2亦可。 · 前述第3半導體區域為環狀，以包圍前述第之半導體區域， 之方式形成亦可。 有關本發明之第3觀點之半導體元件之特徵在於具備： 第1導電型之第1半導體區域； 八 第2導電型之第2半導體區域，其形成於前述第4導體區φ 域之表面區域； 第2導電型之第3半導體區域，其以與前述第2半導體區域 離間之方式形成於前述第丨半導體區域之表面區域； 第1導電型之第4半導體區域，其以與前述第3半導體區域 離間、相對之方式形成於前述第i半導體區域之表面區域； 第2導電型之第5半導體區域，其形成於前述第i半導體1 域之表面區域，將半導體元件間隔開；及 98267.doc 1270144 電流抑制區域，其以覆蓋前述第2半導體區域之至少底面 之方式形成於前述第1半導體區域與前述第2半導體區域之 間’抑制經由前述第4導體區域而由前述第2半導體區域 之底面流至前述第3半導體區域之電流。 有關本發明之第4觀點之半導體元件之製造方法係半導 體元件之製造方法，其特徵在於具備： 選擇性地擴散第2導電型之雜質於第丨導電型之第ι半導 體區域的表面區域，形成第2半導體區域之步驟； 選擇性地擴散第2導電型之雜質於前述p半導體區域的 表面區$，以與前述第2半導體區域離間之方式形成第3半 導體區域之步驟；及 以覆盍第2半導體區域之下面之方式形成電流抑制區域 之步驟。 、前述電流抑制區域係擴散第丨導電型之雜質而形成，以便 成為較前述第1半導體區域高的雜質濃度亦可。 前述電流抑制區域由絕緣體形成亦可。 前述電流抑制區域係離子植入氧原子而形成亦可。 以包圍前述第2半導體區域之方式將前述第3半導體區域 形成環狀亦可。 【發明效果】 、本發明係鑑於上述之實情所完成者’可以提供可提高電 流放大率之半導體元件。 此外’本發明可以提供可抑制由射極區域之底面流至集 極區域之電流的半導體元件。 98267.doc -10- 1270144 再者’本發明可以提供即使相對於射極周圍長之射極面 積之比例變大’電流放大率亦不易降低之半導體元件。 【實施方式】 [實施發明之最佳型態] 以下一面參照圖面一面說明有關本發明之實施型態之半 導體元件。 於圖1及圖2顯示有關本實施型態之半導體元件1之構 造。圖2係半導體元件平面圖，圖1係圖2之一點鏈線a_a， 之剖面圖。半導體元件1係如圖1及圖2所示，具備半導體基 體11、集極電極21、射極電極22及基極電極23。再者，於 圖2省略各電極（集極電極21、射極電極22、基極電極23)等。 半導體基體11係由P型半導體基板12及形成於p型半導體 基板12上之半導體層20所構成。 P型半導體基板12係藉由擴散P型雜質（例如硼）於單晶石夕 基板而形成。 半導體層20係藉由於P型半導體基板12上使N型之半導體 層例如磊晶成長而形成。半導體層20具有基極區域13、射極 區域14、集極區域15、基極接觸區域16、電流抑制區域17 及隔離（分離）區域18。 基極區域13係半導體層20之中藉由隔離區域is區隔開之 島狀的區域。 射極區域14係由具有P型之導電性的半導體區域所構 成，形成於基極區域13之表面區域。 集極區域15係由具有P型之導電性的半導體區域所構 98267.doc 1270144 成形成於基極區域13之表面區域。集極區域15以與射極 區域14離間同時包圍射極區域14之方式形成例如環狀。 基極接觸區域16係由具有N型之導電性的半導體區域所 構成，形成於基極區域13之表面區域。基極接觸區域16有 較基極區域丨3高的雜質濃度，於包夾集極區域15而與射極 區域14相對的位置上，與射極區域14離間而形成。 電流抑制區域17以覆蓋射極區域丨4之底面之方式形成於 射極區域14之下方。電流抑制區域17具有抑制由射極區域 14之底面流向集極區域15之電流的功能。於本實施型態 中，電流抑制區域17係由具有N型之導電性的半導體區域所 構成，具有較基極區域13高的雜質濃度。如此，因於射極 區域14之下方开^成電流抑制區域17，故與電流抑制區域1 7 相交之射極區域14之底面部濃度增加，順向電壓增加。因 此，可以抑制由射極區域14之底面流向集極區域15之電流。 隔離區域18以包圍基極區域13之方式形成於p型半導體 基板12上，由具有p型之導電性的半導體區域所構成。隔離 區域18保持於一定之電位，起作用作為將複數元件電性分 離之區域。 絕緣膜19由氧化矽膜等所構成，配置於半導體層2〇之特 定的區域上。絕緣膜19覆蓋半導體基體丨丨之一方的主面， 於對應集極電極21、射極電極22及基極電極23之位置上具 備接觸孔191。經由此接觸孔191，集極區域15、射極區域 14、基極接觸區域μ電性連接於各電極。 集極電極21形成於集極區域15上，經由接觸孔ι91與集極 98267.doc -12- 1270144 區域15電性連接。射極電極22形成於射極區域14上，經由 接觸孔191與射極區域14電性連接。基極電極23形成於基極 接觸區域16上，經由接觸孔191與基極接觸區域16電性連 接。集極電極21、射極電極22及基極電極23分別由鋁、銅、 鎳等金屬所構成。 根據如以上所構成之半導體元件丨，因以覆蓋射極區域i 4 之底面之方式設置電流抑制區域17，故射極區域14之底面 部的順向電壓增加，由射極區域14之底面向集極區域丨5電 流的不易流動。因此，電流由射極區域14之側面部流至集 極區域1 5，可以提高電流放大率。此外，相對於射極周圍 長之射極面積之比例變大時，因電流不易由射極區域14之 底面流向集極區域1 5，故電流放大率亦不易降低。 圖3係顯示設置電流抑制區域丨7之橫向pNp電晶體之等 效電路。圖3中的2個電晶體係射極之側面部的電晶體（Trl) 與底面部的電晶體（Tr2)。如圖3所示，電流流向順向電壓低 之側面部的橫向PNP電晶體，難以流動至底面部的橫向pNp 電晶體。此乃因電流抑制區域17而底面部的橫向pnp電晶 體之順向電壓較側面部的橫向PNP電晶體之順向電壓大之 故。此結果，電流不流至基部幅寬大的底面部之橫向pNp 電晶體，橫向PNP電晶體之電流放大率提高。例如，側面 部之電流放大率為1〇〇 ’底面部之電流放大率為1〇，則橫向 PNP電晶體之電流放大率可以維持大致丨〇〇。 繼之’邊參照圖4及圖5邊說明有關如以上所構成之半導 體元件1之製造方法。 98267.doc • 13 - 1270144 首先，擴散導入p型之雜質於單晶矽基板，作成p型半導 體基板12。繼之’如圖4(a)所示’於p型半導體基板12之一 方的主面上例如使用磊晶成長法形成半導體層2〇。 繼之，於半導體層20之一面上形成未圖示之光阻膜，選 擇性地蝕刻形成之光阻膜中對應隔離區域丨8之形成預定區 域之α卩位而形成窗。由此窗離子植入p型雜質（例如硼）至特 定之深度，如圖4(b)所示，形成隔離區域18。如此形成之半 V體層20中，藉由隔離區域18區隔之内側的島區域成為基 極區域13。 繼之，於基極區域13(半導體層2〇)之射極區域14及集極 區域15之形成預定區域上，選擇性地導型雜質（例如硼） 至特疋之深度而擴散，如圖4(c)所示，形成ρ型之射極區域 14及集極區域15。再者，分別形成射極區域14及集極區域 1 5亦可。 繼之，於基極接觸區域16之形成預定區域上，選擇性地 導入Ν型雜質（例如磷）至特定之深度而擴散，如圖5(幻所 示，形成基極接觸區域丨6。 繼之，於電流抑制區域17之形成預定區域上，經由射極 區域14選擇性地離子植入N型雜質（例如磷）至特定之深 度’如圖5(e)所示，形成電流抑制區域17。 繼之，以絕緣膜19覆蓋半導體層20之一面後，如圖5(f) 所不，於絕緣膜19上之特定區域上，形成射極、基極、集 極用之接觸孔191。 繼之，於絕緣膜19上真空蒸鍍金屬（鋁、銅、鎳等）。然 98267.doc 1270144 後，將蒸鍍之金屬選擇性地圖案化，形成經由前述接觸孔 191與集極區域i 5接觸之集極電極21、經由接觸孔191與射 極區域14接觸之射極電極22及經由接觸孔191與基極接觸 區域16接觸之基極電極23。藉由以上之步驟，形成如圖}所 示之本實施型態之半導體元件1。 根據此製造方法，因藉由磊晶成長法形成半導體層2〇， 故基極區域13具有較一定之雜質濃度分佈。此外，於電流 抑制區域17之形成上，因使用離子植入法，故容易控制深 度，可以得到所希望之深度的電流抑制區域17。 再者，本發明不限定於上述之實施型態，可作各種之變 形及應用。 於上述之實施型態中，以使用具有較基極區域13高之雜 質濃度之N型導電性半導體區域於電流抑制區域17之情形 為例說明了本發明，惟電流抑制區域17係可以抑制由射極 區域14之底面流向集極區域15之電流者即可，例如藉由絕 緣層开> 成亦可。此時，由射極區域之上面離子植入例如氧， 於射極區域14之下面形成由si〇2構成之絕緣膜。 此外，於上述之實施型態中，以藉由離子植入法形成電 流抑制區域17之情形為例說明了本發明，惟例如以熱擴散 法形成亦可。 於上述之貫;型態中，集極區域15以與射極區域1 *離間 同時包圍射極區域14之方式形成環狀之情形為例說明了本 發明，惟與射極區域14離間形成即可，以包圍射極區域14 之方式未形成環狀亦可。例如以與射極區域14離間之方式 98267.doc -15- 1270144 形成之情形亦可。於此情形，若以覆蓋射極區域i4之至少 底面之方式形成電流抑制區域17，則可以抑制由射極區域 14之底面流向集極區域15之電流，可以提高電流放大率。 於上述之實施型態中，以PNP電晶體之情形為例說明了 本發明之半導體元件i，惟半導體元件丨亦可以作為使用於 NPN電晶體者而形成。 此外，有關本發明之半導體元件丨的製造方法不限於上述 實施型態說明之方法，按照需要可以更替步驟之順序或採 用別的步驟。於上述實施型態中，已舉藉由磊晶成長法形 成半導體層20之情形為例說明，惟不限於此，例如亦可擴 散導入N型雜質於P型半導體基板12而形成半導體層2〇。 根據本發明，可以提供可提高電流放大率之半導體元件。 此外，根據本發明，可以提供可抑制由射極區域之底面 流至集極區域之電流的半導體元件。 再者，根據本發明，可以提供即使相對於射極周圍長之 射極面積之比例變大，電流放大率亦不易降低之半導體元 件。 本專利申請係基於2003年12月12曰作成之曰本國專利申 請特願2003-415523號。將其說明書、專利請求範圍、圖面 全體作為參照而取入於本說明書中。 [產業上利用之可能性] 本發明可以應用於具備使用於類比積體電路之橫向構造 的半導體元件。 【圖式簡單說明】 98267.doc -16- 1270144 圖1係本實施型態之半導體元件之剖面圖 圖2係本發明之實施型態之半導體元件的平面圖。 圖3係顯不彡又置電流抑制區域時之橫向pNp電晶體之等 效電路。 圖4(a)-4(c)係用以說明本實施型態之半導體元件的製造 方法之圖。 圖5(d)-5(f)係用以說明本實施型態之半導禮元件的氩& 方法之圖。 【主要元件符號說明】 11 半導體基體 12 P型半導體基板 13 基極區域 14 射極區域 15 集極區域 16 基極接觸區域 17 電流抑制區域 18 離區域 19 絕緣膜 20 W型半導體層 21 集極電極 22 射極電極 23 基極電極 98267.doc -17-BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a lateral structure and a method of fabricating the same. [Prior Art] In the analog integrated circuit, a lateral PNP transistor having a structure in which an emitter, a collector, and a base are adjacent to each other in a horizontal direction is used. A semiconductor device used for a lateral pNp transistor, for example, a base region including an N-type region, a P+ type emitter region formed on a surface region of a base region, and a surface region of the base region formed in a manner spaced apart from the emitter region a collector region of the P+ type, a collector collector region, and an N+ type base contact region formed at a position opposite to the emitter region and an emitter region, and a surface region formed in the base region and electrically interposed between the components Separated P + type isolation area. When current is flown to the semiconductor element having such a configuration, current from the emitter region flows not only to the collector region but also to the base contact region and the isolation region. Therefore, leakage current is generated when the transistor is actuated (leakage current " current amplification factor of the transistor is lowered. Therefore, in order to prevent generation of leakage current, Patent Document 1 proposes a lateral PNP in which the collector region surrounds the structure around the emitter region. In the collector region of the lateral PNP transistor shown in Patent Document 1, since the emitter region is surrounded by the emitter region, most of the current flowing from the emitter region flows into the collector region 44. This result can prevent the leakage current from being generated when the transistor is activated. Moreover, if the lateral PNP transistor is to be used at a high current level and the current amplification factor is maintained at a certain degree of 98267.doc 1270144 degrees, the lateral pNp transistor must be connected in parallel. , or lengthening the length around the emitter. However, if the lateral PNP transistor is connected in parallel, as the output current increases, the number of parallel connected PNP transistors becomes larger, which makes the circuit size larger. On the other hand, the extended emitter The surrounding length, the ratio of the emitter area becomes larger, resulting in a decrease in current amplification. Transverse PNP electro-crystals constructed with such components The transistor having the bottom surface portion of the emitter region and the bottom portion of the emitter region. Since the base portion of the transistor at the bottom portion is larger than the transistor of the side portion, the current of the transistor at the bottom portion is generally amplified. The current amplification rate of the transistor is lower than that of the side portion. Since the current amplification factor of the transistor at the bottom portion is lower than that of the side portion, the current amplification factor of the lateral PNP transistor as a whole is lowered. For example, the side portion is The current amplification factor of the transistor is 1 〇〇, and the current amplification factor of the transistor at the bottom portion is 1 〇. In the equivalent circuit, since the current is 1/2 due to the parallel arrangement of the transistors, the transistor of the side portion is The current amplification factor becomes 50, and the current amplification factor of the transistor at the bottom portion becomes 5. Therefore, the current amplification factor of the entire lateral pNp transistor is 55. Thus, since there is a transistor having a base portion having a long base width, The present invention is based on the above-mentioned facts, and the present invention is completed in view of the above-mentioned facts. Further, the present invention has an object of providing a semiconductor element capable of suppressing a current flowing from a bottom surface of an emitter region to a pole region of a set 98267.doc 1270144. Further, the present invention In order to provide a semiconductor element in which the ratio of the area of the emitter which is longer than the circumference of the emitter is increased, the current amplification factor is not easily lowered. [Means for Solving the Problem] In order to achieve the above object, the semiconductor relating to the first aspect of the present invention is provided. The device is characterized by comprising: a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type formed on a surface region of the second semiconductor region; and a third semiconductor region of a second conductivity type And forming a surface region of the i-th semiconductor region so as to be delocalized from the second semiconductor region; and forming a current suppressing region on the first semiconductor region so as to cover at least a bottom surface of the second semiconductor region Between the second semiconductor region and the second semiconductor region, the second semiconductor region is prevented from passing through the second semiconductor region Current flowing to the bottom surface of the third semiconductor region. The current suppressing region may be a semiconductor region of a first conductivity type in which the impurity concentration is higher than that of the second semiconductor region. The current suppression region may be formed of an insulator. The insulator of the current suppression region may be 〇2. The third semiconductor region described in the month is annular and may be formed to surround the second semiconductor region. The semiconductor device according to the second aspect of the present invention is characterized by comprising: a first semiconductor region of a first conductivity type; and a second semiconductor region of a second V electrical pattern formed on a surface of the second semiconductor region 98267.doc 1270144 a third semiconductor region of the second conductivity type formed in a surface region of the i-th semiconductor region so as to surround the second semiconductor region while surrounding the second semiconductor region; and a current suppression region The bottom surface of the second semiconductor region is formed between the first semiconductor region and the second semiconductor region, and suppresses a current flowing from the bottom surface of the second semiconductor region to the third semiconductor region via the first semiconductor region . The current suppression region may be a semiconductor region of a first conductivity type in which the impurity concentration is higher than that of the first semiconductor region. The current suppression region may be formed of an insulator. The insulator of the current suppression region may be 〇2. The third semiconductor region may be formed in a ring shape so as to surround the first semiconductor region. A semiconductor device according to a third aspect of the present invention includes: a first semiconductor region of a first conductivity type; and a second semiconductor region of an eighth conductivity type formed in a surface region of the fourth conductor region φ domain; a third semiconductor region of the second conductivity type is formed on a surface region of the second semiconductor region so as to be spaced apart from the second semiconductor region; and a fourth semiconductor region of the first conductivity type and the third semiconductor region a second surface region of the second conductivity type formed in a surface region of the ith semiconductor 1 region to space the semiconductor elements; and 98267.doc 1270144 a current suppressing region formed between the first semiconductor region and the second semiconductor region so as to cover at least a bottom surface of the second semiconductor region, and suppressing flow from a bottom surface of the second semiconductor region via the fourth conductor region Current to the third semiconductor region. A method of manufacturing a semiconductor device according to a fourth aspect of the present invention, characterized in that the method for producing a semiconductor device is characterized in that: selectively diffusing a second conductivity type impurity into a surface region of a first semiconductor region of a second conductivity type a step of selectively diffusing a second conductivity type impurity in a surface region $ of the p semiconductor region to form a third semiconductor region so as to be spaced apart from the second semiconductor region; and The step of forming a current suppression region in a manner below the semiconductor region. The current suppression region is formed by diffusing impurities of the second conductivity type so as to have a higher impurity concentration than the first semiconductor region. The current suppression region may be formed of an insulator. The current suppression region may be formed by ion implantation of an oxygen atom. The third semiconductor region may be formed in a ring shape so as to surround the second semiconductor region. [Effect of the Invention] The present invention has been made in view of the above facts, and a semiconductor element capable of improving current amplification can be provided. Further, the present invention can provide a semiconductor element which can suppress a current flowing from the bottom surface of the emitter region to the collector region. 98267.doc -10- 1270144 Further, the present invention can provide a semiconductor element in which the ratio of the emitter area longer than the circumference of the emitter becomes large, and the current amplification factor is not easily lowered. [Embodiment] [Best Mode of Carrying Out the Invention] A semiconductor element according to an embodiment of the present invention will be described below with reference to the drawings. The structure of the semiconductor device 1 of the present embodiment is shown in Figs. 1 and 2. 2 is a plan view of a semiconductor element, and FIG. 1 is a cross-sectional view of a dot chain line a_a of FIG. As shown in Figs. 1 and 2, the semiconductor element 1 includes a semiconductor substrate 11, a collector electrode 21, an emitter electrode 22, and a base electrode 23. Further, each electrode (collector electrode 21, emitter electrode 22, base electrode 23) and the like are omitted in Fig. 2 . The semiconductor substrate 11 is composed of a P-type semiconductor substrate 12 and a semiconductor layer 20 formed on the p-type semiconductor substrate 12. The P-type semiconductor substrate 12 is formed by diffusing a P-type impurity (e.g., boron) on a single crystal substrate. The semiconductor layer 20 is formed by growing an N-type semiconductor layer such as epitaxial growth on the P-type semiconductor substrate 12. The semiconductor layer 20 has a base region 13, an emitter region 14, a collector region 15, a base contact region 16, a current suppressing region 17, and an isolation (separation) region 18. The base region 13 is an island-like region separated by an isolation region is region among the semiconductor layers 20. The emitter region 14 is formed of a semiconductor region having a P-type conductivity and is formed on a surface region of the base region 13. The collector region 15 is formed in a surface region of the base region 13 by a semiconductor region having a P-type conductivity 98267.doc 1270144. The collector region 15 is formed, for example, in a ring shape so as to surround the emitter region 14 while being spaced apart from the emitter region 14. The base contact region 16 is formed of a semiconductor region having an N-type conductivity and is formed on a surface region of the base region 13. The base contact region 16 has a higher impurity concentration than the base region 丨3, and is formed apart from the emitter region 14 at a position opposing the emitter region 14 in the collector collector region 15. The current suppressing region 17 is formed below the emitter region 14 so as to cover the bottom surface of the emitter region 丨4. The current suppressing region 17 has a function of suppressing the current flowing from the bottom surface of the emitter region 14 to the collector region 15. In the present embodiment, the current suppressing region 17 is composed of a semiconductor region having an N-type conductivity and has a higher impurity concentration than the base region 13. As described above, since the current suppressing region 17 is formed below the emitter region 14, the concentration of the bottom portion of the emitter region 14 intersecting the current suppressing region 17 increases, and the forward voltage increases. Therefore, the current flowing from the bottom surface of the emitter region 14 to the collector region 15 can be suppressed. The isolation region 18 is formed on the p-type semiconductor substrate 12 so as to surround the base region 13, and is composed of a semiconductor region having p-type conductivity. The isolation region 18 is maintained at a certain potential and functions as an area for electrically separating the plurality of elements. The insulating film 19 is made of a hafnium oxide film or the like and is disposed on a specific region of the semiconductor layer 2A. The insulating film 19 covers one main surface of the semiconductor substrate, and has a contact hole 191 at a position corresponding to the collector electrode 21, the emitter electrode 22, and the base electrode 23. Via the contact hole 191, the collector region 15, the emitter region 14, and the base contact region μ are electrically connected to the respective electrodes. The collector electrode 21 is formed on the collector region 15 and is electrically connected to the collector 98267.doc -12-127044 region 15 via the contact hole ι91. The emitter electrode 22 is formed on the emitter region 14 and is electrically connected to the emitter region 14 via the contact hole 191. The base electrode 23 is formed on the base contact region 16 and is electrically connected to the base contact region 16 via the contact hole 191. The collector electrode 21, the emitter electrode 22, and the base electrode 23 are each made of a metal such as aluminum, copper, or nickel. According to the semiconductor device 以上 configured as described above, since the current suppressing region 17 is provided so as to cover the bottom surface of the emitter region i 4 , the forward voltage of the bottom portion of the emitter region 14 increases, and the bottom surface of the emitter region 14 faces. The current in the collector region 丨5 is not easy to flow. Therefore, current flows from the side portion of the emitter region 14 to the collector region 15 to increase the current amplification factor. Further, when the ratio of the area of the emitter to the periphery of the emitter becomes large, since the current does not easily flow from the bottom surface of the emitter region 14 to the collector region 15, the current amplification factor is not easily lowered. Fig. 3 shows an equivalent circuit of a lateral pNp transistor in which a current suppressing region 丨7 is provided. In Fig. 3, the transistor (Trl) on the side surface of the emitter of the two electro-crystal system and the transistor (Tr2) on the bottom surface portion. As shown in Fig. 3, the current flows to the lateral PNP transistor of the side portion having a low forward voltage, and it is difficult to flow to the lateral pNp transistor of the bottom portion. This is because the forward voltage of the lateral pnp electric crystal on the bottom surface portion is larger than the forward voltage of the lateral PNP transistor on the side surface portion due to the current suppression region 17. As a result, the current does not flow to the lateral pNp transistor of the bottom portion having a large base width, and the current amplification of the lateral PNP transistor is improved. For example, if the current amplification factor of the side portion is 1 〇〇 'the current amplification factor of the bottom portion is 1 〇, the current amplification factor of the lateral PNP transistor can be maintained substantially 丨〇〇. Next, a method of manufacturing the semiconductor element 1 constructed as described above will be described with reference to Figs. 4 and 5 . 98267.doc • 13 - 1270144 First, a p-type impurity is diffused and introduced into a single crystal germanium substrate to form a p-type semiconductor substrate 12. Then, as shown in Fig. 4(a), the semiconductor layer 2 is formed on the main surface of one of the p-type semiconductor substrates 12 by, for example, epitaxial growth. Then, a photoresist film (not shown) is formed on one surface of the semiconductor layer 20, and a window in which a predetermined region of the corresponding isolation region 丨8 is formed in the photoresist film formed by etching is selectively etched to form a window. The p-type impurity (e.g., boron) is ion implanted into the window to a specific depth, and as shown in Fig. 4(b), the isolation region 18 is formed. In the half V body layer 20 thus formed, the island region inside the partition region 18 is the base region 13. Then, on a predetermined region where the emitter region 14 and the collector region 15 of the base region 13 (semiconductor layer 2) are formed, the impurity (for example, boron) is selectively guided to a depth of the special diffusion, as shown in FIG. As shown in Fig. 4(c), a p-type emitter region 14 and a collector region 15 are formed. Further, the emitter region 14 and the collector region 15 may be formed separately. Then, on the predetermined region where the base contact region 16 is formed, a bismuth-type impurity (for example, phosphorus) is selectively introduced to a specific depth to be diffused, as shown in FIG. 5 (the phantom, the base contact region 丨6 is formed. The N-type impurity (for example, phosphorus) is selectively ion-implanted to a specific depth via the emitter region 14 on the predetermined region where the current suppression region 17 is formed. As shown in FIG. 5(e), the current suppression region 17 is formed. Then, after covering one surface of the semiconductor layer 20 with the insulating film 19, a contact hole 191 for the emitter, the base, and the collector is formed on a specific region on the insulating film 19 as shown in Fig. 5 (f). Then, a metal (aluminum, copper, nickel, etc.) is vacuum-deposited on the insulating film 19. After 98267.doc 1270144, the vapor-deposited metal is selectively patterned to form via the contact hole 191 and the collector region i. 5 contact collector electrode 21, emitter electrode 22 in contact with emitter region 14 via contact hole 191, and base electrode 23 in contact with base contact region 16 via contact hole 191. The above steps are formed as shown in the figure. } The semiconductor element 1 of the present embodiment is shown. In the method, since the semiconductor layer 2 is formed by the epitaxial growth method, the base region 13 has a relatively constant impurity concentration distribution. Further, in the formation of the current suppression region 17, it is easy to control the depth by using the ion implantation method. The current suppression region 17 of a desired depth can be obtained. Further, the present invention is not limited to the above-described embodiment, and various modifications and applications can be made. In the above embodiment, the base region is used. The present invention has been described by taking the case where the N-type conductive semiconductor region having a high impurity concentration is in the current suppressing region 17, but the current suppressing region 17 is capable of suppressing the current flowing from the bottom surface of the emitter region 14 to the collector region 15 Alternatively, it may be formed by an insulating layer. At this time, an insulating film made of si 〇 2 is formed under the emitter region 14 by ion implantation of, for example, oxygen on the upper surface of the emitter region. In the embodiment, the present invention has been described by taking the case where the current suppressing region 17 is formed by ion implantation, but it may be formed by, for example, a thermal diffusion method. The present invention is described by taking the case where the pole region 15 is formed in a ring shape so as to surround the emitter region 1 while enclosing the emitter region 14 , but the emitter region 14 may be formed apart to surround the emitter region 14 . It is also possible to form a ring shape, for example, 98267.doc -15 - 1270144 in a manner spaced apart from the emitter region 14. In this case, a current suppressing region is formed so as to cover at least the bottom surface of the emitter region i4. 17, the current flowing from the bottom surface of the emitter region 14 to the collector region 15 can be suppressed, and the current amplification ratio can be improved. In the above embodiment, the semiconductor element i of the present invention is illustrated by taking the case of a PNP transistor as an example. However, the semiconductor device 丨 can also be formed as an NPN transistor. Further, the method of manufacturing the semiconductor device of the present invention is not limited to the method described in the above embodiment, and the steps may be replaced or other steps may be employed as needed. In the above embodiment, the case where the semiconductor layer 20 is formed by the epitaxial growth method is described as an example. However, the present invention is not limited thereto. For example, the N-type impurity may be diffused and introduced into the P-type semiconductor substrate 12 to form the semiconductor layer 2 . . According to the present invention, it is possible to provide a semiconductor element which can increase current amplification. Further, according to the present invention, it is possible to provide a semiconductor element which can suppress a current flowing from the bottom surface of the emitter region to the collector region. Further, according to the present invention, it is possible to provide a semiconductor element in which the current amplification ratio is not easily lowered even if the ratio of the area of the emitter which is longer than the periphery of the emitter becomes large. This patent application is based on Japanese Patent Application No. 2003-415523, filed on Dec. 12, 2003. The specification, the scope of the patent request, and the entire drawings are incorporated herein by reference. [Possibility of Industrial Use] The present invention can be applied to a semiconductor element having a lateral structure used for an analog integrated circuit. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view showing a semiconductor device of the present embodiment. FIG. 2 is a plan view showing a semiconductor device according to an embodiment of the present invention. Figure 3 shows an equivalent circuit of a lateral pNp transistor when the current suppression region is present. 4(a)-4(c) are views for explaining a method of manufacturing the semiconductor device of the present embodiment. Figures 5(d)-5(f) are views for explaining the argon & method of the semi-guide element of the present embodiment. [Major component symbol description] 11 Semiconductor substrate 12 P-type semiconductor substrate 13 Base region 14 Emitter region 15 Collector region 16 Base contact region 17 Current suppression region 18 Off region 19 Insulating film 20 W-type semiconductor layer 21 Collector electrode 22 emitter electrode 23 base electrode 98267.doc -17-