JPS59186322A - Photomask testing apparatus - Google Patents

Photomask testing apparatus

Info

Publication number
JPS59186322A
JPS59186322A JP6134583A JP6134583A JPS59186322A JP S59186322 A JPS59186322 A JP S59186322A JP 6134583 A JP6134583 A JP 6134583A JP 6134583 A JP6134583 A JP 6134583A JP S59186322 A JPS59186322 A JP S59186322A
Authority
JP
Japan
Prior art keywords
photomask
coordinates
reference pattern
chip
measured
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6134583A
Other languages
Japanese (ja)
Inventor
Fuminori Kawasaki
川崎 文憲
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP6134583A priority Critical patent/JPS59186322A/en
Publication of JPS59186322A publication Critical patent/JPS59186322A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26

Abstract

PURPOSE:To measure the relative dimensional error between a reference photomask and a tested photomask accurately by a method wherein the coordinates of the reference mask and the coordinates of the tested mask are measured and compared. CONSTITUTION:The coordinates of a reference photomask are measured by a coordinates measuring part 32 and the coordinates data are memorized by a memory part 33. In the same way, the coordinates data of a tested photomask are also measured by the coordinates measuring part 32 and memorized by the memory part 33. Then the dimensional difference of whole arrangement, the square rate difference of the arrangement, the difference of each pitch of the arrangement, the dimensional difference of each chip and the difference of the chip rotation against the direction of the arrangement between the reference photomask and the tested photomask are calculated by a comparison processing part 34 according to the both coordinates data memorized by the memory part 33 and indicated to an output part 35. With this constitution, the relative dimensional error of the tested photomask to the reference photomask can be measured accurately.

Description

【発明の詳細な説明】 本発明はフォトマスクの検査装置に係シ特に集積回路の
製造に用いるフォトマスクの検査装置に関するものであ
る。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a photomask inspection apparatus, and more particularly to a photomask inspection apparatus used in the manufacture of integrated circuits.

半導体集積回路の製造には一品種の製造に約5ないし2
0種類のフォトマスクが使用される。各フォトマスク間
のパターンのずれは集積回路の製造歩留特性および信頼
性に直接影響を及ぼすので極力小さくしなければならな
い。しかし集積回路製造用マスクは一品種の製造に用い
られるフォトマスク相互間のパターンの相対的位置のず
れが小さければ絶対位置の精度はそれ程厳しく要求され
ない。このため従来からフォトマスクの品質規格の一つ
としてフォトマスク相互間の比較誤差が着目されてきた
In the production of semiconductor integrated circuits, it takes approximately 5 to 2 to produce one type of semiconductor integrated circuit.
0 types of photomasks are used. The pattern deviation between each photomask must be minimized as it directly affects the manufacturing yield characteristics and reliability of the integrated circuit. However, absolute positional accuracy is not so strictly required for masks for manufacturing integrated circuits as long as the relative positional deviation of patterns between photomasks used for manufacturing one type of mask is small. For this reason, comparative errors between photomasks have traditionally been focused on as one of the quality standards for photomasks.

すなわち−品種の果柄回路用のフォトマスクとして適自
に定める一枚のフォトマスクを比較基準フォトマスクと
し、他のフォトマスク上のパターン位置は、全てこの基
準フォトマスクのパターン位置に対する相対位置誤差を
以て品質管理をする。
In other words, one photomask appropriately determined as a photomask for the fruit pattern circuit of the variety is used as a comparison reference photomask, and all pattern positions on other photomasks are relative position errors with respect to the pattern positions of this reference photomask. Quality control is carried out using

ここで上記フォトマスクパターンの相対位置の誤差の種
類を第1図に示す。同図に於てフォトマスク1上には同
一のチップパターン2が縦横ニ規則正しく配置されてい
る。このフォトマスクに於て基準マスクに対する他のマ
スクのパターンの位置ずれ、マスク製造装置の特性から
次の種類のものが含まれる。すなわち配列全体の寸法3
、配列の直角度4、配列の個々のピッチ5、チップ寸法
6、および配列方向に対するチップの回転7である。
Here, types of errors in the relative positions of the photomask patterns are shown in FIG. In the figure, identical chip patterns 2 are regularly arranged vertically and horizontally on a photomask 1. In this photomask, the following types of misalignment of patterns of other masks with respect to the reference mask are included due to the characteristics of the mask manufacturing apparatus. i.e. the size of the entire array 3
, the squareness of the array 4, the individual pitch of the array 5, the chip dimension 6, and the rotation of the chip with respect to the array direction 7.

従来この相対的な誤差を測定する手段として、フォトマ
スクを光学的に重ね合せてずれ量を測定する方法が用い
られている。しかしながらこの方法によると作業者の感
能にたよるところが大であり、精密な測定が出来ないと
いう不都合が生じていた。本発明は上記従来技術の欠点
を解決されるために々されるものであって、基準となる
第1のフォトマスク上配置された基準パターンの座標及
び該基準となる第1のフォトマスクの基準パターンに対
応する被検査用第2のフォトマスク上に配置された基準
パターンの座標を測定する手段と、両座標の測定値を記
憶する手段と、第1のフォトマスク上に配置された基準
パターンの座標と第2のフォトマスク上の基準パターン
の座標を比較し第1のフォトマスクに対する第2のフォ
トマスクの相対的な寸法誤差を測定する手段とを有する
と吉を%徴さするフォトマスク検査装置を提供するもの
である。以下に図面を用いて不発明の実施例を詳細に説
明する。
Conventionally, as a means for measuring this relative error, a method has been used in which photomasks are optically overlapped and the amount of deviation is measured. However, this method relies heavily on the sensibilities of the operator and has the disadvantage that precise measurements cannot be made. The present invention has been made to solve the above-mentioned drawbacks of the prior art, and includes the coordinates of a reference pattern placed on a first photomask serving as a reference and the reference of the first photomask serving as a reference. means for measuring the coordinates of a reference pattern placed on a second photomask for inspection corresponding to the pattern; means for storing measured values of both coordinates; and a reference pattern placed on the first photomask. and a means for measuring a relative dimensional error of the second photomask with respect to the first photomask by comparing the coordinates of the reference pattern on the second photomask with the coordinates of the reference pattern on the second photomask. The present invention provides an inspection device. Embodiments of the invention will be described in detail below with reference to the drawings.

第2図はフォトマスクの配列全体の寸法を測定の様子を
示すものである。基率フォ]・マスク8上のチップ9上
に配置された基準パターン11、及びチップ10上の基
準パターン12の中心座標をそれぞれ測定する。同様に
被検フォトマスク13上のチップ14上に配置された基
準パターン16、チップ15上の基準パターン17の中
心座標をそれぞれ測定する。ここで基準フォトマスク8
き被検フォトマスク16の配列全体の寸法差は、(”2
 、z、)2+(y、、 yI)2(r4 Z3)2+
(Y4 ys)2で表わされる。ここでxl・・・基準
パターン11のX座標、yl・・・基準パターン11の
X座標、x2・・・基準パターン12のX座標、y2・
・・基準パターン12のX座標1.21−3・・・基準
パターン16のX座標、ys・・基準パターン16のX
座標1.2:4・・・基準パターン17のX座標、y4
・・・基準パターン17のX座標である。
FIG. 2 shows how the dimensions of the entire array of photomasks are measured. The center coordinates of the reference pattern 11 placed on the chip 9 on the mask 8 and the center coordinates of the reference pattern 12 on the chip 10 are respectively measured. Similarly, the center coordinates of the reference pattern 16 placed on the chip 14 and the reference pattern 17 placed on the chip 15 on the photomask 13 to be tested are measured. Here, the reference photomask 8
The dimensional difference of the entire array of photomasks 16 to be tested is ("2
,z,)2+(y,,yI)2(r4 Z3)2+
It is expressed as (Y4 ys)2. Here, xl...X coordinate of the reference pattern 11, yl...X coordinate of the reference pattern 11, x2...X coordinate of the reference pattern 12, y2.
...X coordinate of reference pattern 12 1.21-3...X coordinate of reference pattern 16, ys...X of reference pattern 16
Coordinates 1.2:4...X coordinate of reference pattern 17, y4
. . . is the X coordinate of the reference pattern 17.

第6図は配列の直交度を測定する場合を示すものである
。基準フォトマスク18上のチップ19上に配置された
基準パターン22、チップ20上に配置された基準パタ
ーン26及びチップ21上に配置された基準パターン2
4の中心座標を測定する。
FIG. 6 shows the case of measuring the orthogonality of arrays. A reference pattern 22 placed on the chip 19 on the reference photomask 18, a reference pattern 26 placed on the chip 20, and a reference pattern 2 placed on the chip 21.
Measure the center coordinates of 4.

同様に被検フォトマスク25上のチップ26上に配置さ
れた基準パターン29、チップ27上に配置された基準
パターン60及びチップ28上に配置された基準パター
ン31の測定する。ここでフォトマスク18とフォトマ
スク25の配列の直交度の誤差は(jan ” yI 
3’2)/ (,2++ xz)+tan ’(3’2
 ys)/ (、ra−、r2) ) −(jan ’
 (y4 ys)/ (、;5−、z6) 十tan’
 (3’5 y6)/ (、r6x6月で表わされる。
Similarly, the reference pattern 29 placed on the chip 26 on the photomask 25 to be tested, the reference pattern 60 placed on the chip 27, and the reference pattern 31 placed on the chip 28 are measured. Here, the error in orthogonality between the photomasks 18 and 25 is (jan ” yI
3'2)/ (,2++ xz)+tan'(3'2
ys)/(,ra-,r2))-(jan'
(y4 ys)/ (,;5-,z6) 十tan'
(3'5 y6)/ (, expressed as r6x6 months.

ここでX、・・・基準パターン22のX座標、yI・・
・基準パターン22のX座標、x2・・・基準パターン
23のX座標、y2・・・基準パターン23のX座標、
x3・・・基準パターン24のX座標、ys・・・基準
パターン24のX座標、x4・・・基準パターン29の
X座標、y4・・・基準パターン29のX座標、x5・
・・基準パターン30のX座標、y5−・・基準パター
ン30のX座標、x6・・・基準パターン31のX座標
、y6・・・基準パターン61のX座標である。
Here, X,...X coordinate of the reference pattern 22, yI...
・X coordinate of the reference pattern 22, x2...X coordinate of the reference pattern 23, y2...X coordinate of the reference pattern 23,
x3...X coordinate of the reference pattern 24, ys...X coordinate of the reference pattern 24, x4...X coordinate of the reference pattern 29, y4...X coordinate of the reference pattern 29, x5.
...X coordinate of the reference pattern 30, y5--X coordinate of the reference pattern 30, x6--X coordinate of the reference pattern 31, y6--X coordinate of the reference pattern 61.

同様にして配列の個々のピッチの差、チップ寸法の差お
よび配列方向に対するチップの回転の差においても同様
手段で測定可能である。第4図は本発明の概略を示すブ
ロック線図でちる。座標測定部62で基準フォトマスク
の座標を測定し座標データは記憶部33に記憶される。
Similarly, differences in the pitches of the individual arrays, differences in chip dimensions, and differences in rotation of the chips with respect to the array direction can also be measured by the same means. FIG. 4 is a block diagram showing an outline of the present invention. The coordinate measuring section 62 measures the coordinates of the reference photomask, and the coordinate data is stored in the storage section 33.

同様に被検フォトマスクの座標データも座標測定部52
で測定された後記憶部63に記憶される。ここで必要に
応じて基準フォトマスクと被検フォトマスクの座標デー
タを比較処理部64に転送する。
Similarly, the coordinate data of the photomask to be tested is also stored in the coordinate measurement unit 52.
After being measured, it is stored in the storage unit 63. Here, the coordinate data of the reference photomask and the test photomask are transferred to the comparison processing section 64 as necessary.

比較処理部34は、基準フォトマスク、及び被検フォト
マスクの座標データから、基準フォトマスクと被検フォ
トマスクの配列全体の寸法の差配列の直交度の差、配列
の個々のピッチ差、チップ寸法差、及び配列方向に対す
るチップの回転の差を算出し、出力部65により表示す
るわけである。
The comparison processing unit 34 calculates, from the coordinate data of the reference photomask and the test photomask, the difference in dimensions of the entire array of the reference photomask and the test photomask, the difference in orthogonality of the arrays, the individual pitch difference in the array, and the chip. The dimensional difference and the difference in rotation of the chips with respect to the arrangement direction are calculated and displayed by the output unit 65.

以上のべた様に本発明によるマスク相互間の比較誤差の
測定装置によれば作業者の感能にたよることなく精度の
高い測定を行うことができる効果を有するものである。
As described above, the apparatus for measuring comparison errors between masks according to the present invention has the effect of being able to perform highly accurate measurements without relying on the sensibility of the operator.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はフォトマスクパターンの相対位置の誤差の種類
を示す図、第2図は本発明におけるフォトマスクの配列
全体の寸法側の様子を示す図、第3図は本発明における
フォトマスクの配列の直交度の測定の様子を示す図。又
第4図は本発明装置のブロック図である。 1・・・フォトマスク、2・・・チップパターン、ろ・
・・配列全体の寸法、4・・・配列の直交度、5・・・
配列の個々のピッチ、6・・・チップ寸法、7・・・配
列方向に対するチップの回転、8・・・基準フォトマス
ク、9・・・チップ、10・・・チップ、11・・・基
準パターン、12・・基準パターン、13・・被検フォ
トマスク、14・・・チップ、15・・・チップ、16
・・・基準パターン、17・・・基準パターン、18・
・・基準フォトマスク、19・・・チップ、20・・・
チップ、21・・・チップ、22・・基準パターン、2
6・・・基準パターン、24・・・基準パターン、25
・・・被検フォトマスク、26・・・チップ、27・・
・チップ、28・・・チップ゛、29・・基準パターン
、60・・・基準ノくターン、51・・・基に店パター
ン、32・・・座標測定部、63・・言己憶音b、64
・・・比較処理部、35・・・出力部。 特許出願人 日本電気株式会社 代理人 弁理士 菅 野   中 第1図 / 第4図
Fig. 1 is a diagram showing the types of errors in the relative position of photomask patterns, Fig. 2 is a diagram showing the dimensions of the entire photomask array in the present invention, and Fig. 3 is a diagram showing the photomask arrangement in the present invention. FIG. 3 is a diagram showing how the degree of orthogonality is measured. FIG. 4 is a block diagram of the apparatus of the present invention. 1...Photomask, 2...Chip pattern, ro・
... Dimensions of the entire array, 4... Orthogonality of the array, 5...
Individual pitch of the array, 6... Chip dimension, 7... Rotation of the chip with respect to the array direction, 8... Reference photomask, 9... Chip, 10... Chip, 11... Reference pattern , 12... Reference pattern, 13... Test photomask, 14... Chip, 15... Chip, 16
...Reference pattern, 17...Reference pattern, 18.
...Reference photomask, 19...Chip, 20...
Chip, 21...Chip, 22...Reference pattern, 2
6... Reference pattern, 24... Reference pattern, 25
...Test photomask, 26...Chip, 27...
・Chip, 28...Chip ', 29...Reference pattern, 60...Reference number turn, 51...Store pattern based on, 32...Coordinate measurement unit, 63...Word memory b, 64
. . . Comparison processing section, 35 . . . Output section. Patent applicant NEC Corporation Representative Patent attorney Naka Kanno Figure 1/Figure 4

Claims (1)

【特許請求の範囲】[Claims] 基準となる第1のフォトマスク上に配置された基準パタ
ーンの座標及び該基準となる第1のフォトマスク上の基
準パターンに対応する被検査用の第2のフォトマスク上
に配置された基準パターンの座標を測定する手段と、両
座標の測定値を記憶する手段と、第1のフォトマスク上
に配置された基準パターンの座標と第2のフォトマスク
上の基準パターンの座標を比較し第1のフォトマスクに
対する第2のフォトマスクの相対的な寸法誤差を測定す
る手段とを有することを特徴とするフォトマスク検査装
置。
Coordinates of a reference pattern placed on a first photomask serving as a reference and a reference pattern placed on a second photomask to be inspected corresponding to the reference pattern on the first photomask serving as a reference a means for measuring the coordinates of the first photomask; a means for storing the measured values of both coordinates; A photomask inspection apparatus comprising means for measuring a relative dimensional error of a second photomask with respect to the second photomask.
JP6134583A 1983-04-07 1983-04-07 Photomask testing apparatus Pending JPS59186322A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6134583A JPS59186322A (en) 1983-04-07 1983-04-07 Photomask testing apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6134583A JPS59186322A (en) 1983-04-07 1983-04-07 Photomask testing apparatus

Publications (1)

Publication Number Publication Date
JPS59186322A true JPS59186322A (en) 1984-10-23

Family

ID=13168448

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6134583A Pending JPS59186322A (en) 1983-04-07 1983-04-07 Photomask testing apparatus

Country Status (1)

Country Link
JP (1) JPS59186322A (en)

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