JP2012023278A - Semiconductor device and method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an inspection process capable of reducing, especially, the time required for probe inspection of a semiconductor integrated circuit formed on a semiconductor substrate.SOLUTION: On a semiconductor substrate to be tested, a circuit region 2a including a semiconductor integrated circuit body is formed and a TEG 3a is formed in a scribe area adjacent to the circuit region 2a. Rows of first pad electrodes 5a and 5b are provided in the circuit region 2a, and a row of second pad electrodes 6 is provided in the TEG 3a. The first pad electrodes 5a adjacent to the TEG 3a are arranged so as not to face the second pad electrodes 6. Probe needles 8a, 8b, and 9 are contacted to the first pad electrodes 5a and 5b and the second pad electrodes 6 arranged in that state, and then the inspection of the semiconductor integrated circuit and the measurement of the TEG are simultaneously performed.

Description

  The present invention relates to a technique of a probe inspection process that occupies a part close to a final process in a series of manufacturing processes in a semiconductor integrated circuit.

  In general, in a semiconductor integrated circuit manufacturing process, a semiconductor integrated circuit body, a TEG (Test Element Group), an accessory pattern such as an alignment mark, and the like are formed on a semiconductor wafer. Among these, the TEG and the accessory are usually formed on a scribe area provided between the semiconductor integrated circuit body forming regions. The TEG is composed of an evaluation element group for evaluation of manufacturing process variation, evaluation of semiconductor element characteristics, or evaluation of a semiconductor integrated circuit main body, which is generally called a diffusion process. With respect to an integrated circuit, it is possible to elucidate the cause of the failure by analyzing the electrical characteristics of the TEG that is present at the location closest to the position on the semiconductor wafer where the defective semiconductor integrated circuit was formed. . For this reason, it is meaningful to arrange the TEG on the scribe area.

  Another purpose of the TEG is to measure the element characteristics of transistors and the like mounted on the TEG, analyze the relationship between the measured element characteristics and the yield of the semiconductor integrated circuit body, and finally The manufacturing process conditions are finely adjusted so as to obtain a device characteristic such that the yield, that is, the yield rate of non-defective products is high. In this sense, the role of TEG is extremely important.

  On the other hand, accessories are various patterns for controlling or evaluating the manufacturing process without depending on the measurement of electrical characteristics. For example, an alignment mark is one of accessories, and is provided for alignment that aligns a circuit pattern already formed on a semiconductor wafer and a design pattern on a photomask in the next process with an optimal relative positional relationship. . An example of a method of arranging the TEG and accessories in the scribe area as described above is disclosed in Patent Document 1.

  FIG. 9 is a diagram for explaining the arrangement of chips and TEGs formed on a semiconductor wafer when exposure is performed with a one-shot / 4-chip described in Patent Document 1. In FIG. In FIG. 9, four semiconductor chips 50a, 50b, 50c, and 50d are formed in one shot area SA, and four TEGs 52a, 52b, 52c, and 52d are provided in the scribe area 51 near each corner of these chips 50a to 50d. Is provided. A TEG 52e is provided at the center of the four chips 50a to 50d.

  As described above, the probe test is performed on the semiconductor wafer on which the TEG is disposed. In the probe test, the electrical characteristics of the TEG formed on the semiconductor wafer are first tested and then formed on the semiconductor chip. The electrical characteristics of the integrated circuit in the semiconductor chip are tested by applying a probe needle to the bonded pad. Then, when a defect in electrical characteristics is detected in any of the semiconductor chips 50a to 50d by arranging the TEG in one shot as shown in FIG. 9, the inspection result of the probe test for the TEG closest to the defect region, or The cause of the characteristic failure is detected from the dimensional variation in the shot.

JP 2001-085309 A

  However, in the conventional probe inspection process as described in Patent Document 1, it is usual that the electrical characteristic inspection of the integrated circuit in the semiconductor chip and the measurement of the electrical characteristics for the TEG formed on the scribe area are performed separately. It is. In this case, at least two types of probe cards dedicated for integrated circuit inspection and TEG measurement are prepared, and inspection is continued by exchanging these probe cards in the middle of the inspection process. Resetting of the inspection conditions including the replacement of the time required a relatively long time, and the ratio of the time occupied in the inspection process could not be ignored, and there was a problem that the number of process steps increased. In addition, as described above, it is difficult to reduce the cost of the inspection process because a plurality of probe cards are required and a plurality of inspection facilities are required depending on circumstances.

  The present invention solves the above-described conventional problems, and can reduce the time required for the inspection process of a semiconductor integrated circuit, or can suppress an increase in probe cards and inspection equipment for inspection. It is an object of the present invention to provide a method of manufacturing a semiconductor device including the inspection method and a semiconductor device corresponding to the inspection method.

  First, a first semiconductor device configured to be suitable for an inspection process of a semiconductor device according to the present invention for solving the above-described problems is arranged in a semiconductor integrated circuit and a column extending in one direction and A circuit region having a plurality of first pad electrodes electrically connected to the semiconductor integrated circuit, and a plurality of rows arranged in rows extending in a direction along the one direction in a scribe area adjacent to the circuit region The second pad electrodes are formed on the substrate, and each of the first pad electrodes and each of the second pad electrodes are formed at positions that do not face each other in a direction orthogonal to the one direction. It is.

  In this semiconductor device, the semiconductor integrated circuit is manufactured in a scribe area adjacent to the circuit area and extending in a direction perpendicular to the scribe area in which the plurality of second pad electrodes are arranged by a method other than electrical characteristic measurement. An accessory region may be formed that includes a test pattern for evaluating the process, and it is desirable to do so.

  A second semiconductor device according to the present invention includes a semiconductor integrated circuit, a test circuit for inspecting characteristics of the semiconductor integrated circuit, the semiconductor integrated circuit or the test circuit, and the semiconductor integrated circuit A plurality of first pad electrodes used when inspecting circuit characteristics, and a plurality of second pad electrodes electrically connected to the semiconductor integrated circuit and not used when inspecting characteristics of the semiconductor integrated circuit. And a plurality of third pad electrodes arranged in a row extending in one direction in a scribe area adjacent to the circuit region, and the third pad electrode is formed on the substrate. It is formed at a position facing the second pad electrode and not facing the first pad electrode.

  In the second semiconductor device, the plurality of second pad electrodes are continuously arranged in a row extending in the direction along the one direction, and the row of the third pad electrodes is the row of the second pad electrodes. Can be opposed to each other.

  If desired, the test circuit includes a BIST circuit, and the first pad electrode includes a pad electrode for driving the BIST circuit.

  Furthermore, an accessory region including a test pattern for evaluating the manufacturing process of the semiconductor integrated circuit by a method other than electrical characteristic measurement may be formed in an arbitrary scribe area adjacent to the circuit region.

  Next, a first method of manufacturing a semiconductor device including a semiconductor device inspection process according to the present invention for solving the above-described problems is a semiconductor integrated circuit, and a semiconductor array arranged in a row extending in one direction and the semiconductor. A circuit region having a plurality of first pad electrodes electrically connected to an integrated circuit; a test element for performing an evaluation relating to manufacture of the semiconductor integrated circuit; and the one-way electrically connected to the test element Each of the first pad electrodes and a plurality of second pad electrodes arranged so as not to oppose each other in a direction perpendicular to the one direction. And a step of preparing a substrate on which a TEG provided in a scribe area adjacent to the circuit region is formed, and the first pad electrode and the second pad electrode on the substrate. Contacting the lobe needle, comprising an inspection step for inspecting and measuring of the TEG of the semiconductor integrated circuit.

  In the manufacturing method, the plurality of sets of the first pad electrode and the second pad electrode made of the circuit region and the TEG are brought into contact with probe needles, and the semiconductor regions included in the circuit regions of the plurality of sets, respectively. Circuit inspection and measurement of the TEG for each of the plurality of sets can be performed.

  Further, in a desirable mode of the first semiconductor device manufacturing method, a predetermined number of the circuit regions are arranged in a direction along the one direction, and one TEG is the predetermined number of circuit regions in the scribe area. The probe needle is brought into contact with the first pad electrode formed in the predetermined number of circuit regions and the second pad electrode of the one TEG. Thus, the semiconductor integrated circuit included in each of the predetermined number of circuit regions is inspected and the one TEG is measured.

  Further, the second pad electrode is formed at an intersection between the scribe area that separates each of the predetermined number of circuit regions in the direction along the one direction and the scribe area provided with the TEG. It is effective.

  A second method of manufacturing a semiconductor device including a semiconductor device inspection process according to the present invention includes a semiconductor integrated circuit, a test circuit for inspecting characteristics of the semiconductor integrated circuit, and the semiconductor integrated circuit or the test circuit. A plurality of first pad electrodes that are electrically connected to the semiconductor integrated circuit and used when testing the characteristics of the semiconductor integrated circuit; and when connected to the semiconductor integrated circuit and testing the characteristics of the semiconductor integrated circuit A circuit region having a plurality of second pad electrodes that are not used, a test element for evaluating the manufacture of the semiconductor integrated circuit, and a column electrically connected to the test element and extending in one direction Each of which has a plurality of third pad electrodes arranged to face the second pad electrode and not to face the first pad electrode. And a step of preparing a substrate on which a TEG provided in a scribe area adjacent to the circuit region is formed, and a probe needle is brought into contact with the first pad electrode and the third pad electrode on the substrate. And an inspection process for inspecting the semiconductor integrated circuit and measuring the TEG.

  In the second method for manufacturing a semiconductor device, the inspection of the semiconductor integrated circuit includes an inspection performed by driving the test circuit. In one embodiment, the test circuit includes a BIST circuit, and the first pad electrode includes a pad electrode for driving the BIST circuit.

  In the first and second semiconductor device manufacturing methods described above, it is most desirable to perform the inspection of the semiconductor integrated circuit and the measurement of the TEG at the same time.

  As described above, in the first semiconductor device according to the present invention, the first pad electrode formed in the circuit region and electrically connected to the semiconductor integrated circuit, and the scribe area adjacent to the circuit region are formed. The second pad electrodes are formed at positions that do not face each other. In the second semiconductor device according to the present invention, a first pad electrode that is electrically connected to a semiconductor integrated circuit or a test circuit in the circuit region and is used when testing the characteristics of the semiconductor integrated circuit, and the semiconductor integrated circuit A plurality of second pad electrodes that are electrically connected to the circuit but are not used when testing is formed. The third pad electrode formed in the scribe area adjacent to the circuit region is disposed at a position facing the second pad electrode and not facing the first pad electrode.

  In the semiconductor device manufacturing method including the semiconductor device inspection process according to the present invention, the semiconductor device having the above-described configuration is inspected. Therefore, the second pad electrode and the second semiconductor device of the first semiconductor device are used. When the third pad electrode is a TEG pad electrode, the probe needle can be simultaneously brought into contact with the pad electrode in the circuit region and the TEG pad electrode. Based on this, since the inspection of the semiconductor integrated circuit and the TEG measurement are performed at the same time in the inspection process of the present invention, the inspection process time can be shortened and the inspection cost can be reduced.

FIG. 3 is a diagram showing a pattern layout including a semiconductor device for one exposure shot formed on a semiconductor wafer to be inspected by the inspection method according to the first embodiment of the present invention. The flowchart which shows the inspection method which concerns on this invention. The figure which shows the state which made the probe needle of the probe card contact the semiconductor device and TEG shown in FIG. FIG. 8 is a diagram showing a modification of the pattern layout including the semiconductor device shown in FIG. 1. The figure which shows the pattern layout containing the semiconductor device for 1 exposure shot formed on the semiconductor wafer inspected by the inspection method which concerns on the 2nd Embodiment of this invention. The figure which shows the state which made the probe needle of the probe card contact the semiconductor device and TEG shown in FIG. The figure which shows the pattern layout containing the semiconductor device for 1 exposure shot formed on the semiconductor wafer test | inspected with the test | inspection method which concerns on the 3rd Embodiment of this invention. The figure which shows the state which made the probe needle of the probe card contact the semiconductor device and TEG shown in FIG. The figure which shows the conventional arrangement | positioning of the chip | tip and TEG which were formed in the semiconductor wafer.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment 1)
The semiconductor integrated circuit manufacturing process includes a diffusion process for forming semiconductor elements such as transistors, capacitors, resistors, etc. constituting the integrated circuit by performing fine processing on the silicon wafer and various thin films formed thereon, and the integrated circuit completed. It is composed of an inspection process for inspecting the electrical characteristics or the quality of the function, an integrated circuit chip mounting process, and the like. One of the inspection processes is a probe inspection process for inspecting a large number of integrated circuits formed on a semiconductor wafer.

  FIG. 1 is a diagram showing an example of a planar layout of a semiconductor device used for the inspection method according to the first embodiment of the present invention, particularly the above-described probe inspection. Before explaining the inspection method of the present invention, this semiconductor device will be described. Will be described. FIG. 1 shows a pattern layout in one exposure shot area that is exposed once on a semiconductor wafer such as a silicon substrate by a reduction projection exposure apparatus such as a stepper and a scanner.

  1, four rectangular semiconductor integrated circuit regions (hereinafter referred to as circuit regions) 2a, 2b, 2c, and 2d having the same configuration are arranged in an exposure shot region 1 indicated by a dotted line. The outside of the circuit areas 2a to 2d, that is, the area between the circuit areas 2a to 2d is a scribe area for cutting and separating the circuit areas 2a to 2d into individual pieces of semiconductor integrated circuit chips. Extending in the X direction and Y direction perpendicular thereto. Since such exposure shot areas are arranged in a matrix with a regular pitch on an actual semiconductor wafer, the circuit areas 2a to 2d are also periodically arranged on the almost entire surface of the semiconductor wafer at a constant pitch. Will be.

  In a region adjacent to the left side of each of the circuit regions 2a to 2d on the scribe area, TEGs 3a, 3b, 3c, and 3d including necessary numbers of test elements such as transistors, capacitors, and resistors having various dimensions are provided in the circuit region. 2a to 2d are provided so as to have substantially the same length as one side in the direction along the Y direction. Further, only accessory regions 4a, 4b, 4c, and 4d are provided on the scribe areas adjacent to the upper sides of the circuit regions 2a to 2d. For example, alignment marks, alignment misalignment measurement marks, and film thicknesses used in the photolithography process are provided. Many test patterns for evaluating the manufacturing process of a semiconductor device (semiconductor integrated circuit) by a method other than the measurement of electrical characteristics such as monitor marks are included.

  Next, in the circuit regions 2a to 2d and TEGs 3a to 3d, a probe needle for electrical measurement is brought into contact to apply an electrical signal to the integrated circuit or various test elements, or to extract the electrical signal to the outside. A pad electrode made of a metal film is formed. In the circuit regions 2a to 2d, a plurality of pad electrodes 5a and 5b having the same dimensions are provided in a line along the left and right sides, and these pad electrodes are not shown in the circuit regions 2a to 2d. It is electrically connected to the formed circuit. The distance between the pad electrodes 5b is set to a distance that is sufficient and close to the minimum so that adjacent probe needles do not come into contact with each other when the inspection process is performed, while the pad electrode 5a has a dimension of one pad electrode. These are arranged at a relatively coarse interval.

  Also in the TEGs 3a to 3d, a plurality of pad electrodes 6 having the same dimensions are arranged in a line in the direction along the Y direction in which the scribe area extends, and at a relatively coarse interval that is larger than the dimension of one pad electrode. The electrode 6 is electrically connected to a test element such as a transistor, a capacitor, or a resistor. The direction in which the row of pad electrodes 6 extends is basically the direction along the direction in which the row of pad electrodes 5a extends. In the example of FIG. 1, the row of pad electrodes 6, the row of pad electrodes 5a and 5b, and the circuit regions 2a to 2d. The left and right sides and the Y direction are parallel. Further, as shown in FIG. 1, the individual pad electrodes 5 a and the pad electrodes 6 are arranged at positions that do not directly face each other when viewed in a direction orthogonal to the column direction of the pad electrodes 5 a (direction along the X direction). Accordingly, the pad electrode 5a and the pad electrode 6 are arranged at alternate positions in the vertical direction.

  The patterns, dimensions, structure, arrangement, etc. of the test elements and pad electrodes 6 formed inside each of the TEGs 3a to 3d are all the same, and therefore the four TEGs are the same. In FIG. 1, although the width of the scribe area is drawn large, the actual width is about 100 μm at most, and the same applies to the pattern layout diagrams on all the semiconductor wafers shown below.

  Next, an inspection method according to the present invention for inspecting a semiconductor integrated circuit device on a semiconductor wafer having the above-described configuration will be described. FIG. 2 is a flowchart showing the inspection process. First, for example, a semiconductor wafer is transported and set on a measurement stage from a wafer cassette installed in a prober. It is assumed that circuit regions 2a to 2d, TEGs 3a to 3d and accessory regions 4a to 4d shown in FIG. 1 are formed on the semiconductor wafer. Next, the probe card used for the previous inspection is removed from the prober, and the probe card is replaced with a probe card corresponding to the type of semiconductor integrated circuit to be inspected formed on the semiconductor wafer set on the stage. .

  Next, a prober file for alignment is set in the prober, and horizontal position alignment between each pad electrode 5a, 5b, 6 on the semiconductor wafer and the probe needle is monitored through a monitor CCD camera or the like provided in the prober. Adjust the needle pressure in the vertical direction. FIG. 3 is a diagram showing a state in which probe needles fixed to a probe card are aligned and contacted with various pads on a semiconductor wafer having the pattern layout shown in FIG. Since the probe card body has a known structure in which a multilayer wiring that is electrically connected to the probe needle is provided on a substrate made of resin or the like, the display is omitted in FIG. 3, and a rectangular opening through which the probe needle is exposed is shown. Only 7 is shown.

  The probe needle shown in FIG. 3 is a cantilever type, the probe needle 8a is set in the right direction from the left side of the opening 7 and contacts the pad electrode 5a in the circuit region 2a, and the probe needle 9 is in the same direction from the same side. Is set to contact the pad electrode 6 of the TEG 3a, and the probe needle 8b is set leftward from one side of the right side of the opening 7 and contacts the pad electrode 5b. The probe needles 8a are longer than the probe needles 9, and are alternately arranged along the direction in which the row of pad electrodes 5a and the row of pad electrodes 6 extend. As shown in FIG. 1, the pad electrodes 5a and the pad electrodes 6 are alternately arranged at positions that do not directly face each other in the direction orthogonal to the column direction of the pad electrodes 5a, thereby testing the pad electrodes 5a and TEG connected to the integrated circuit. The probe needles 8a and 9 can be simultaneously brought into contact with the pad electrode 6 connected to the device for use.

  After the alignment between the probe needle and the pad electrode, a circuit using a semiconductor tester (LSI tester) connected to the prober with the probe needles 8a, 8b, 9 in contact with the pad electrodes 5a, 5b, 6 respectively. The inspection of the electrical characteristics of the integrated circuit body formed in the region 2a and the measurement of the electrical characteristics of the TEG 3a are simultaneously performed in parallel. After the inspection / measurement of the circuit area 2a and TEG 3a is completed, the prober stage is moved at a predetermined pitch, and the circuit area 2b, TEG 3b,. In this way, the inspection and measurement for all the dies (chips) on one semiconductor wafer, that is, all the circuit regions and TEGs, and all the semiconductor wafers mounted on the semiconductor wafer cassette are completed.

  As described above, the method for inspecting a semiconductor device according to this embodiment includes the pad electrode 6 in the column of the TEG pad electrode 6 formed in the scribe area and the column of the pad electrode 5a in the adjacent semiconductor integrated circuit region. A semiconductor wafer to be inspected is used in which the relative arrangement with respect to the pad electrode 5a is such that they do not face each other. Then, the probe needle is brought into contact with the pad electrode in the circuit area and the pad electrode in the TEG at the same time, and the inspection of the integrated circuit in the circuit area and the TEG measurement are simultaneously performed.

  In general, since the TEG measurement time is shorter than the integrated circuit inspection time, according to the inspection method of the present embodiment, the time required for the TEG measurement can be obtained by simultaneously performing the integrated circuit inspection and the TEG measurement. Can be absorbed into. Instead of using such an inspection method, the integrated circuit inspection and the TEG measurement may be performed separately and sequentially with the probe needle in the state shown in FIG.

  As described above, in the conventional inspection process, the inspection of the integrated circuit and the measurement of the TEG are performed separately, but it is natural that the pad electrode arrangement on the integrated circuit and the pad electrode arrangement of the TEG are different. At least two types of probe cards dedicated to integrated circuit testing and TEG measurement are required. Therefore, the conventional inspection process is, for example, setting a semiconductor wafer on the stage → changing to the first probe card → prober file setting → probe alignment → TEG measurement → changing to the second probe card → prober file setting → probe alignment → The flow is integrated circuit inspection.

  On the other hand, since the flow of the inspection method according to the present invention is as shown in FIG. 2, according to the inspection method according to the present invention, probe card replacement, prober file setting, and probe alignment are performed one step each from the conventional inspection steps This can be reduced, and at the same time, one expensive probe card can be reduced. In this way, the total inspection time can be shortened, and in some cases, the number of inspection facilities can be reduced to reduce the inspection cost. In the case where a semiconductor integrated circuit device having a predetermined scale is to be inspected, the time required for the inspection process in which the integrated circuit inspection and the TEG measurement are separately performed can be reduced by about 10% compared to the conventional technique. For the inspection process in which the inspection and the TEG measurement are performed at the same time, the time can be reduced by about 25%.

  Note that the pattern layout formed on the semiconductor wafer is not arranged side by side in the Y direction in which the scribe areas where the TEGs 3a to 3d are provided as shown in FIG. It is installed on the scribe area extending in the direction (X direction) and avoiding the TEGs 3a to 3d. Such an arrangement greatly reduces the probability that the probe needle (see FIG. 3) contacts the accessory areas 4a-4d for any reason during the inspection process and damages the test patterns formed therein. There is an advantage that can be.

  The pattern layout configuration including the circuit region shown in FIG. 1 is a typical example of a configuration in which the inspection method according to the present invention can be carried out. However, the configuration is not limited to this, and various modifications are possible. FIG. 4 is a diagram showing a modification of the pattern layout in one exposure shot area in FIG. Also in this example, circuit areas 2a to 2d and accessory areas 4a to 4d are formed in the exposure shot area 1. However, since these are the same as those in FIG. . In the pattern layout of FIG. 4, two TEG groups (20a, 21a), (20b, 21b), (20c) adjacent to the left side of each of the circuit regions 2a to 2d on the scribe area extending in the Y direction. , 21c) and (20d, 21d) are formed with a length substantially the same as the length of the left side of the circuit regions 2a to 2d.

  In each TEG group (20a, 21a) to (20d, 21d), test elements such as transistors and resistors are formed, and a plurality of pad electrodes 22 arranged in a line in the extending direction of the scribe area (Y direction). Are formed and electrically connected to the test element. Further, the pad electrode 22 and the pad electrode 5a in the circuit regions 22a to 22d adjacent to the pad electrode 22 are provided at positions that do not directly face each other in the direction orthogonal to the column direction of the pad electrode 5a, as in the example of FIG. Yes. Even in such a configuration, the probe needles are simultaneously brought into contact with the pad electrodes 22, 5a and 5b, so that the inspection of the circuit regions 2a to 2d and the measurement of the TEG groups (20a, 21a) to (20d, 21d) can be performed simultaneously. 1 has the same effect as the inspection of the semiconductor wafer of FIG. If the TEG is divided into a plurality of parts on the condition that they are arranged in a line in the same scribe area as in this modification, an advantage that the degree of freedom of arrangement increases can be obtained.

(Embodiment 2)
FIG. 5 is a diagram showing a planar pattern layout including a semiconductor device formed on a semiconductor wafer used in the inspection method according to the second embodiment of the present invention. First, a pattern layout including this semiconductor device will be described. In FIG. 5, four rectangular circuit areas 2a, 2b, 2c and 2d having the same configuration are arranged in an exposure shot area 1 indicated by a dotted line exposed by a reduction projection exposure apparatus on a semiconductor wafer. . In the circuit regions 2a to 2d, a plurality of pad electrodes 5a and 5b having the same dimension are provided in a line along one side along the left and right sides, and the circuit regions 2a to 2d not shown are electrically connected to each other. It is connected to the. The circuit regions 2a to 2d, the circuits formed in these circuit regions, and the configurations, dimensions, and arrangement of the pad electrodes 5a and 5b are the same as those in FIG.

  On the scribe area extending in the Y direction outside the circuit regions 2a to 2d and adjacent to the left side of the circuit regions 2a and 2c or the circuit regions 2b and 2d, transistors, capacitors, resistors having various dimensions TEGs 10a and 10b including a necessary number of test elements such as the circuit regions 2a and 2c or the circuit regions 2b and 2d and the total length of the scribe area width extending in the X direction between them The length is continuously provided.

  Test elements such as transistors, capacitors, and resistors are formed in the TEG 10a, and a test element formed in a portion adjacent to the circuit region 2a of the TEG 10a and a test element formed in a portion of the TEG 10a adjacent to the circuit region 2c. The type is different. Further, in the TEG 10a, a plurality of pad electrodes 12, 13, and 14 (hatched pad electrodes) having the same dimensions are arranged in a line along the direction in which the line of the pad electrodes 5a extends. In FIG. 5, the row of pad electrodes 12, 13, and 14, the row of pad electrodes 5a, the left side of the circuit regions 2a and 2c, and the Y direction are substantially parallel. The pad electrodes 12 and 13 are arranged at a relatively coarse interval equal to or larger than the size of one pad electrode, whereas the pad electrodes 14 are not in contact with adjacent probe needles when performing an inspection process, for example. Arranged at intervals close to the minimum and close to the minimum. The pad electrodes 12, 13 and 14 are electrically connected to test elements formed in the vicinity of the respective pads.

  In the pattern layout according to the present embodiment, the pad electrodes 12 and 13 included in the TEG 10a and the pad electrodes 5a in the circuit regions 2a and 2c are arranged in the same relative positional relationship as in the first embodiment. That is, the pad electrodes 12 and 13 and the pad electrode 5a are all arranged at positions that do not directly face each other when viewed in a direction orthogonal to the direction in which the row of pad electrodes 5a extends. As a result, in FIG. 5, the pad electrode 5a and the pad electrodes 12, 13 are arranged at alternate positions in the vertical direction. On the other hand, a portion facing the pad electrode 14 is a scribe area extending in the X direction, and is arranged at a narrow interval as described above regardless of the position of the pad electrode 5a.

  The pad electrode 14 is formed at the intersection of the scribe area extending in the Y direction and the scribe area extending in the X direction by separating the scribe area extending in the Y direction from the scribe area extending in the Y direction and the scribe area extending in the X direction. It is clear that is not opposite. Further, the pattern, dimensions, structure, arrangement and the like of the region of the TEG 10b, the test elements formed in the TEG 10b, and the pad electrodes 12, 13, and 14 are the same as the TEG 10a, that is, the TEG 10b is the same as the TEG 10a.

  Further, only accessory regions 11a and 11b are provided on the scribe area that extends in the X direction and is adjacent to the upper side of each of the circuit regions 2a and 2b. Further, accessory regions 11c and 11d are provided on the scribe area extending in the X direction and adjacent to the upper side of the circuit regions 2c and 2d. The accessory regions 11c and 11d are longer than the accessory regions 4a and 4b in order to avoid overlapping with the TEGs 10a and 10b. Is set short. In these accessory regions 11a to 11d, as in the accessory regions 4a to 4d (FIG. 1) in the first embodiment, a semiconductor device manufacturing process such as an alignment mark for photolithography process, an alignment displacement measurement mark, and a film thickness monitor mark There are many test patterns to evaluate

  The inspection method according to the second embodiment for inspecting the semiconductor device having the pattern layout as described above on the semiconductor wafer is substantially the same as the inspection flow shown in FIG. And the specific contents of the semiconductor device / TEG simultaneous inspection and measurement are different. 6 is a diagram showing a state in which the probe needle fixed to the probe card is in contact with various pads on the semiconductor wafer having the pattern layout of FIG. 5 after the alignment of the probe needle in the inspection flow of FIG. As shown in FIG. 6, each probe needle simultaneously contacts the pads of the two circuit regions 2a and 2c and the TEG 10a.

  The probe needle 16a is set in the right direction from the left side of the opening 15 of the probe card and contacts the pad electrodes 5a in both the circuit areas 2a and 2c, and the probe needle 17a is set in the same direction from the same side to be the pad electrode of the TEG 10a. 12 and 13 and the probe needle 17b is set in the same direction from the same side and contacts the pad electrode 14 of the TEG 10a. Further, the probe needle 16b is set to the left from one side on the right side of the opening 15, and contacts the pad electrodes 5b of both the circuit regions 2a and 2c.

  The probe needle 16a is longer than the probe needles 17a and 17b, and the probe needles 16a and 17a are alternately arranged along the Y direction according to the arrangement of the pad electrodes 5a, 12, and 13. As shown in FIG. 5, the pad electrode 5a and the pad electrodes 12, 13, and 14 are arranged at positions that do not face each other in the direction orthogonal to the direction in which the row of the pad electrodes 5a extends, whereby the integrated circuit of the circuit regions 2a and 2c. The probe needles 16a, 17a and 17b can be simultaneously brought into contact with the pad electrode 5a connected to the pad electrode 12, 13 and 14 connected to the test element of the TEG.

  After the probe needle is brought into contact with the electrode pad as described above, in the simultaneous measurement step of the TEG / integrated circuit characteristics in the inspection flow (FIG. 2), the inspection of the integrated circuits in the circuit regions 2a and 2c and the characteristic measurement of the TEG 10a are performed simultaneously. carry out. Next, the prober stage is moved at a predetermined pitch, and simultaneous inspection / measurement is sequentially performed on the circuit regions 2b, 2d and the TEGs 10b,. As in the case described in the first embodiment, the inspection of the integrated circuit and the measurement of the TEG may be sequentially performed separately with the probe needle contacted as shown in FIG.

  According to the semiconductor device inspection method of the present embodiment, the same effects as those of the first embodiment can be obtained. In addition to this, in the present embodiment, since two circuit areas are simultaneously inspected, the time required for the inspection process can be shortened as compared with the first embodiment. Further, a region adjacent to two circuit regions of the scribe area extending in the Y direction, and an intersection of the scribe area and the scribe area extending in the X direction by separating the two circuit regions from each other are TEG formation regions. Therefore, it is possible to increase the types of test elements built into the TEG as compared with the first embodiment, and to perform a more detailed analysis of the semiconductor device manufacturing process.

  The present embodiment can also be applied to a case where a predetermined number of circuit areas of three or more are simultaneously inspected. Further, this embodiment may be applied to a semiconductor wafer having the pattern layout of FIG. In this case, a probe card in which the probe needle configuration of the probe card shown in FIG. 6 is corrected and the probe needles 17b contacting the pad 14 are removed may be used.

(Embodiment 3)
The semiconductor device to be inspected by the inspection methods according to the first and second embodiments is similar to that of FIG. 1, FIG. 4, or FIG. 5, while preventing the adjacent probe needles from contacting each other. In order to allow the probe needles to come into contact with both pads, the pad electrode spacing is larger than its own dimension, and there is an area margin that can be rearranged relatively freely. However, for example, in recent semiconductor devices such as system LSIs, the number of pad electrodes for signal input / output with respect to the outside is increased to several hundred pins or more in some cases in accordance with miniaturization, higher density, or higher functionality of mounted elements. And there is no space on the chip where the pad electrodes can be freely arranged.

  The semiconductor device inspection method according to the third embodiment of the present invention corresponds to such a semiconductor device. FIG. 7 is a diagram showing a planar pattern layout including a semiconductor device formed on a semiconductor wafer used in the inspection method according to the third embodiment of the present invention. In this embodiment, the semiconductor device is a system LSI. For example.

  A pattern layout including this system LSI will be described. In FIG. 7, a rectangular circuit region 31 is formed in an exposure shot region 30 displayed by a dotted line exposed by a reduction projection exposure apparatus on a semiconductor wafer. An integrated circuit main body region 32 constituting the system LSI is arranged at the center of the circuit region 31. Although not shown in the figure, the integrated circuit main body region 32 has a CPU (Central Processing Unit), ROM (Read Only Memory), RAM (Random Access Memory), port, user logic, and electrical characteristics and functions of the integrated circuit itself. A test circuit for automatically inspecting characteristics such as The test circuit includes a test circuit for inspecting an integrated circuit in a predetermined test mode other than a BIST (Built-in Self Test) circuit and a BIST circuit.

  A plurality of pad electrodes 35 (hatched pad electrodes) and pad electrodes 37 having the same dimensions are formed in a line along the left side on the periphery of the circuit region 31. The pad electrode 35 is a pad electrode for driving and communicating with the BIST circuit in order to perform BIST of the system LSI, and is electrically connected to the BIST circuit. The pad electrode 37 is a pad electrode that is used in an actual use state but is not used in the inspection method according to the present embodiment. In addition, a plurality of pad electrodes 37 having the same dimensions in a row along the right side of the circuit region 31 and not used in this inspection method are continuously formed. All the pad electrodes 37 are electrically connected to the system LSI circuit.

  On the other hand, a plurality of pad electrodes 36 (pad electrodes shaded with dots) are continuously formed in a row in the direction along one side of the upper side and the lower side of the circuit region 31. The pad electrode 36 is used for driving and communicating with a test circuit other than the BIST circuit, and for testing by a method such as applying a signal directly to the system LSI as in the actual use state without using the test circuit. And electrically connected to a test circuit or a system LSI circuit.

  The pad electrodes 35, 36, and 37 formed in the circuit region 31 are sufficient and close to the minimum (for example, one side of the pad electrode) so that adjacent probe needles do not come into contact with each other when the inspection process is performed. It is arranged in length-about half of that).

  The outside of the circuit region 31 is a scribe area. The region on the scribe area extending in the Y direction and adjacent to the right side of the circuit region 31 includes transistors, capacitors, resistors, and the like having various dimensions. A TEG 33 including a required number of test elements is provided, and the length in the direction in which the scribe area extends is a length corresponding to the required number of test elements within a range shorter than the arrangement pitch of the exposure shot regions 30 in the direction. Is set. In the TEG 33, a plurality of pad electrodes 38 having the same dimensions are arranged in a line in a direction along the extending direction (Y direction) of the scribe area, and are electrically connected to test elements formed on the semiconductor wafer.

  Similarly to the pad electrodes 35, 36 and 37, the pad electrode 38 formed in the TEG 33 is sufficiently small and close to the minimum (pad electrode 1) so that adjacent probe needles do not come into contact with each other when the inspection process is performed. The length of the side is about ½ of the length. As shown in FIG. 7, the row of pad electrodes 38 of the TEG 33 is formed in the scribe area so as to face at least the row of pad electrodes 37 not used in the inspection process in the circuit region 31.

  In the example shown in FIG. 7, each pad electrode 38 is opposed to each pad electrode 37 accurately in a direction orthogonal to the direction in which the row of pad electrodes 38 extends. However, it is not always necessary that the individual pad electrodes face each other exactly as described above. However, for example, when a pad electrode used along the right side of the circuit region 31 includes a pad electrode used for the inspection process and a pad electrode not used, the pad electrode 38 of the TEG 33 is inspected in the circuit region 31. It is desirable to place it directly opposite the pad electrode that is not used in the process.

  An accessory region 34 is provided on the scribe area extending in the X direction, which is orthogonal to the scribe area where the TEG 33 is formed and adjacent to the row of pad electrodes 36 used in the inspection process formed in the upper periphery of the circuit region 31. It has been. The accessory region 34 includes a large number of test patterns for evaluating the manufacturing process of the semiconductor device such as an alignment mark for a photolithography process, an alignment measurement mark, and a film thickness monitor mark.

  The inspection process according to the third embodiment for inspecting the semiconductor device (system LSI) having the pattern layout described above on the semiconductor wafer and the TEG can be performed substantially using the inspection flow shown in FIG. A probe card having a dedicated configuration is used for the inspection. 8 is a diagram showing a state in which the probe needle fixed to the probe card is in contact with various pads on the semiconductor wafer having the pattern layout of FIG. 7 after the alignment of the probe needle in the inspection flow of FIG.

  The probe needle 41a is set in the right direction from the left side of the opening 40 of the probe card and contacts only the BIST pad electrode 35 in the circuit area 31, and the probe needle 41b is lowered from the upper side and the lower side of the opening 40, respectively. The probe needle 41c is in contact with the pad electrode 38 of the TEG 33. Further, the probe needle 41c is in contact with the pad electrode 36 for inspection using a test circuit other than the BIST circuit and normal inspection.

  Here, the BIST circuit incorporated in the integrated circuit body region 32 includes a circuit that generates a test pattern used for inspection and a circuit that compresses output determination data. The memory BIST circuit and logic corresponding to the circuit type to be inspected There are BIST circuits. For example, a logic BIST that targets a random logic circuit in a system LSI can inspect a circuit with a very small test pattern by incorporating a random signal generator and an output pattern compressor.

  Therefore, when a test is performed in a specific test mode using a BIST test circuit at the time of inspection, it is possible to inspect with a much smaller number of pad electrodes (number of pins) than when the circuit is driven and inspected in the same state as in actual use. Therefore, some pad electrodes (for example, pad electrode 37) become unnecessary in the inspection process. A test circuit that performs a test in a predetermined test mode other than for BIST has a similar capability. Thus, in the inspection method according to the present embodiment, as shown in FIG. 7, the row of pad electrodes 38 of the TEG 33 is arranged adjacent to and opposed to the row of pad electrodes 37 that are not used for the inspection, or the TEG 33 By arranging the individual pad electrodes 38 to face the individual pad electrodes 37 in the circuit region 31, the probe needles can be simultaneously brought into contact with the pad electrodes 35 and 36 in the circuit region 31 and the pad electrode 38 in the TEG 33. it can.

  After contacting the probe needle to each electrode pad as described above, the system LSI circuit formed in the integrated circuit main body region 32 is changed to the test mode in the simultaneous measurement step of the TEG / integrated circuit characteristics in the inspection flow (FIG. 2). Then, the BIST circuit and other test circuits are driven, and a signal voltage is applied to the pad electrodes not related to these test circuits for inspection, and at the same time, the characteristics of the TEG 33 are measured. Next, the prober stage is moved at a predetermined pitch, and the simultaneous inspection and measurement are repeatedly performed. In the same manner as described in the first embodiment, the inspection of the system LSI circuit and the measurement of the TEG may be sequentially performed separately with the probe needle contacted as shown in FIG.

  According to the present embodiment, the integrated circuit body and the TEG are provided even when there are a large number of pad electrodes provided on the semiconductor device such as a system LSI and there is no space to freely place the pad electrodes at intended positions. Since the time required for the inspection process can be shortened and the number of probe cards can be reduced, the same effects as those of the first embodiment can be obtained.

  As described above, the semiconductor device inspection method according to the present invention and the configuration of the semiconductor device applied to this inspection method shorten the probe inspection process, which is one of a series of semiconductor device manufacturing processes, and reduce the inspection cost. It is useful when trying to do so. The present invention is also effective for other devices manufactured by a manufacturing process similar to a semiconductor device.

1, 30 Exposure shot regions 2a, 2b, 2c, 2d, 31 Semiconductor integrated circuit regions 3a, 3b, 3c, 3d, 10a, 10b, 20a, 20b, 20c, 20d, 21a, 21b, 21c, 21d, 33 TEG
4a, 4b, 4c, 4d, 11a, 11b, 11c, 11d, 34 Accessory regions 5a, 5b, 35, 36 Pad electrodes 6, 12, 13, 14, 22, 38 of the semiconductor integrated circuit region TEG pad electrodes 7, 15, 40 Probe card opening 8a, 8b, 9, 16a, 16b, 17a, 17b, 41a, 41b, 41c Probe needle 32 Integrated circuit body region 37 Pad electrode in semiconductor integrated circuit region not used for inspection

Claims (14)

A semiconductor integrated circuit, and a circuit region having a plurality of first pad electrodes arranged in rows extending in one direction and electrically connected to the semiconductor integrated circuit;
A plurality of second pad electrodes arranged in a row so as to extend in a direction along the one direction in a scribe area adjacent to the circuit region, are formed on the substrate,
Each of the first pad electrodes and each of the second pad electrodes are formed at positions that do not face each other in a direction orthogonal to the one direction.   A test pattern for evaluating a manufacturing process of the semiconductor integrated circuit by a method other than electrical characteristic measurement on a scribe area adjacent to the circuit region and extending in a direction perpendicular to the scribe area where the plurality of second pad electrodes are arranged. 2. The semiconductor device according to claim 1, wherein an accessory region is formed. A semiconductor integrated circuit; a test circuit for inspecting characteristics of the semiconductor integrated circuit; and a plurality of second circuits electrically connected to the semiconductor integrated circuit or the test circuit and used for inspecting characteristics of the semiconductor integrated circuit. A circuit region having one pad electrode and a plurality of second pad electrodes that are electrically connected to the semiconductor integrated circuit and are not used when testing the characteristics of the semiconductor integrated circuit;
A plurality of third pad electrodes arranged in a row extending in one direction in a scribe area adjacent to the circuit region are formed on the substrate,
The semiconductor device, wherein the third pad electrode is formed at a position facing the second pad electrode and not facing the first pad electrode.   The plurality of second pad electrodes are continuously arranged in a row extending in the direction along the one direction, and the third pad electrode row is opposed to the second pad electrode row. The semiconductor device according to claim 3.   5. The semiconductor device according to claim 3, wherein the test circuit includes a BIST circuit, and the first pad electrode includes a pad electrode for driving the BIST circuit.   The accessory region including a test pattern for evaluating a manufacturing process of the semiconductor integrated circuit by a method other than an electrical characteristic measurement is formed in a scribe area adjacent to the circuit region. Semiconductor device. A semiconductor integrated circuit, and a circuit region having a plurality of first pad electrodes arranged in rows extending in one direction and electrically connected to the semiconductor integrated circuit;
A test element for performing an evaluation relating to the manufacture of the semiconductor integrated circuit; and a test element electrically connected to the test element and arranged in a row extending in a direction along the one direction, and each of the first pads Each of the electrodes has a plurality of second pad electrodes arranged so as not to oppose each other in a direction orthogonal to the one direction, and a TEG provided in a scribe area adjacent to the circuit region is formed. Preparing a prepared substrate; and
A semiconductor device manufacturing method, comprising: an inspection step of inspecting the semiconductor integrated circuit and measuring the TEG by bringing a probe needle into contact with the first pad electrode and the second pad electrode on the substrate. Method.   The plurality of sets of the first pad electrode and the second pad electrode made of the circuit region and the TEG are brought into contact with a probe needle to inspect the semiconductor integrated circuit included in each of the plurality of sets and the plurality of sets. The method of manufacturing a semiconductor device according to claim 7, wherein the TEG is measured for each of the sets. A predetermined number of the circuit regions are arranged in a direction along the one direction, and one TEG is provided so as to extend over a region adjacent to the predetermined number of circuit regions in the scribe area,
In the inspection step, a probe needle is brought into contact with the first pad electrode formed in the predetermined number of circuit regions and the second pad electrode of the one TEG, and each of the predetermined number of circuit regions includes The method for manufacturing a semiconductor device according to claim 7, wherein the semiconductor integrated circuit is inspected and the one TEG is measured.   The second pad electrode is formed at an intersection of a scribe area that separates each of the predetermined number of circuit regions in a direction along the one direction and the scribe area provided with the TEG. A method for manufacturing a semiconductor device according to claim 9. A semiconductor integrated circuit; a test circuit for inspecting characteristics of the semiconductor integrated circuit; and a plurality of second circuits electrically connected to the semiconductor integrated circuit or the test circuit and used for inspecting characteristics of the semiconductor integrated circuit. A circuit region having one pad electrode and a plurality of second pad electrodes that are electrically connected to the semiconductor integrated circuit and are not used when testing the characteristics of the semiconductor integrated circuit;
Test elements for performing an evaluation relating to the manufacture of the semiconductor integrated circuit, and electrically connected to the test elements and arranged in a row extending in one direction, each facing the second pad electrode And a TEG provided with a plurality of third pad electrodes arranged so as not to face the first pad electrode and provided in a scribe area adjacent to the circuit region. A preparation process;
A semiconductor device manufacturing method, comprising: an inspection step of inspecting the semiconductor integrated circuit and measuring the TEG by bringing a probe needle into contact with the first pad electrode and the third pad electrode on the substrate. Method.   12. The method of manufacturing a semiconductor device according to claim 11, wherein the inspection of the semiconductor integrated circuit includes an inspection performed by driving the test circuit.   13. The method of manufacturing a semiconductor device according to claim 11, wherein the test circuit includes a BIST circuit, and the first pad electrode includes a pad electrode for driving the BIST circuit.   The method of manufacturing a semiconductor device according to claim 7, wherein the inspection of the semiconductor integrated circuit and the measurement of the TEG are performed simultaneously.

Images