JPS59184566A - Insulated gate type field effect transistor - Google Patents
Insulated gate type field effect transistorInfo
- Publication number
- JPS59184566A JPS59184566A JP5886483A JP5886483A JPS59184566A JP S59184566 A JPS59184566 A JP S59184566A JP 5886483 A JP5886483 A JP 5886483A JP 5886483 A JP5886483 A JP 5886483A JP S59184566 A JPS59184566 A JP S59184566A
- Authority
- JP
- Japan
- Prior art keywords
- under
- gate
- oxide film
- film
- thin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005669 field effect Effects 0.000 title claims description 4
- 239000010408 film Substances 0.000 claims abstract description 44
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 239000010409 thin film Substances 0.000 claims abstract description 6
- 239000004065 semiconductor Substances 0.000 claims description 6
- 238000000034 method Methods 0.000 abstract description 5
- 239000000969 carrier Substances 0.000 abstract description 2
- 238000009413 insulation Methods 0.000 abstract 4
- 239000010410 layer Substances 0.000 description 14
- 230000015556 catabolic process Effects 0.000 description 8
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 4
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 241000238631 Hexapoda Species 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000005422 blasting Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、特に絶縁ゲート型電界効果トランジスタ（以
下、ＩＧＦＥＴという）の高耐圧化ＶＣ関わるものであ
る。DETAILED DESCRIPTION OF THE INVENTION The present invention particularly relates to a high breakdown voltage VC of an insulated gate field effect transistor (hereinafter referred to as IGFET).
一般に、ＩＧＦＥＴのドレイン耐圧は、ゲート下のドレ
イン端における電界集中によるアバランシュ破壊で決ま
る。このため、ドレイン耐圧を向上するにｌ−１：、Ｉ
ＧＦＥＴ のドレイン側のゲート絶縁膜厚をソース側
に比べ厚くする方法がとられる。Generally, the drain breakdown voltage of an IGFET is determined by avalanche breakdown due to electric field concentration at the drain end under the gate. Therefore, in order to improve the drain breakdown voltage, l-1:, I
A method is used in which the thickness of the gate insulating film on the drain side of the GFET is made thicker than on the source side.
この方法による高耐圧ＭＯ８ＦＥＴの構造を第１図に示
す。第１図において、１は例えばＮ型シリコン基板であ
り、基板１ｖｃＦｉソース領域２およびドレイン領域３
が形成されている。ソース、ドレイン間の基板上ＶＣは
ゲート絶縁膜としてのシリコン酸化膜２０が形成されて
いる。酸化膜２０の厚さは一様でなく、ソース側の薄い
部分４とドレイン側の厚い部分５とでなる。酸化膜２０
上には多結晶半導体層１１が設けられている。ゲート部
分以外は厚いフィールド酸化膜６が形成されている。The structure of a high voltage MO8FET produced by this method is shown in FIG. In FIG. 1, 1 is an N-type silicon substrate, for example, and the substrate 1vcFi source region 2 and drain region 3
is formed. A silicon oxide film 20 as a gate insulating film is formed on the substrate VC between the source and drain. The thickness of the oxide film 20 is not uniform, and consists of a thin portion 4 on the source side and a thick portion 5 on the drain side. Oxide film 20
A polycrystalline semiconductor layer 11 is provided thereon. A thick field oxide film 6 is formed in areas other than the gate portion.
例えばアルミニウム等の金属でなるドレイン電極８、ゲ
ート電極９およびソース電極１０が全面をおおう絶縁膜
７Ｖｃ開孔を設けて形成されている。A drain electrode 8, a gate electrode 9, and a source electrode 10 made of metal such as aluminum, for example, are formed by providing an opening in an insulating film 7Vc covering the entire surface.
このような構造にすることにより、ゲートとドレイン間
の電界が緩和されてゲート下のドレイン端のアバランシ
ュ破壊電圧は大きくな９．ＩＧＦＥＴの耐圧は向上する
。By adopting such a structure, the electric field between the gate and the drain is relaxed, and the avalanche breakdown voltage at the drain end under the gate is increased.9. The withstand voltage of the IGFET is improved.
しかしながら、この構造をとるとゲート酸化膜２０の膜
厚が薄い領域４と厚い領域５とで、ＩＧＦＢＴのしきい
値ＶＴが異なり、ゲート酸化膜厚が厚い部分５でのＶＴ
が高くなる。このため、印加ゲート電圧に対し、十分な
大きさの相互コンダクタンスを確保することができない
欠点がある。However, when this structure is adopted, the threshold voltage VT of the IGFBT is different between the thin region 4 and the thick region 5 of the gate oxide film 20, and the VT in the thick gate oxide film 20 is different.
becomes higher. Therefore, there is a drawback that a sufficiently large mutual conductance cannot be ensured with respect to the applied gate voltage.
不発明の目的は、相互コンダクタンスｇｍが向上された
高耐圧の１ＧＦＥＴ 全提供することにある。An object of the invention is to provide a high voltage 1GFET with improved mutual conductance gm.
不発明は、ドレイン側のゲート絶縁膜厚がソース側のそ
れよＶも厚いＩＧＦＥＴであって、厚い方のゲート絶縁
膜下ＶＣおけるチャンネル領域の多数キャリア濃度が薄
い方のゲート絶縁膜下におけるそれよりも低いことを特
徴とする。The non-invention is an IGFET in which the gate insulating film on the drain side is thicker than that on the source side, and the majority carrier concentration in the channel region of VC under the thicker gate insulating film is lower than that under the thinner gate insulating film. It is characterized by being lower than
以下、図面により不発明の詳細な説明する。Hereinafter, the invention will be explained in detail with reference to the drawings.
第２図は不発明の一実施例全示し、第１図と同−機能部
は同一番号で示してその説明を省略する。FIG. 2 shows an entire embodiment of the present invention, and the same functional parts as in FIG. 1 are designated by the same numbers and their explanations will be omitted.
第２図で示されたＩＧＦＥＴは、高耐圧化全得るために
ゲート絶縁膜２０がソース側の薄い部分４とドレイン側
の厚い部分５とでなす、シかも、相互コンダクタンスを
向上させるために、薄い膜厚部分４下の基板表面部分１
２と厚い膜厚部分５下の基板表面部分１３との多数キャ
リアが異なり、前者の方が後者よりも高い多数キャリア
濃度を有する。薄い膜厚部分４上ＶＣは耐熱性であって
耐酸化性の導体層１４が形成され、厚い膜厚部分５上に
は多結晶層１５が形成され、これらはゲート電極９に接
続されている。導体層１４および多結晶層１５は、この
ＩＧＦＥＴ 全製造する際に用いたもので、これＶＣつ
いては後述する。このような構造をもつＩＧＦＢＴは、
従来の第１図のＩＧＦＥＴと比較すると、ドレイン側の
厚いゲー）［化膜領域５下では基板表面部分１３の多数
キャリアの濃度が低いことからこの領域のしきい値電圧
ＶＴ ｋ薄いゲート酸化膜４におけるしきい値電圧と等
しくすることができる。このことによｆｉ、１ＧＦＥＴ
の特性パラメータの１つであるｇｍが劣化しない。また
、耐圧は階段状のゲート絶縁膜を有するＭＯＳＦＥＴと
等しい。In the IGFET shown in FIG. 2, the gate insulating film 20 has a thin part 4 on the source side and a thick part 5 on the drain side in order to obtain a high breakdown voltage. Substrate surface portion 1 under thin film thickness portion 4
2 and the substrate surface portion 13 under the thick film thickness portion 5 have different majority carriers, and the former has a higher majority carrier concentration than the latter. A heat-resistant and oxidation-resistant conductor layer 14 is formed on the thin film thickness portion 4 of the VC, and a polycrystalline layer 15 is formed on the thick film thickness portion 5, which are connected to the gate electrode 9. . The conductor layer 14 and the polycrystalline layer 15 were used in the entire manufacture of this IGFET, and the VC will be described later. IGFBT with such a structure is
Compared to the conventional IGFET shown in FIG. 4 can be made equal to the threshold voltage at 4. Due to this, 1GFET
gm, one of the characteristic parameters, does not deteriorate. Further, the breakdown voltage is equal to that of a MOSFET having a stepped gate insulating film.
第３図は、ゲート絶縁膜の膜厚に応じて基板表面部の多
数キャリア濃度が異なる第２図で示したＩＧＦＥＴの製
造全示す一実施例である・ます、第３図（ａ）に示すよ
うに、厚いフィールド酸化膜６が形成された半導体基板
１０表面に熱酸化膜４ｖｉ−形成する。この熱酸化膜と
第２図で示した薄い膜厚部分との参照数字が同じである
ことから明らかなように、熱噴化膜４は薄い膜厚部分と
なる。次ＶＣＰ ｉの不純物（ｆｃとえば、ボロン）を
基板１の導電型が反転しないドース量（ユ１０１１ｃｍ
−２）でイオン注入する。次に、耐熱性であって耐酸化
性の金属１４（たとえば白金）全蒸着し、リソグラフィ
ーＶＣよりパターンニングする（第３図（ｂ））。これ
によって、薄い膜厚部分上の導体層が形成される０次Ｖ
Ｃ，金属１２をマスクｖｃＰ型の不純物（たとえばボロ
ン）全基板１の導電型が反転しないドーズ量（−１０１
１（Ｈｌ−２）でさらにイオン注入する。これによって
、基板１には表面部分１２よシも多数キャリア濃度が低
い表面部分１３が形成される。さらＶこ、金属１４をマ
スクＶＣ選択酸化した後、ドレイン側の厚いゲート酸化
膜５上に金属１４が一部かさなる多結晶シリコン層１５
を選択的に形成する（第３図（Ｃ））。次に、金属１４
５ −
と多結晶シリコン１５をマスクに酸化膜のエツチング全
行ない、基板１の一部全露出させてソース。Figure 3 is an example of manufacturing the IGFET shown in Figure 2, in which the majority carrier concentration on the substrate surface varies depending on the thickness of the gate insulating film, as shown in Figure 3(a). A thermal oxide film 4vi- is formed on the surface of the semiconductor substrate 10 on which the thick field oxide film 6 is formed. As is clear from the fact that the reference numerals of this thermal oxide film and the thin film thickness portion shown in FIG. 2 are the same, the thermal blasting film 4 is a thin film thickness portion. Next, add an impurity (fc, boron, for example) to VCP i at a dose that does not invert the conductivity type of substrate 1 (yu 1011cm).
-2) perform ion implantation. Next, a heat-resistant and oxidation-resistant metal 14 (for example, platinum) is completely deposited and patterned by lithography VC (FIG. 3(b)). This results in the formation of a zero-order V
C, the metal 12 is masked with a vcP type impurity (for example, boron) at a dose (-101
Further ion implantation is performed at 1 (Hl-2). As a result, a surface portion 13 having a lower majority carrier concentration than the surface portion 12 is formed on the substrate 1. Further, after selectively oxidizing the metal 14 using a mask, a polycrystalline silicon layer 15 is formed on the thick gate oxide film 5 on the drain side, with the metal 14 partially covering the thick gate oxide film 5.
is selectively formed (FIG. 3(C)). Next, metal 14
5- and polycrystalline silicon 15 as a mask, the entire oxide film is etched to completely expose a part of the substrate 1, and a source is formed.
ドレイン拡散層２．３を形成する（第３図（ｄ））。A drain diffusion layer 2.3 is formed (FIG. 3(d)).
その彼、第２図で示すように層間絶縁膜としてＰＥＧ膜
７を形成し、コンタクト穴をホトレジスト工程で開孔し
てＡＡによるドレイン、ゲートおよびソース電極８，９
．１０を形成する・
このようＶＣ１厚いゲート酸化膜５下のチャネル領域に
薄いゲート酸化膜４下のチャネル領域より基板１とは逆
導電型の不純物を高濃度にイオン注入を行なうことによ
り、厚いゲート酸化膜５下の反転層形成が低電圧で容易
になる。従って、第３図（ａ）、 （ｂ）で示した２回
のイオン注入のドーズ量全制御すれば、ゲートのソース
側、ドレイン側でのしきい値ｖＴは同程度となり、階段
構造のＭＯ８Ｆ’ＥＴの相互コンダクタンスｇｍが劣化
することはない・第４図は、本発明の他の実施例を示す
ものである。この実施例では、ドレインの高濃度層３の
周囲にこれと同一導電型の低濃度層１６が設けである。As shown in FIG. 2, he formed a PEG film 7 as an interlayer insulating film, opened contact holes using a photoresist process, and formed drain, gate, and source electrodes 8 and 9 using AA.
．． By ion-implanting impurities of a conductivity type opposite to that of the substrate 1 into the channel region under the thick gate oxide film 5 of VC1 at a higher concentration than the channel region under the thin gate oxide film 4, a thick gate is formed. Formation of the inversion layer under the oxide film 5 is facilitated at low voltage. Therefore, if the dose of the two ion implantations shown in FIGS. 3(a) and 3(b) is fully controlled, the threshold value vT on the source side and drain side of the gate will be approximately the same, and the MO8F of the stepped structure 'The transconductance gm of ET is not degraded. Figure 4 shows another embodiment of the present invention. In this embodiment, a low concentration layer 16 of the same conductivity type is provided around the high concentration layer 3 of the drain.
よって、第２図で示した実施例ＶＣ比較して相 ６−
互コンダクタンスｇｍは低下するが、ドレイン耐圧はさ
らＶＣ高くすることが出来る。Therefore, although the mutual conductance gm is lower than that of the example VC shown in FIG. 2, the drain breakdown voltage can be further increased.
なお、不発明はＰチャンネル型のものについて説明した
が、Ｎチャンネル型にも適用できる。また、その製法は
第３図に限定されない。Although the invention has been described for a P-channel type, it can also be applied to an N-channel type. Further, the manufacturing method is not limited to that shown in FIG.
第１図は従来法の階段状ゲート構造含有する高耐圧ＭＯ
８ＦＥＴの構造を示す断面図、第２図は本発明の一実旅
例を示す高耐圧ＭＯ８ＦＥＴの構造断面図、第３図（ａ
）〜（ｄ）は不発明による高耐圧ＭＯ８−ＦＥＴ の
製造方法の一例を示す工程断面図、第４図は本発明の他
の実施例含水す断面図である。
図中、１・・・・・・Ｎ型シリコン基板、２・・・・・
・ソース拡散層、３・・・・・・ドレイン拡散層、４・
・・・・・薄いゲートば化膜、訃・・・・・厚いゲート
酸化膜、６・・・・・・フィールド改化膜、７・・・・
・層間絶縁膜、８・・・・・・ドレイン電極、９・・・
・・・ゲート電極、１０・・・・・ソース電極、１１．
１５・・・・・多結晶シリコン層、１２・・・・・・薄
いゲート酸化膜下の半導体基板表面の多数キャリア濃度
の多い領域、１３・・・・・・厚いゲート酸化膜下の半
導体基板表面の多数キャリア濃度の少ない領域、１４・
・・・・白金、１６・・・・・・ドレイン低濃度層。
第 １ 区
１ １虫 Ｉ ＆
第４区Figure 1 shows a conventional high-voltage MO containing a stepped gate structure.
FIG. 2 is a cross-sectional view showing the structure of an MO8FET, and FIG.
) to (d) are process cross-sectional views showing an example of a manufacturing method of a high voltage MO8-FET according to the invention, and FIG. 4 is a cross-sectional view of another embodiment of the present invention in a water-containing state. In the figure, 1... N-type silicon substrate, 2...
・Source diffusion layer, 3...Drain diffusion layer, 4.
... Thin gate oxide film, Thick gate oxide film, 6... Field modification film, 7...
・Interlayer insulating film, 8...Drain electrode, 9...
. . . Gate electrode, 10 . . . Source electrode, 11.
15...Polycrystalline silicon layer, 12...Region with high majority carrier concentration on the surface of the semiconductor substrate under the thin gate oxide film, 13...Semiconductor substrate under the thick gate oxide film Region with low majority carrier concentration on the surface, 14.
...Platinum, 16... Drain low concentration layer. 1st Ward 1 1 Insect I & 4th Ward
Claims (1)
分とでなる絶縁ゲート型電界効果トランジスタＶＣおい
て、前記第１部分下の半導体基板表面部の多数キャリア
良度が前記第２部分下の半導体基板表面部のそれよりも
高いこと全特徴とする絶線ゲート型電界効果トランジス
タ。In an insulated gate field effect transistor VC in which the gate insulating film has a first portion with a thin film thickness and a second portion with a thick film thickness, the majority carrier quality of the semiconductor substrate surface portion under the first portion is An isolated gate field effect transistor characterized in that its height is higher than that of the surface of a semiconductor substrate below.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5886483A JPS59184566A (en) | 1983-04-04 | 1983-04-04 | Insulated gate type field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5886483A JPS59184566A (en) | 1983-04-04 | 1983-04-04 | Insulated gate type field effect transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59184566A true JPS59184566A (en) | 1984-10-19 |
Family
ID=13096584
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5886483A Pending JPS59184566A (en) | 1983-04-04 | 1983-04-04 | Insulated gate type field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59184566A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04214672A (en) * | 1990-12-12 | 1992-08-05 | Sharp Corp | Semiconductor device and manufacture thereof |
-
1983
- 1983-04-04 JP JP5886483A patent/JPS59184566A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04214672A (en) * | 1990-12-12 | 1992-08-05 | Sharp Corp | Semiconductor device and manufacture thereof |
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