JPS59184544A - Device for inspecting integrated circuit - Google Patents

Abstract

PURPOSE:To enable to largely shorten the working of evaluation in research and development by a method wherein the titled device is so constructed as to automatically point out a test object circuit DUT with the possibility of the existence of considerably many non-defective parts even when the DUT is defective. CONSTITUTION:The group 1 of drivers supplies a discriminating sign to discriminate the DUT, a series of testing patterns, and the expected values thereof. A testing pattern driver 5 receives the testing pattern through the group 3 of signal lines and impresses it via group 6 of signal lines to the input terminals of the DUT. The group 8 of receivers receives the group 7 of response signals and then judges whether the signal level is over the fixed value or not. A judging circuit 10 judges agreement/disagreement by inputting the judged result 9 and the expected value signal 4 from the group 1 of drivers 1. A disagreement analyzing circuit 12 inputs a signal 11 for reporting the number of disagreement output terminals and thus analyzes the result of disagreement. A code holding circuit 14 inputs the DUT discriminating coded signal line 2 in said group 1 and the control signal 13 from said circuit 12 and then holds the DUT discriminating code. A disagreement bit accumulated holding circuit 20 accumulates the bit information corresponding to each output terminal.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a testing device for a logic circuit configured as a semiconductor integrated circuit.

Background> In the past, this type of inspection equipment was designed with the primary purpose of use in a mass production environment, and inspection functions for research and development were not taken into account. . One of the differences between the mass production environment and the R&D environment is the failure analysis function. That is, during testing, emphasis is placed on determining whether the integrated circuit under test is good or bad, while during research and development, it is important to investigate the cause of the failure. For example, in the case of integrated circuits in which many identical chips are manufactured on one wafer, during mass production, only normal chips are selected by inspection equipment on the wafer, and 0 normal chips are selected. All you have to do is send it to the post-process (cutting, assembly). However, during research and development, it is not uncommon for all chips on Ueno 1 to have some sort of defect. In this case, it is impossible to investigate the cause of the defect while the chip is still in its raw state due to the strength of the chip, so we select a chip that contains as many normally operating partial circuits as possible, send it to the subsequent process, and assemble it. It is necessary to analyze the cause of the failure under the condition in which the For this purpose, it is necessary to efficiently select chips as candidates for failure analysis on the wafer in as short a time as possible. However, conventional inspection equipment does not have an effective function that can deal with such problems in a short time, and has the disadvantage that it requires a great deal of time and experience to select chips that are candidates for failure analysis.

<Object of the Invention> The object of the present invention is to eliminate the above drawbacks by enabling an inspection device to automatically display candidate chips for failure analysis based on the inspection results, and to efficiently perform failure analysis. The purpose of the present invention is to provide an inspection device that can perform the following tasks.

<Summary of the Invention> According to the inspection device of the present invention, in order to achieve the above-mentioned object, means for supplying an identification code for identifying a circuit to be tested, a series of test stamps and their expected values, and the above-mentioned A means for applying the above test voltage to the input terminal of the circuit under test, a means for determining the response of the output terminal of the circuit under test, and a comparison result of the response judgment with the above expected value. Connect the output terminal of the circuit under test that caused the mismatch to
A means for storing results related to a series of test patterns, a means for storing results stored in relation to the series of test patterns, and a saving means for saving the stored and retained contents. a means for comparing the saved contents with the accumulated and held contents to determine the magnitude relationship of the number of mismatched output terminal types; a holding means for holding the above identification code; means for determining the magnitude relationship between the content and the stored content as the content to be saved by the saving means; and means for causing the holding means to hold the identification code at this time; If it is an identification code, it also includes means for displaying the saved contents.

<Example> composition Next, the present invention will be explained in detail with reference to the drawings.

In FIG. 1 showing an embodiment of the present invention, the inspection apparatus of the present invention includes an identification code for identifying a circuit under test (DUT), a driver group 1 for supplying a series of test buttons and their expected values. , a test button driver 5 receives a series of test patterns from the driver group 1 through the signal line group 3, and applies them to the input terminal of the DUT via the signal line group 6.
, a receiver group 8 which receives the response signal group 7 at the output terminal of the DUT and determines whether the signal level is above a predetermined value, a determination result 9 of the response of the DUT in the receiver group 8, and a driver group. A determination circuit 10 that inputs the expected value signal 4 of 1 and 2 to determine whether it is a match/mismatch, and a mismatch circuit that inputs the mismatch report signal group 11 of the output of the match/mismatch determination circuit 10 and analyzes the mismatch result. The analysis circuit 12 and D in the driver group l
A DU which inputs the UT identification code signal line 2 and the control signal 13 from the mismatch analysis circuit 12 and holds the DUT identification code.
It is comprised of a T identification code holding circuit 14 and a display device 16 that displays the discrepancy analysis result 15 from the discrepancy analysis circuit 12 and the DUT identification code.

Operation When testing each chip on an integrated circuit wafer using the testing apparatus configured as described above, the testing method and the operation of the apparatus are as follows.

First, before starting the inspection, initialize the inspection device and
initialization) is performed. At this time, of the two types of counters existing in the discrepancy analysis circuit 12, the minimum discrepancy counter as a saving means is set to the maximum value, and the other working counter as a discrepancy output terminal accumulation holding means is set to O. I'll keep it.

Next, for the first chip on the wafer, a series of test chips from driver group 1 are sent to test chip driver 5. A series of responses from the DUT are collected into a receiver group 8 and become an input signal 9 on one side to a match/mismatch determination circuit]0.

The response of the DUT is compared with the signal group 4 of the driver groups 1 to p that supply expected values in a match/mismatch determination circuit 10, and if they do not match, a mismatch report signal group 11 is generated.

The configuration of the match/mismatch determination circuit 10 is, for example, as shown in FIG. The expected value signal 4 and the DUT response signal 9 whose level has been determined are input to a bit-by-bit comparison circuit 18 for each output terminal, and the comparison results are sent onto the corresponding output lines 19, respectively. The mismatch bit accumulation/holding circuit 20 that receives the comparison result has bit information indicating mismatch or match corresponding to each output terminal of the DUT, and even if a mismatch occurs even once during the application of a series of test patterns. The bit corresponding to the output terminal where the mismatch occurred is set to ], and the bit corresponding to the output terminal where the mismatch occurred more than once is set to 0. The contents of the mismatch pit accumulation/holding circuit 20 after a series of tests and/or pulses are sent to the mismatch report signal line group 11.

In the discrepancy analysis circuit 12 (FIG. 1) which receives the signals from the discrepancy report line group 11, the number of 1's in the discrepancy report line group 11 is counted by the working counter.

At the time when a series of tests and the application of the voltage are completed, the working counter holds the number of types of mismatch (error) output terminals that occurred during the test with respect to a specific chip on the wafer. Therefore, the contents of the minimum mismatch count counter and the contents of the working counter at that point are compared, and if the conditions (content of the minimum mismatch count counter) > (contents of the working counter) are satisfied, the minimum mismatch count counter is The contents are rewritten with the contents of the working counter, the number of types of output terminals are saved, and at the same time, the DU is sent to the DUT identification code holding circuit 14.
The control signal 13 is sent to the mismatch analysis circuit 1 so as to write the T identification code signal 2 (in this case, the Ueno chip number).
Generate in 2. When the testing of a specific chip on the wafer using a series of test patterns is completed in this way, the working counter in the discrepancy analysis circuit 12 is set to 0, and the next chip on the wafer is tested using the same procedure. executed.

When all chips on the wafer have been inspected, the DU
By displaying the contents of the T identification code holding circuit 14 and the contents of the minimum mismatch count counter on the display device 16, the chip with the smallest number of mismatch (error) output terminal types among the chips on the wafer is automatically selected. In many cases, it is no longer necessary to investigate and analyze test results as in the past.
This results in the effect that research and development work can be significantly shortened.

The configuration of the mismatch analysis circuit 12 is as shown in FIG. 3, for example. That is, the working counter 21 has its addition operation controlled by the discrepancy report signal 11, and the contents of this counter 21 are outputted as a signal 22'. The contents of the minimum mismatch count counter 23 are output to the signal line 24 and compared with the contents of the working counter 21 by the comparator circuit 25. If the contents of the working counter 21 are small, write control to the DUT identification code holding circuit is performed. A signal 13 and a write signal 26 to the minimum mismatch counter 23 are generated. When the minimum mismatch count counter 23 receives the write signal 26, the working counter 2
It is rewritten with the contents 22 of 1.

Effect> As explained above, the present invention allows the inspection device to be used even when the DUT is defective, even when the DUT is defective.
By configuring it to automatically point out T,
This has the effect of significantly shortening evaluation work during research and development.

[Brief explanation of drawings]

FIG. 1 is an overall block diagram showing an embodiment of the invention, FIG. 2 is a circuit diagram showing an embodiment of the match/mismatch determination circuit 10 shown in FIG. 1, and FIG. 3 is a circuit diagram showing an embodiment of the match/mismatch determination circuit 10 shown in FIG. FIG. 2 is a circuit diagram showing an example of a mismatch analysis circuit 12. FIG. 1...DUT identification code, test button, expected value driver group, 2...DUT identification code signal, 3...test/button signal, 4...expected value signal, 5...DUT input Terminal driver, 6... Test bang signal, 7... DUT
Output terminal response signal, 8...DUT response determination circuit, 9.
...DUT response judgment signal, lO... Match/mismatch judgment circuit, 11... Mismatch report signal line group, 12... Mismatch analysis circuit, 13... DUT identification code write signal,
14... DUT identification code holding circuit, 15... Minimum mismatch count signal, 16... Display device. Patent applicant Takashi Kusano (11), agent of NEC Corporation

Claims (1)

[Claims] (1) Means for supplying an identification code for identifying the circuit under test, a series of test/master buttons, and their expected values; means for applying the test pattern to the input terminal of the circuit under test; and the test A means for determining the response of the output terminal of the circuit under test, a means for comparing the above expected value with the determination result of the above response, and detecting the output terminal of the circuit under test that has caused a discrepancy in the comparison result.
A means for accumulating results related to a series of test patterns; a means for retaining results accumulated in relation to the series of test patterns; a saving means for saving the accumulated and retained contents; means for comparing the saved contents with the accumulated and held contents to determine the magnitude relationship of the number of mismatched output terminal types; a holding means for holding the above identification code; and a means for comparing the saved contents and the accumulated held contents. means for making one of the determination results of the size relationship the stored and held contents as the contents to be saved in the saving means and the holding means to hold the identification code at that time; and the identification code of the holding means and the saving means. A means for displaying the saved contents of the means, and a better integrated circuit testing device.