JP3808575B2 - Yield analysis method and apparatus - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a yield analysis method and apparatus, and more particularly to a method and apparatus suitable for analyzing yield and defects of semiconductor products.
[0002]
[Prior art]
In the mass production process of semiconductor products, a system that statistically processes the test results to determine pass / fail and displays the distribution of the number of defective products detected for each test item is built into the factory line In practical use.
[0003]
Among semiconductor products, for example, semiconductor memory devices, for example, occupy most of the regions where the same circuits constituting the cells are regularly arranged. Such an apparatus is relatively easy to obtain a physical address of a defective part found by a test, display the defective part on a map, and perform a yield analysis to find out the cause of the defect.
[0004]
On the other hand, logic circuit products such as CPUs, microcomputers, and ASICs (Application Specific ICs) do not have a configuration in which the same circuits are regularly arranged, and it is difficult to identify defective portions. For such products, by using a failure dictionary obtained from failure simulation, which will be described later, and an address indicating a defective pattern position obtained from a function test, an external output terminal, and the like, the failure candidate nodes inside the circuit are narrowed down. The following methods are used.
[0005]
[Problems to be solved by the invention]
In recent years, as the scale of products has increased, and the miniaturization in manufacturing processes and the complexity of circuit configurations have progressed, the demand for improving the yield of products has been increasing. However, the amount of information for analyzing the yield from the test results of the product is not sufficient, and the yield analysis for identifying the defective part has been difficult. Tests in the conventional production line are mainly characteristic tests using a tester that discriminates between non-defective products and defective products. In order to analyze the yield by processing and analyzing the test results, a new separate line should be provided. Alternatively, the production line must be stopped and analyzed. In addition, the analysis method is not automated, and there are many aspects that must be relied on by manual work by skilled workers, requiring a great deal of time and labor.
[0006]
In addition, unlike the storage device in which the same circuit configuration is regularly arranged as described above, the logic circuit product has no regularity in the circuit configuration, so that the result of the non-defective product discrimination test in the conventional production line is used. It was difficult to identify the defective part.
[0007]
The present invention has been made in view of the above circumstances, and can provide useful information for performing a yield analysis to narrow down the position of a defective candidate node on a chip or a wafer and determine the cause of the defect. It is an object of the present invention to provide a yield analysis method and apparatus.
[0008]
[Means for Solving the Problems]
The yield analysis apparatus of the present invention is
A measurement means for outputting a measurement result obtained by performing a measurement for determining pass / fail for a plurality of chips or wafers;
A simulation execution unit that performs a failure simulation on the chip or the wafer and creates a failure dictionary indicating failure candidate nodes;
A layout information generator for generating and outputting layout information including a layout diagram showing a layout of each element in the chip or wafer;
Dust detection means for detecting dust present on the chip or wafer and outputting dust information indicating a position where the dust is distributed on the surface of the chip or wafer;
Collating the measurement result output by the measurement unit with the failure dictionary created by the simulation execution unit, narrowing down good product candidate nodes and failure candidate nodes, the layout information output by the layout information generation unit, A fail map for displaying the non-defective product candidate node and the defective candidate node on the layout diagram in association with the narrowed non-defective product candidate node and the defective candidate node is created, and the non-defective product candidate node and the defective candidate are created. A controller that superimposes the position of the node and the position of the dust to analyze the cause of the failure of the failure candidate node;
And a display unit for displaying the fail map.
[0009]
In addition to the failure simulation, the simulation execution unit includes a logic simulation for determining the quality of the logic description of the circuit pattern, a function simulation for determining the quality of the functional description of each cell, and a circuit simulation for determining the quality of the circuit operation. And output the simulation results for each.
The control unit collates the simulation result output from the simulation execution unit and the measurement result output from the measurement unit to narrow down the non-defective product candidate node and the defective candidate node, and narrows down the layout information and the narrowed down A non-defective product candidate node and a defective candidate node may be associated with each other to create a fail map for displaying the non-defective product candidate node and the defective candidate node on the layout diagram.
[0010]
The control unit determines that the influence of dust is high at a position where the position of the defect candidate node and the position of the dust coincide with each other, and excluding the influence of the dust, a predetermined number or more in the plurality of chips or wafers If the defect candidate node group exists in common, it is determined that there is a high possibility that there is an abnormality in the manufacturing process at that location, and a warning is displayed on the display unit based on the determination result. May be.
[0011]
The yield analysis method of the present invention is:
Performing measurement for determining the quality of a plurality of chips or wafers using a measurement means, and generating a measurement result;
Performing a simulation for determining the presence or absence of a failure of the chip or wafer, and generating a failure dictionary indicating a node in which the failure is detected;
Collating the measurement result with the fault dictionary and narrowing down non-defective candidate nodes and defective candidate nodes;
The non-defective product candidate node and the defective candidate node are superimposed on the layout diagram by associating layout information including a layout diagram showing a layout of each element on the chip or the wafer with the good product candidate node and the defective candidate node. Creating a fail map for display;
Detecting the position of dust present on the chip or wafer;
Superimposing the position of the good candidate node and the defect candidate node and the position of the dust to analyze the cause of the defect of the defect candidate node;
Displaying the fail map on a display means;
It is characterized by providing.
[0012]
In the step of analyzing the cause of the failure of the failure candidate node, it is determined that the influence of dust is high at a location where the position of the failure candidate node and the position of the dust match, In the case where the defect candidate node group exists in common in a predetermined number or more of the chips or wafers, it is determined that there is a high possibility that there is an abnormality in the manufacturing process at that location,
A step of displaying a warning by the display means based on the determination result may be further provided.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
In the yield analysis method and the apparatus according to an embodiment of the present invention, the failure candidate nodes are squeezed out using information obtained by simulation such as failure simulation as information obtained by performing the measurement test. From the node and layout information, the area of the physical failure candidate node on the chip or wafer is determined. Further, the cause of the failure is analyzed by superimposing the physical failure candidate node region and the dust distribution indicated in the dust information. Further, the defect candidate node area obtained in this way is obtained for each of a plurality of chips or wafers and statistically processed, and a defect common to many chips or wafers is analyzed. If necessary, each information is accumulated, and monitoring is performed in the factory line to detect an abnormality. Further, when a defect is detected in a predetermined number of chips or wafers, a warning is issued.
[0014]
Here, the test information is the result of collecting the results of measuring the characteristics using a tester or the like to determine the quality of the extracted lot or sample at the time of manufacture or evaluation of the semiconductor product, and performing statistical processing. It is what I did.
[0015]
The logic simulation information is obtained by performing computer simulation as to whether or not the circuit pattern correctly describes the logic shown in the circuit diagram. The logic simulation is the same as the activation simulation for examining the change in the level of a node in which other nodes are activated to 1 or 0 when test data is input to a certain node.
[0016]
In the failure simulation, the circuit pattern is logically and functionally correct, but indicates a failure found as a result of the simulation performed by verifying the test information. By this failure simulation, a failure dictionary indicating failure candidate nodes is created.
[0017]
The layout information indicates the physical position of each device on the wafer or chip. However, the yield analysis does not require information showing up to a detailed pattern, and it is sufficient if the location where each device exists is schematically shown using a block or the like.
[0018]
The dust information is obtained by detecting the position of dust present on the chip or wafer. Dust is an accidental failure. The object of analysis in the present invention is a case where there is a cause of a defect in the manufacturing process and a defect occurs in a common area of a plurality of chips or wafers. Therefore, defects caused by dust are excluded from the target of yield analysis.
[0019]
Hereinafter, an embodiment of the present invention will be described. First, an outline of the yield analysis method according to this embodiment will be described. FIG. 3 shows a chip 31 to be tested and test data 32. The chip 31 is divided into physical areas a, b, c, and d, and the test data 32 is divided into A, B, C, and D according to test items.
[0020]
As indicated by the arrows, the test data A covers the region a of the chip 31, the test data B covers the region b, the test data C covers the region c, and the test data D covers the region d.
[0021]
Using such test data A to D, the areas a, b, c, and d to be tested are tested and a fault simulation is executed, thereby generating a fault dictionary indicating defective candidate nodes. By using this failure dictionary and layout information indicating the layout of each node, the physical position of the failure node on the chip 31 as shown in FIGS. As shown in FIG. 4A, it is assumed that a failure simulation is performed using the test data A, and a failure candidate node group in which a failure is detected exists in the hatched regions 41 and 42. In the failure simulation using the test data B, there are defective candidate node groups in the areas 43 and 44 as shown in FIG. It is assumed that a failure candidate node group exists in the regions 45 and 46 shown in FIG. 4C by the failure simulation using the test data C. Further, it is assumed that a failure candidate node group exists in the areas 47 and 48 shown in FIG. 4D by the failure simulation using the test data D.
[0022]
Then, it is assumed that the test result is expressed as shown in FIG. In the test using the test data A and B, both pass as good products, and the areas 41 to 44 in FIGS. 4A and 4B are good product candidate node groups. Since the test using the test data C has failed, the areas 45 and 46 shown in FIG. 4C are defective candidate node groups.
[0023]
In this test, it is assumed that once a defect is found, the test is performed in a mode in which subsequent tests are not performed. As a result, the test using the test data D has not been performed, and the area shown in FIG. As described above, after superimposing the defective candidate node group areas shown in FIGS. 4A to 4D, the non-defective candidate node group is based on the pass or fail of FIG. 5 and the test result of execution or non-execution. When the region is excluded, the result as shown in FIG. 6 is obtained. That is, the physical areas 51 and 53 of the chip 31 have good candidate node groups, and the area 52 has defective candidate node groups.
[0024]
Thereafter, based on the dust detection result of the dust checker 15, it is possible to determine whether or not the cause of the defect in the area 52 is due to dust by superimposing a physical area where a defect candidate node group due to dust exists. it can.
[0025]
By performing the above operations on a plurality of chips and performing statistical processing on the obtained results, it is possible to determine whether a physical area where a defective candidate node group exists commonly appears on many chips. It is possible to judge and grasp the tendency of defective products. Similar to the case where the above processing is performed on a chip basis, it can also be performed on a wafer to determine in which physical region on the wafer the defective node candidate group exists.
[0026]
FIG. 1 shows the configuration of a yield analysis apparatus according to this embodiment. The measuring device 11 is for measuring the characteristics of a product, and for example, a tester such as ATE (APPROVAL TEST EQUIPMENT) is used. The measurement data collection unit 12 collects measurement data output from the measurement device 11. The measurement data collection unit 12 may perform statistical processing on the collected data. The simulation execution unit 14 executes, for example, the above-described failure simulation, logic simulation, activation simulation, and the like. Other simulations include functional simulations that examine the functional description of each block or cell unit, circuit simulations that examine the operation of circuits down to the transistor level, and mixed simulations that combine logic and functional simulations. May be.
[0027]
The layout information generation unit 18 reads not only the information indicating the position of the chip with respect to the node in the circuit or the position on the wafer, but also the outer shape information of the wafer, the information indicating the position of the chip in the wafer, and the like. Alternatively, layout information on a chip in the wafer is generated.
[0028]
The CAD data collection unit 13 reads the simulation result output from the simulation execution unit 14 and the layout information output from the layout information generation unit 18 and collects them as CAD data.
[0029]
The dust checker 15 detects dust on the chip or the wafer and outputs the obtained dust information. This dust information is input to the dust information collecting unit 16 and collected.
[0030]
The control unit 17 is given the measurement data collected by the measurement data collection unit 12, the CAD data collected by the CAD data collection unit 13, and the dust information collected by the dust information collection unit 16. The data storage / storage unit 19 is given and stores various information given to the control unit 17 and information processed by the control unit 17 with respect to the information. The control unit 17 performs yield analysis using the information stored in the data storage unit 19. Specifically, a process for determining the area of the defective candidate node group by superimposing the above information on the wafer or the device is performed.
[0031]
The display unit 20 displays information stored in the data storage unit 19, information processed by the control unit 17, and an area where a failure candidate node group analyzed and determined by the control unit 17 exists.
[0032]
A procedure of processing when yield analysis is performed using the analysis apparatus having such a configuration will be described with reference to the flowchart of FIG.
[0033]
First, as step 100, a test program is given to the measuring apparatus 11 to specify a test mode. For example, when a test is proceeded for each area, there are a mode in which a test is terminated when a failure location is found in any area, and a mode in which the test is completed until all areas have been tested. Specify either one. Specified items include items indicating the contents of the test, the number of times the defective part was taken in, or the pattern name where the defect exists as defect information when a defect is found, and the defective part to which level of the address external terminal There are various levels.
[0034]
In step 102, measurement for examining the characteristics of the product is performed by the measurement device 11, and in step 104, the measurement result is collected by the measurement data collection unit 12. In this case, the measurement data collection unit 12 collects the good / bad information captured in the measurement apparatus 11 in a mode designated in advance. Also collect the names of the test data that were good / bad in the test.
[0035]
In step 108, the simulation execution unit 14 executes a fault simulation and creates a fault dictionary. In step 110, the CAD data collection unit 13 reads the failure dictionary. The failure dictionary includes information for each test data regarding the node where the failure is detected.
[0036]
In step 106, the control unit 17 collates the measurement data with the failure dictionary, thereby determining the good product candidate node / defective candidate node in the circuit. In this case, if the measurement result output from the measurement apparatus 11 includes an address of a location determined to be defective or external terminal information, the failure dictionary is collated with this information, so that a non-defective candidate node and defect candidate can be obtained. It becomes easy to narrow down the nodes.
[0037]
In step 114, the layout information generation unit 18 reads layout information. This information includes layout information of each node displayed on the drawing and information indicating the correspondence between the layout and the nodes in the circuit.
[0038]
In step 112, the control unit 17 associates the non-defective product candidate nodes and the defective product candidate nodes with physical positions on the layout. Further, as step 116, the control unit 17 creates a fail map for superimposing and displaying non-defective product candidate nodes and defective product candidate nodes on the layout diagram.
[0039]
In step 120, the dust checker 15 detects dust on the chip or wafer, and in step 122, the dust information collection unit 16 collects dust information. This dust information indicates the position where dust is distributed on the surface of the chip or wafer.
[0040]
In step 118, a defect map is created by superimposing dust information on the defect map created in step 116 by the control unit 17. Using this defect map, in step 124, analysis is performed such that dust is highly influenced by a location where the dust location matches the failure candidate node.
[0041]
The processing in steps 100 to 124 is performed on a plurality of chips or wafers, statistics are processed on the result obtained in step 126, and the presence / absence of abnormality is determined. Specifically, if there is a defective candidate node at a similar location among many chips or wafers excluding the influence of dust, it is determined that there is a high possibility that there is an abnormality in the manufacturing process at that location. . Based on the determination result, the control unit 17 displays a warning on the display unit 20 as step 128 as necessary.
[0042]
According to the present embodiment, it is possible to narrow down a region where a defect exists even for a logic circuit product, which has been difficult in the past, and can provide information effective for yield analysis. .
[0043]
The above-described embodiment is an example and does not limit the present invention. For example, the apparatus shown in FIG. 1 includes a measurement data collection unit 12, a dust information collection unit 16, a CAD data collection unit 13, and a layout information generation unit 18. However, information may be directly given to the control unit 17 from the measurement device 11, the simulation execution unit 14, the layout information generation unit 18, and the dust checker 15 without going through these collection units.
[0044]
【The invention's effect】
As described above, according to the yield analysis method and the apparatus of the present invention, the failure candidate node chip or the test result obtained by measuring the characteristics, the simulation result by failure simulation, and the layout information of each element are used. By narrowing down the position on the wafer and combining this with the dust distribution, it is possible to easily and quickly perform a yield analysis to find the cause of the defect.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a yield analysis apparatus according to an embodiment of the present invention.
FIG. 2 is a flowchart showing a procedure of a yield analysis method according to an embodiment of the present invention.
FIG. 3 is an explanatory diagram showing a correspondence relationship between test data A to D and chip areas a to d when analyzing a defective portion of a chip based on the yield analysis method;
FIG. 4 is an explanatory diagram showing a result of detecting a defective candidate node group using test data A to D based on the yield analysis method.
FIG. 5 is an explanatory diagram showing a result of a test using test data A to D based on the yield analysis method.
FIG. 6 is an explanatory diagram showing a state in which a test is performed using test data A to D based on the yield analysis method, and the obtained results are superimposed to narrow down a region of a defective candidate node group.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 11 Measuring apparatus 12 Measurement data collection part 13 CAD data collection part 14 Simulation execution part 15 Dust checker 16 Dust information collection part 17 Control part 18 Layout information generation part 19 Data storage storage part 20 Display part

Claims (5)

A measurement means for outputting a measurement result obtained by performing a measurement for determining pass / fail for a plurality of chips or wafers;
A simulation execution unit that performs a failure simulation on the chip or the wafer and creates a failure dictionary indicating failure candidate nodes;
A layout information generator for generating and outputting layout information including a layout diagram showing a layout of each element in the chip or wafer;
Dust detection means for detecting dust present on the chip or wafer and outputting dust information indicating a position where the dust is distributed on the surface of the chip or wafer;
Collating the measurement result output by the measurement unit with the failure dictionary created by the simulation execution unit, narrowing down good product candidate nodes and failure candidate nodes, the layout information output by the layout information generation unit, A fail map for displaying the non-defective product candidate node and the defective candidate node on the layout diagram in association with the narrowed non-defective product candidate node and the defective candidate node is created, and the non-defective product candidate node and the defective candidate are created. A controller that superimposes the position of the node and the position of the dust to analyze the cause of the failure of the failure candidate node;
A display unit for displaying the fail map;
A yield analysis apparatus comprising: In addition to the failure simulation, the simulation execution unit includes a logic simulation for determining the quality of the logic description of the circuit pattern, a function simulation for determining the quality of the functional description of each cell, and a circuit simulation for determining the quality of the circuit operation. And output the simulation results for each.
The control unit collates the simulation result output from the simulation execution unit and the measurement result output from the measurement unit to narrow down the non-defective product candidate node and the defective candidate node, and narrows down the layout information and the narrowed down 2. A yield analysis according to claim 1, wherein a failure map is created for associating non-defective product candidate nodes and non-defective candidate nodes and displaying the non-defective product candidate nodes and the defective candidate nodes on the layout diagram. apparatus. The control unit determines that the influence of dust is high at a position where the position of the defect candidate node and the position of the dust coincide with each other, and excluding the influence of the dust, a predetermined number or more in the plurality of chips or wafers If the defect candidate node group exists in common, it is determined that there is a high possibility that there is an abnormality in the manufacturing process at that location, and a warning is displayed on the display means based on the determination result The yield analysis apparatus according to claim 1 or 2, characterized in that Performing measurement for determining the quality of a plurality of chips or wafers using a measurement means, and generating a measurement result;
Performing a simulation for determining the presence or absence of a failure of the chip or wafer, and generating a failure dictionary indicating a node in which the failure is detected;
Collating the measurement result with the fault dictionary and narrowing down non-defective candidate nodes and defective candidate nodes;
The non-defective product candidate node and the defective candidate node are superimposed on the layout diagram by associating layout information including a layout diagram showing a layout of each element on the chip or the wafer with the good product candidate node and the defective candidate node. Creating a fail map for display;
Detecting the position of dust present on the chip or wafer;
Superimposing the position of the good candidate node and the defect candidate node and the position of the dust to analyze the cause of the defect of the defect candidate node;
Displaying the fail map on a display means;
A yield analysis method characterized by comprising: In the step of analyzing the cause of the failure of the failure candidate node, it is determined that the influence of dust is high at a location where the position of the failure candidate node and the position of the dust match, In the case where the defect candidate node group exists in common in a predetermined number or more of the chips or wafers, it is determined that there is a high possibility that there is an abnormality in the manufacturing process at that location,
5. The yield analysis method according to claim 4, further comprising a step of displaying a warning by the display means based on the determination result.

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