CN111653500A

CN111653500A - Method for judging wafer yield loss

Info

Publication number: CN111653500A
Application number: CN202010563067.1A
Authority: CN
Inventors: 赵韦韦; 王恺; 沈萍
Original assignee: Shanghai Huali Integrated Circuit Manufacturing Co Ltd
Current assignee: Shanghai Huali Integrated Circuit Manufacturing Co Ltd
Priority date: 2020-06-19
Filing date: 2020-06-19
Publication date: 2020-09-11

Abstract

The invention discloses a method for judging wafer yield loss, which comprises the following steps: generating a wafer map through wafer testing; obtaining each defect structure on the surface of the wafer, and defining the coordinates of the defect structure; and comparing the defects with the wafer map, and analyzing the influence of the defects on yield loss in the coordinates according to a preset analysis mode. The invention can pertinently analyze the defect with high influence on the yield and pertinently improve the defect, thereby being capable of rapidly improving the yield of the product.

Description

Method for judging wafer yield loss

Technical Field

The invention relates to the technical field of semiconductor integrated circuit manufacturing methods, in particular to a method for judging yield loss of a wafer.

Background

Before each IC is subjected to the post-process, CP (chip Prober) is required to be carried out, and the CP and chip Prober tests are divided into wafer probe testing and finished product testing, and the CP and chip Prober tests have the main functions of detecting problems generated in the manufacturing process of the IC and finding out reasons so as to verify whether the functions of the product are normal, and picking out poor products and distinguishing performance grades.

In the wafer manufacturing process, a small error in any link will cause the failure of the whole chip, and particularly, as the Critical Dimension (CD) of a circuit is continuously reduced, the requirement on process control becomes stricter and stricter, so that the defect detection needs to be performed on the product in the actual production process so as to find and solve the problem in time.

As semiconductor integrated circuits are rapidly developed and the critical dimensions are scaled down, the fabrication processes thereof become more complex. Current advanced integrated circuit fabrication processes typically involve hundreds of process steps, and as long as one of the process steps is defective, defects may occur in the entire semiconductor integrated circuit chip on the wafer, and in the worst case, the entire chip may fail. Therefore, in the industry, a scanning machine scans the defects of the wafer under a certain scanning program, and compares the number of the scanned defects with the control limit to determine whether the defects on the wafer exceed the control standard, and then performs corresponding processing.

In wafer fabrication, pulling a single crystal, slicing, lapping, polishing, layer-adding, photolithography, doping, heat treatment, probing and scribing are common wafer fabrication processes, and in the series of processes, chemical vapor deposition, optical development and chemical mechanical polishing may cause defects on the wafer surface.

Among the defect types of wafers, the non-pattern wafer and the pattern wafer are the most common two wafer types, and among the specific wafer defects, redundancy, crystal defects, and scratch pattern missing are the more common wafer defects. The wafer surface redundancy is a common defect type on the wafer surface, and the wafer surface redundancy is likely to cause the wafer surface redundancy defects due to nano-scale micro-particles, micro-scale dust and residues of related processes.

In the manufacturing process of a semiconductor chip with nodes of 28nm and below, different defects of different layers have great influence on the yield of products; by analyzing the influence of each defect on yield loss, the defect with large influence on the yield loss is improved, and the yield of the product can be better improved. At present, an effective off-line detection method is not available for the influence of defects on yield, and the influence of the defects on the yield can be known only through comparison after CP Map results are obtained, so that the influence of the defects on yield loss is analyzed with long hysteresis, and the defects with the same type and different shapes are improved disadvantageously.

Disclosure of Invention

The technical problem to be solved by the invention is as follows: the defects with high influence on the yield are analyzed in a targeted manner, and the defects are improved in a targeted manner, so that the yield of the product can be rapidly improved.

In order to solve the technical problem, the invention discloses a method for judging the yield loss of a wafer, which comprises the following steps: generating a wafer map through wafer testing; obtaining each defect structure on the surface of the wafer, and defining the coordinates of the defect structure; and comparing the defects with the wafer map, and analyzing the influence of the defects on yield loss in the coordinates according to a preset analysis mode.

Preferably, the method further comprises the following steps: and correcting the analysis and judgment flow according to the data of the relationship between the yield and the defects.

Preferably, the preset analysis mode is as follows: and analyzing the structure of the defect, finding out a critical value influencing the defect, and adding the critical value into an analysis judgment process database.

Preferably, the structure of the defect is analyzed based on the location of the defect in three directions X, Y, Z in the coordinate axis.

Preferably, the preset analysis mode is to analyze the material of the defect.

Preferably, the predetermined analysis manner is whether the defect falls on the silicon dioxide layer.

Preferably, the preset analysis mode is whether the contact hole is connected with the metal or not.

Preferably, the preset analysis mode is to analyze whether a low-voltage device exists at the position where the defect falls.

Preferably, the preset analysis mode is to analyze whether a metal connection line exists at the position where the defect falls.

According to the wafer yield calculation method, the appearance, the position and the material of the defect are analyzed, whether the defect has yield loss or not can be known, so that the yield of the wafer can be calculated quickly, the defect with high influence on the yield can be analyzed in a targeted manner, the defect is improved in a targeted manner, and the yield of the product can be improved quickly.

Drawings

FIG. 1 is a flowchart illustrating a method for determining yield loss of a wafer according to an embodiment of the present invention.

Detailed Description

The technical solutions in the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Example one

The embodiment discloses a method for judging wafer yield loss, which comprises the following steps:

step one, a wafer map is generated through wafer testing.

Wafer testing (CP) is a first station of semiconductor subsequent packaging testing, and refers to testing voltage, current, timing sequence, etc. of a chip die on a wafer (wafer) before packaging, so as to verify whether each chip meets product specifications. After the wafer test, a wafer MAP graph file for displaying the wafer test result distribution can be obtained.

And step two, obtaining each defect structure on the surface of the wafer, and defining the coordinates of the defect structure.

Because the wafer manufacturing process includes hundreds of steps, a small error in any link will cause the failure of the whole chip, especially along with the continuous reduction of the critical dimension of the circuit, the requirement for process control is more and more strict, the problem must be found and solved in time in the production process, and therefore, the defect detection must be carried out. At present, optical and electronic defect detection equipment is generally used for online detection of products, signals of several chips are collected firstly, and physical images on the chips are converted into data images which can be represented by different bright and dark gray scales.

A preferred detection method is to acquire image data of a plurality of chips simultaneously, and if a certain chip has a defect, then compare the chip with other chips to obtain a position with signal difference, and the corresponding position with complementary difference in each comparison result is the position on the chip where the defect is detected.

And step three, comparing the defects with the wafer map, analyzing the influence of the defects on yield loss in the coordinates according to a preset analysis mode, and forming an analysis judgment flow.

As shown in fig. 1, the analysis and determination process of a preferred embodiment is as follows:

firstly, analyzing the CP influence of the Micro Scratch according to the CP MAP; meanwhile, the gray scale of the depth of the Micro Scratch is retrieved by SEM (scanning electron microscope).

Scanning Electron Microscopy (SEM) is an observation instrument that is intermediate between transmission electron microscopy and optical microscopy. The method utilizes a focused narrow high-energy electron beam to scan a sample, excites various physical information through the interaction between a light beam and a substance, and collects, amplifies and re-images the information to achieve the purpose of characterizing the microscopic morphology of the substance.

The influence of CP of Micro Scratch can be analyzed by a big data analysis algorithm, if there is CP LOSS, the corresponding gray scale is output, and if there is no CP LOSS, 0 is output.

Then, a database is formed by comparing a large number of points of CP LOSS with the gray scale of the scanning electron microscope image to find a value T1 that can cause the gray scale of CP LOSS.

Then, it is analyzed whether any lot gray scale exceeds T1, if T1 is exceeded, CP loss is identified, and if T1 is not exceeded, no annotation is made.

Example two

The process of the second embodiment further includes the following steps based on the first embodiment: and correcting the analysis and judgment flow according to the data of the relationship between the yield and the defects.

EXAMPLE III

In a third embodiment, based on the first or second embodiment, the predetermined analysis manner may be: analyzing the structure of the defect according to the positions of the defect in X, Y, Z directions in the coordinate axis, finding out the critical value influencing the defect and adding the critical value into an analysis judgment process database.

The predetermined analysis method may also be a method of analyzing the material of the defect, including whether the defect falls on the silicon dioxide layer, whether the contact hole is connected to the metal, and the like.

The preset analysis mode can also be to analyze whether a low-voltage device is at the position where the defect is located or not and whether a metal connecting line is at the position where the defect is located or not.

The present invention has been described in detail with reference to the specific embodiments, which are merely the preferred embodiments of the present invention, and the present invention is not limited to the embodiments discussed above. Obvious modifications or alterations based on the teachings of the present invention should also be considered to fall within the technical scope of the present invention. The foregoing detailed description is provided to disclose the best mode of practicing the invention, and also to enable a person skilled in the art to utilize the invention in various embodiments and with various alternatives for carrying out the invention.

Claims

1. A method for determining wafer yield loss, comprising:

generating a wafer map through wafer testing;

obtaining each defect structure on the surface of the wafer, and defining the coordinates of the defect structure;

and comparing the defects with the wafer map, and analyzing the influence of the defects on yield loss in the coordinates according to a preset analysis mode.

2. The method of determining wafer yield loss as claimed in claim 1, further comprising the steps of: and correcting the analysis and judgment flow according to the data of the relationship between the yield and the defects.

3. The method according to claim 1 or 2, wherein the predetermined analysis method is: and analyzing the structure of the defect, finding out a critical value influencing the defect, and adding the critical value into an analysis judgment process database.

4. The method of claim 3, wherein the structure of the defect is analyzed according to the position of the defect in three directions X, Y, Z on the coordinate axis.

5. The method of claim 1, wherein the predetermined analysis is performed by analyzing the material of the defect.

6. The method of claim 5, wherein the predetermined analysis is whether the defect is in a silicon dioxide layer.

7. The method of claim 5, wherein the predetermined analysis is whether the contact hole is connected to a metal.

8. The method of claim 1, wherein the predetermined analysis is performed to determine whether there is a low voltage device at a defect location.

9. The method of claim 1, wherein the predetermined analysis is to analyze whether there is a metal connection at a defect location.