JPS59181711A - Differential amplifier circuit - Google Patents
Differential amplifier circuitInfo
- Publication number
- JPS59181711A JPS59181711A JP5447783A JP5447783A JPS59181711A JP S59181711 A JPS59181711 A JP S59181711A JP 5447783 A JP5447783 A JP 5447783A JP 5447783 A JP5447783 A JP 5447783A JP S59181711 A JPS59181711 A JP S59181711A
- Authority
- JP
- Japan
- Prior art keywords
- differential
- collector
- differential amplifier
- diode
- amplifier circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/68—Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Amplifiers (AREA)
Abstract
Description
【発明の詳細な説明】 本発明は差動増幅器に関するものである。[Detailed description of the invention] The present invention relates to a differential amplifier.
第１図は従来の一般的な例を示す。アナログ信号は入力
端子４１．５１から差動増幅回路】６−１に入力される
。差動増幅回路１６−１はエミッタ共通の差動ペアトラ
ンジスタ９−１．１０−１ のベースにそれぞれ接続さ
れている。前記差動ペアトランジスタ９−１．１０−１
の共通エミッタは電流スイッチ用トランジスタ１１−１
のコレクタに接続されている。以上の様な差動増幅回路
がｎ個（ｎン２）（１６−１からｌ６−ｎ）存在し、そ
れそ゛れの差動ペアトランジスタ９−１ ＋ １０−１
〜９−ｎ 、 １０−ｎ のコレクタ各々出力端子２
，３に共通に接ｆ＊されると共に、一端が電源端子１に
接続さ匙ている負Ｍ抵抗７，８の他端にも各々接続され
、又電流スイッチ用トランジスタ１１−１〜１１−ｎの
エミッタは共通に接続され、さらに駆動用電流源１２に
接続されている。電流スイッチ用トランジスタ１１−１
〜１１〜ｎのベースはマルチプレクサの出力など選択信
号が印加され、差動ベアトランジスタ９−１゜１０−１
〜９−ｎ、１０−ｎ の活性、不活性を決定する。FIG. 1 shows a conventional general example. The analog signal is input from input terminals 41.51 to the differential amplifier circuit 6-1. The differential amplifier circuit 16-1 is connected to the bases of differential pair transistors 9-1 and 10-1, each having a common emitter. Said differential pair transistor 9-1.10-1
The common emitter of is the current switch transistor 11-1.
connected to the collector. There are n differential amplifier circuits as described above (n-2) (16-1 to 16-n), and each differential pair transistor 9-1 + 10-1
~9-n, 10-n collector each output terminal 2
. The emitters of the two are connected in common and further connected to a driving current source 12. Current switch transistor 11-1
A selection signal such as the output of a multiplexer is applied to the bases of ~11~n, and differential bare transistors 9-1゜10-1
Determine the activity and inactivity of ~9-n and 10-n.
通常はｎ組のアナログ入力端子から一絹だけを選択し、
増幅する多チャンネル入力−出力の選択増幅器として使
われる。Normally, only one terminal is selected from n sets of analog input terminals,
Used as a multi-channel input-output selection amplifier.
従来の一般的な例においては、１１個の差動増幅回路の
うち選択されず（Ｃ不活性状態である差動増幅回路の差
動ベアトランジスタのベースに信号が印加された場合、
信号を受けた差動ペアトランジスタのコレクタ・ベース
容量ＣＪｃによって入力端子・出力端子間が直結カップ
リングされ、選択されなかったトランジスタへの入カ侶
号が出力端子に現われていた。すなわち、選択されてい
ない入力端子から出力端子までの利得と、選択された入
力端子から出力端子までの利得との比であるチャンネル
分離度が悪いという欠点があった。In a typical conventional example, when a signal is applied to the base of a differential bare transistor of a differential amplifier circuit that is not selected among the 11 differential amplifier circuits (C is in an inactive state,
The input terminal and output terminal were directly coupled by the collector-base capacitance CJc of the differential pair transistor that received the signal, and the input signal to the unselected transistor appeared at the output terminal. That is, there is a drawback that the degree of channel separation, which is the ratio of the gain from an unselected input terminal to an output terminal to the gain from a selected input terminal to an output terminal, is poor.
本発明の目的は、上記チャンネル分離度を向上させた差
動増幅回路を提供することにある。An object of the present invention is to provide a differential amplifier circuit with improved channel separation.
本発明の差動増幅回路は、ベースに大刀信号を受け、そ
れぞれのエミッタが共通に接続された、差動ペアトラン
ジスタのコレクタに直列に接続された負荷を介して出力
を取シ出す構成とし、交流的にみて、差動ペアトランジ
スタのコレクタに直列に小容量コンデンサを介して出力
を得ることを特徴としている。The differential amplifier circuit of the present invention has a configuration in which the base receives a long signal and outputs an output through a load connected in series to the collectors of differential pair transistors whose respective emitters are commonly connected. From an AC point of view, it is characterized by obtaining an output via a small capacitor in series with the collector of a differential pair transistor.
第２図に本発明の実施例を示す。第１図と対応するもの
には同一の番号を付しである。単位となる差動増幅回路
１６−１・・・１６−ｎの１つである差動増幅回路１６
−１はアナログ大刀信号を受ける入力端子４１ 、５１
が、エミッタ共通のに動ペアトランジスタ９−１．
１０−１のベースにそれぞれ接続されている。差動ペア
トランジスタ９−１．１０−１の共’４エミッタ接続点
け′戚流ス１ノチ用トクンジスタ１１−１のコレクタに
接縦されている。又差動ペアトランジスタ９−１．１０
−１のそれぞれのコレクタには、ショットキーダイオー
ド１４−１．１５−１のカソード側がそれぞｎ接続され
ている。以上の様な差動増幅回路が１６１から１８まで
のｎ個（ｎ≧２）存在し、それぞれのショットキーダイ
オード１４−１．１５−１〜１４−ｎ、１５−ｎのアノ
ードは各々出力端子２，３に共通に接続されると共に、
一端が電源端子１に接続されている負荷抵抗７゜８の他
端にも各々接続されている。又電流スイッチ用トランジ
スタ１１−１〜】１−ｎのエミッタは共通に接続され、
さらに駆動用電流源１２に接続されている。FIG. 2 shows an embodiment of the present invention. Components corresponding to those in FIG. 1 are given the same numbers. Differential amplifier circuit 16 which is one of differential amplifier circuits 16-1...16-n serving as a unit
-1 is the input terminal 41, 51 that receives the analog long sword signal.
However, the active pair transistors 9-1.
10-1, respectively. The common emitter connection points of the differential pair transistors 9-1 and 10-1 are connected vertically to the collector of the differential current transistor 11-1. Also, differential pair transistor 9-1.10
The cathode sides of Schottky diodes 14-1, 15-1 are connected to the collectors of each of the Schottky diodes 14-1 and 15-1. There are n differential amplifier circuits 161 to 18 (n≧2) as described above, and the anodes of each Schottky diode 14-1, 15-1 to 14-n, and 15-n are output terminals. 2 and 3 in common, and
One end of the load resistor 7.8 is connected to the power supply terminal 1, and the other end of the load resistor 7.8 is also connected to the power supply terminal 1. In addition, the emitters of the current switch transistors 11-1 to 1-n are connected in common,
Furthermore, it is connected to a driving current source 12.
本発明においては、差動ペアトランジスタのコレクタと
出力端子２，３との間にダイオード・１４−１ 、１５
−１・・・１４−ｎ、１５−ｎを挿入したことが従来と
異なる。この為不活性状態の差動増幅回路において、従
来は入力端子４−１．５−１・・・４−ｎ、５−ｎと出
力端子２，３が交流的には、差動ペアトランジスタのコ
レクタ・ベース間容量ＣＪＣによって直結カップリング
されていたが、本発明ではトランジスタのコレクタ・ベ
ース間容量ＣＪｃとダイオードの接合容量ＣＪ Ｏシリ
ーズ
ＣＪＣＸ ＣＪ
となりカップリング容量は著しく減少し、選択されてな
い入力端子への利得は大巾に小さくなる。In the present invention, diodes 14-1 and 15 are connected between the collectors of the differential pair transistors and the output terminals 2 and 3.
-1... 14-n and 15-n are inserted, which is different from the conventional method. For this reason, in a differential amplifier circuit in an inactive state, conventionally input terminals 4-1, 5-1...4-n, 5-n and output terminals 2 and 3 are Direct coupling was performed by the collector-base capacitance CJC, but in the present invention, the collector-base capacitance CJc of the transistor and the junction capacitance CJ O series CJCX CJ of the diode reduce the coupling capacitance significantly. The gain to the terminal is greatly reduced.
つｌチャンネル分離度は向上し、−例では２５ｄＢ以上
向上した。又ダイオード挿入による差動利得への影響は
捷ったく無い。The channel separation was improved by more than 25 dB in the - example. Moreover, the influence on the differential gain due to the insertion of the diode is not significant.
以上の様に、本発明によｐチャンネル分離度は著しく向
上する。又わずかダイオードを加えるだけであり、特に
ショットキーダイオードにおいてはＮＰＮ ）ランジス
タと同一の領域に形成することも可能であり、集積回路
化した場合チップ面積の増大はほとんど無い。As described above, the present invention significantly improves the p-channel separation. In addition, only a few diodes are added, and in particular, a Schottky diode can be formed in the same area as an NPN transistor, and when integrated into an integrated circuit, there is almost no increase in chip area.
上記例においては、差動ペアトランジスタがＮＰＮ型、
負荷が抵抗の場合を示し５たが、ＰＮＰトランジスタの
差動ペアトランジスタを用いても、負荷が抵抗以外であ
っても同様の効果が得られることは言うまでもない。ま
た、ダイオードもショットキー型に限らず、どのような
形式のものでも良い。In the above example, the differential pair transistors are NPN type,
Although the case where the load is a resistor is shown in 5, it goes without saying that the same effect can be obtained even if a differential pair of PNP transistors is used and the load is other than a resistor. Furthermore, the diode is not limited to the Schottky type, and may be of any type.
第１図は差動増幅回路の従来例を示す回路図、第２図は
本発明の一実施例を示す回路図である。
１・・・・・・電源端子、２．３・・・・・・出力端子
、４−１゜５−１〜４−ｎ、５−ｎ・・・・・・差動入
力端子、６−１〜５−ｎ・・・・・・差動回路選択端子
、７，８・・・・・・負荷抵抗、９−１．１０−１〜９
−ｎ１ｉｏ−ｎ・・・・・・差動ペアトランジスタ、１
１−１〜１１−ｎ・・・・・・電流スイッチ用トランジ
スタ、１２・・・・・・駆動用電流源、１４−１．１５
−１〜１４−ｎ１１５−ｎ・・・・・・ショットキーダ
イオード、２７ 図
鵠 ？ワ
６FIG. 1 is a circuit diagram showing a conventional example of a differential amplifier circuit, and FIG. 2 is a circuit diagram showing an embodiment of the present invention. 1...Power supply terminal, 2.3...Output terminal, 4-1゜5-1 to 4-n, 5-n...Differential input terminal, 6- 1 to 5-n... Differential circuit selection terminal, 7, 8... Load resistance, 9-1.10-1 to 9
-n1io-n...Differential pair transistor, 1
1-1 to 11-n... Current switch transistor, 12... Driving current source, 14-1.15
-1~14-n115-n... Schottky diode, 27 Figure ? Wa 6
Claims (1)
スタと、前記第１および第２のトランジスタのコレクタ
にそれぞれ直列に接続されたダイオードと、前記ダイオ
ードの他端に接続された負荷とを有することを特徴とす
る差動増幅回路０first and second transistors whose emitters are connected in a common lotus; a diode connected in series to the collectors of the first and second transistors, respectively; and a load connected to the other end of the diode. Differential amplifier circuit 0 characterized by
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5447783A JPS59181711A (en) | 1983-03-30 | 1983-03-30 | Differential amplifier circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5447783A JPS59181711A (en) | 1983-03-30 | 1983-03-30 | Differential amplifier circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59181711A true JPS59181711A (en) | 1984-10-16 |
| JPH0244164B2 JPH0244164B2 (en) | 1990-10-03 |
Family
ID=12971743
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5447783A Granted JPS59181711A (en) | 1983-03-30 | 1983-03-30 | Differential amplifier circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59181711A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4780630A (en) * | 1986-06-27 | 1988-10-25 | Commissariat A L'energie Atomique | Double differential summing amplifier with four independent inputs |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55138981A (en) * | 1979-04-16 | 1980-10-30 | Matsushita Electric Ind Co Ltd | Signal amplifying circuit |
| JPS5884512A (en) * | 1981-11-16 | 1983-05-20 | Matsushita Electric Ind Co Ltd | Signal amplifying circuit |
-
1983
- 1983-03-30 JP JP5447783A patent/JPS59181711A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55138981A (en) * | 1979-04-16 | 1980-10-30 | Matsushita Electric Ind Co Ltd | Signal amplifying circuit |
| JPS5884512A (en) * | 1981-11-16 | 1983-05-20 | Matsushita Electric Ind Co Ltd | Signal amplifying circuit |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4780630A (en) * | 1986-06-27 | 1988-10-25 | Commissariat A L'energie Atomique | Double differential summing amplifier with four independent inputs |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0244164B2 (en) | 1990-10-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4194166A (en) | Differential amplifier with a current mirror circuit | |
| JPS59181711A (en) | Differential amplifier circuit | |
| EP0181752A2 (en) | Extended range amplifier circuit | |
| JPH0124377B2 (en) | ||
| US6404266B1 (en) | Differential input stage with bias current reduction for latch-up prevention | |
| JPH0738981Y2 (en) | Constant current source circuit | |
| JPH0733463Y2 (en) | Data transmission circuit | |
| JPS6098715A (en) | Comparator | |
| JPS6276911A (en) | Differential circuit | |
| JP3605237B2 (en) | Monitor output circuit | |
| JPS59156010A (en) | Driver stage circuit of output amplifier | |
| JPS58164339U (en) | Signal switching circuit | |
| JPS6076838A (en) | Unit interface circuit | |
| JPS5972872A (en) | Signal switching device | |
| JPH11355066A (en) | Error amplifier circuit | |
| JPS61166614A (en) | Constant current circuit | |
| JPS62264706A (en) | Output stage circuit | |
| JPS6364407A (en) | Emitter follower circuit | |
| JPS6097705A (en) | Differential amplifier | |
| JPH03169108A (en) | Semiconductor integrated circuit | |
| JPH05160714A (en) | Ttl circuit | |
| JPH0697802A (en) | Input circuit using mos transistor of integrated circuit | |
| JPH02137516A (en) | Semiconductor switch driving circuit | |
| JPS60235514A (en) | Current mirror circuit | |
| JPS59140707A (en) | Amplifier |