JPS59181055A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To prevent the generation of a parasitic capacity between a gate and a substrate by forming a different conductive type region on a semiconductor laminate corresponding to semiconductor elements arranged through a high resistance semiconductor layer on the laminate which forms a photosemiconductor element. CONSTITUTION:After a high density n type layer 12 is formed on an n type substrate 11, a p type layer 111 is formed. Then, an i type layer of n type low density, a high resistance layer 15 and an FET operation layer 16 are formed, and a positive electrode forming region of photodiode (PD) is formed by etching. Then, p type impurity is introduced to part of an i type layer 13 of PD to form a p type layer 14, and a positive electrode 20 and a negative electrode 21 of FET electrodes 17, 18, 19, are formed. Thus, different conductive type region 111 is formed on part of the laminated formed with the PD is formed, and a transistor is formed thereon. Accordingly, a parasitic capacity between a gate and a substrate can be prevented.

Description

Detailed Description of the Invention (11) Technical Field of the Invention The present invention relates to a semiconductor integrated circuit device, and in particular to an integrated optical semiconductor device in which a light receiving element and a voltage/current control element such as a transistor are integrated on the same semiconductor substrate. The present invention relates to a device, and to improvements in structure for realizing an integrated optical conductor device that is easy to manufacture, has a fast response speed, and has excellent characteristics.

(2) Background of the technology Since the signal generated by the light receiving element is generally weak, it is necessary to amplify it using an amplifier circuit.

On the other hand, since the light-receiving element usually has a small rectangular shape with sides of about 0.3 (mm), it is better to combine the light-receiving element and the amplifier circuit into a single unit than to combine the light-receiving element and the amplifier circuit, which are formed separately. The integrated optical conductor device formed on a semiconductor substrate can be highly integrated, and is industrially significant.

(3) Prior art and problems A typical example of an integrated optical semiconductor device in the prior art in which a junction type light receiving element and a field effect transistor (hereinafter referred to as FET) are formed on a single conductor, a1: board. Here are two examples.

FIG. 1 shows a PIN type photomeio-P (hereinafter referred to as FD).

) and the field effect transistor are made of gallium arsenide (GaAs).
) This is an example of a structure integrated on a substrate.

This is a conductor layer structure specific to FD formed on a gallium arsenide (GaAs) base, that is, an n-type gallium arsenide (n-GaAs) layer 2 (hereinafter referred to as nN), a low concentration n-type gallium A laminate consisting of a (n"'-GaAθ) layer 3 (hereinafter referred to as "L layer") is spread flat, and a high-resistance semiconductor is placed on top of the top layer 3, which is lattice matched with this layer. A layer 5 (hereinafter referred to as a high-resistance layer) is formed to cut off conduction with the PD section (the area surrounded by a dashed line A in the figure), and a grid is formed on this high-resistance layer 5. In this example, the matching semiconductor is n-type gallium arsenide (n-
FIICT (area surrounded by a dashed line B in the figure) is formed, and has an active layer 6 made of GaAs). In the figure, 4 is a p-type diffusion layer (hereinafter referred to as p layer).

7.8.9 are the FET source, drain, and
There is a gate electrode, 1o and 1d are the positive and negative electrodes of FD respectively!
be. Such a structure has the advantage that the integration process is simple because it is generally planar, but it cannot be said that the response speed is necessarily satisfactory. This is because a parasitic capacitance is generated between the gallium arsenide (GaAs) layer 3 and the PET dirt 9 because the gallium arsenide (GaAs) layer 3 exists.

Figure 2 also shows an example of a structure in which a PIN-type FD and FEAT are integrated on a gallium arsenide (GaAB) substrate, as in the above example.
aAs) substrate 1' is used as a common substrate, and PD (
This is the point where the FET (the area surrounded by the dotted tin line A' in the figure) and the FET (the area surrounded by the dotted chain line B' in the figure) are juxtaposed. In this case, although the PET substrate is semi-insulating, the problem of parasitic capacitance does not occur, but it is difficult to avoid the formation of steps due to the structure, and since it is not planar, it has the disadvantage that the manufacturing process is not easy.

As described above, none of the structures in the prior art were satisfactory and left room for improvement.

(4) Purpose of the Invention The purpose of the present invention is to meet this demand, and includes a PD and a current control element such as a FET arranged side by side on a single substrate, which is generally of a planar type. An object of the present invention is to provide an integrated optical semiconductor device that is easy to process and has improved response characteristics by preventing the generation of parasitic capacitance between the gate and the substrate. The object is to provide a semiconductor element electrically connected to the semiconductor element via a high-resistance semiconductor layer in a part of the semiconductor layered body constituting the optical semiconductor element, and to provide the semiconductor element corresponding to the semiconductor layered body. This is achieved by a semiconductor integrated circuit device in which one of the semiconductor layers constituting a semiconductor stack is provided with a region having a conductivity type different from that of the semi-integrated layer.

The present invention provides an integrated optical semiconductor device in which a light-receiving element part and a control element part are formed in a common semiconductor laminate, and which is different from the above-mentioned laminate. A layer of a different conductivity type is formed, and the built-in potential of the PN junction is used to create a depletion layer between the control element section and this layer of a different conductivity type, thereby preventing the generation of parasitic capacitance. .

The spread of this depletion layer depends on the impurity concentration in the region where this depletion layer spreads, and the lower this concentration is, the larger the spread of the depletion layer becomes. Therefore, it is necessary to select this impurity concentration as low as possible. The formation of the depletion layer can be further ensured by providing an electrode in the above-mentioned regions of different conductivity types provided at the bottom of the control element section and applying a reverse noise voltage to the pNg layer in contact with this region. Since the control for generating a certain depletion layer in a desired range becomes easier, the effect of preventing the generation of parasitic capacitance becomes more reliable and effective.

However, in this case, it is necessary to make the potentials of the light receiving element section and the control element section independent, so it is necessary to ensure electrical isolation between them.

In addition, semiconductor materials include combinations of gallium nitride (GaAs) and aluminum gallium arsenide (AlGaAs) or aluminum gallium arsenide phosphide (AlGaAsP), and combinations of indium phosphide (NP) and indium gallium phosphide (InGaP) or indium gallium arsenide phosphide ( A combination of semiconductors such as GaAsP) is desirable, but this combination of semiconductors is only an example and is not limited to this.

With this configuration, 0, which was difficult to avoid in the conventional technology,
It was confirmed that the parasitic capacitance of about 1 (pF) was reduced to about 0.0 oz (pF), that is, about 1/4.

(6) Embodiments of the Invention With reference to the drawings, three examples of 5N embodiments of the present invention will be described below, each using gallium arsenide (GaAs) as a semiconductor, a P-type N-type PD, a FIT, and a force-integrated one. We will explain the manufacturing process of integrated optical semiconductor devices.

Example 1: Refer to Figure 3. Made of n-type gallium arsenide (n-GaAs) containing n-type impurities of about 1017 to 10" (Cm-3), the thickness is t.
A vapor phase epitaxy method, metalorganic vapor phase epitaxy (hereinafter referred to as MOOVD method), is performed on a substrate 11 of about 300 (μm).

) etc. to add n-type impurities to 5 x 11017 (
It is made of n-type gallium arsenide (n-GaAe) containing a relatively high concentration of about a""') and has a thickness of 3 to 5 (μm).
An n-layer 12 having a thickness of about f is formed.

Refer to FIG. 4 A region corresponding to the above n-layer 120FBT formation region (here,
O forming the p-type region 111, which is a characteristic configuration of the present invention.
This step can be carried out by using a thermal diffusion method or an ion implantation method, and as a p-type impurity, for example, zinc (Zn), beryllium (Be), etc.
Introduce it to a depth of 8 degrees. Note that it is desirable that the impurity concentration of this p-type region 111 is relatively high, about 1017 (Cm-3). ) n-type impurity at a low concentration, i.e., 1014 (cm-3)15<
Low concentration n-type gallium arsenide (n-GaAe) contained in
One layer of gallium arsenide (GaAs) with high resistance by doping with oxygen (0) or undoped gallium arsenide (G
aAs) with a thickness of 3. ooo <';+> high resistance layer 15, (c) n-type impurity at IQ17
m-3) n-type gallium arsenide (n-GaAe
) and a thickness of about 0.2 (μm), which will become the PET active layer 16' is sequentially formed (see Figures 6, 7, and 8).Next, a three-stage etching process is performed. By executing this, the light receiving element section and the control element section are separated.

That is, first, the FI on the layer 16' is formed using a known method.
An etching process (not shown) is applied to the region that will become the T active layer.
and remove other areas of layer 16' using a wet or dry etching process to form an IF''
The ET active layer 16 is left (FIG. 6). Subsequently, the high-resistance layer 15 is etched away from the region except the lower region of the operation layer N16 by a similar process (FIG. 7). Furthermore, by etching a part of the first layer 13 of the FD until it reaches the n layer 12, the positive electrode forming area 2 of the FD is etched.
2 (Figure 8).

Refer to Fig. 89. For example, a p-oxide film such as zinc (Zn) is applied to a part of the first layer 13 of the FD.
This step of forming one layer 14 of PD by introducing type impurities can be performed using thermal diffusion, ion implantation, etc., as described above, and the depth of one layer 14 is l (μm). ) is desirable.

Refer to FIG. 10. Finally, electrodes are formed in each predetermined region using a known method. First, the FET source/drain electrode 17.1B made of a gold/germanium (Au/Ge)/nickel (N1) double layer and the FD positive electrode 20 are formed simultaneously, and then a gold/zinc (Au-Zn) double layer is formed. The negative electrode 21 of the PD is made of aluminum (A1), and the gate t is made of aluminum (A1).
After forming the pole 19, the plate 11 is polished from the back side to a thickness of about 100 (μm), and the manufacturing process is completed.

Second Example FIG. 11 is a sectional view of a seed-type optical semiconductor device according to a second example of the present invention. The manufacturing process of this example is exactly the same as that shown in the first example above, except for the process of forming the p-removal region 111', which is a characteristic feature of the present invention. That is, in the first example, p! Introducing impurities to form pm region Ill
In this example, (1) n layer 1
A layer of p-type gallium arsenide (p-GaAs) containing p-type impurities of about 10 i 7 (Cm-3) and having a thickness of about 1 (μm) was formed on the entire surface of the mold region. A p-type region 111' is formed by forming a mask having an opening, selectively growing a p-type gallium arsenide (p-GaAs) layer, and then removing the mask.

In both the structures of the first example and the second example, the p-type layer 111
．． Due to the built-in potential of the pn junction formed at the interface between 111' and the low concentration n-type layer (1%) 13! 7-
A depletion layer spreads in the 1N13 below the top electrode 19, and the generation of parasitic capacitance is effectively prevented. In the above two examples, 1
By adjusting the concentration of the layer 13 to about 1014 (cm'''3), the depletion J@ is reduced to the high resistance layer 15 and the p-type N1t.
It can be generated over the entire area of one layer 13 sandwiched between 1 and 111'. However, even if the depletion layer spreads incompletely in this case, from an electrical point of view, the parasitic capacitance of capacitors connected in series will still be significantly reduced. In order to further ensure and control the spread of the depletion layer in the above two examples, the present invention has a structure in which an electrode is provided on the p-type layer. Made of gallium arsenide (GaAs) and has 30 steps.
On the substrate 31, which has a diameter of approximately 0 (μm), an n layer containing 5 x 1017 (cm-3)i degrees of tin (Sn) as an n-type impurity is grown using a vapor phase growth method or M'OOV D method. An n layer 32 made of type gallium arsenide (n-GaAs) and having a thickness of about 3 (μm) is formed. Next, a p-type impurity such as zinc (Zn
), beryllium (Be), etc. are introduced to a depth of about 2 (μm) to form a p-type hollow region 131, which is a characteristic structure of the present invention. At this time, the impurity concentration of the p-type region 131 is 1017
1017 (preferably about a. In addition, this p
Since an electrode will be formed in a part of the mold region 131 in a single process, the p-type region 131 will be expanded horizontally more than the region corresponding to the active layer of the FET, unlike the two examples above. It is extended.

Refer to Figure 13. Layer growth is started again, and (a) n-type impurities are added 10141014 (a) on the n-layer 32 where the p-type region 131 is formed.
Low concentration in-type Galiwam arsenic (n-GaAa) containing
One layer 33, which has a thickness of about 3 to 4 (μm) (
b) Aluminum gallium arsenide (aIGaAs) made high in resistance by doping with oxygen (02) or undoped aluminum gallium arsenide (Al'GaAs)
) and has a thickness of about 7゛(ri).
C) Made of n-type gallium arsenide (n-GaAs) containing about 10" (cm-3) of n-type impurities and having a thickness of 0.2" (cm-3).
A layer 36', which will become the active layer of the FET, having a thickness of about .mu.m) is sequentially formed.

Referring to FIG. 14, layer 36' is then selectively removed using conventional methods to form active layer 36 of the FIT.

See Figure 15. At this stage, the top layer of the PD section, which should originally be a p-layer, has become the high-resistance layer 35. Therefore, as a p-type impurity, for example, zinc (Zn) is selectively diffused into one layer of the FD. form 34. The depth of the first layer 34 is desirably equal to the thickness of the high resistance layer 35, that is, about 1 (μm), but it is unavoidable that it exceeds this to some extent.

Refer to Figures 16, 17, and 18. Next, a three-stage etching process is performed to remove the PD and FE parts.
The T part is separated from the T part, and a part of the p-type region under the FET and the -s 11 region of the n-layer of the FD are exposed and used as electrode formation regions, respectively. This etching process can be performed using either a wet etching method or a dry etching method, but bromomethanol (OHs
It is practical to use a wet etching method using a mixed solution of sulfuric acid (H2BO3), hydrogen peroxide (H20□), and water (H2O) as an etchant.

First, a groove-like opening extending 1% of the length of the insulating substrate 31 is formed in the area forming the boundary between the PD section and the FET section, and
The reason for this is that during operation, the p-type region 131 is completely electrically isolated from the p-type region 131 by applying a voltage that is opposite/semi-bias to the PN junction that is in contact with the p-type region 131. This is because it is necessary to make the potentials of the FD and FIT independent in order to ensure that the depletion layer spreads by applying it to the electrode provided at the electrode 131. Subsequently, a part of the p-type region 131 that does not correspond to the FIT operation layer 36, which is a characteristic structure of the present invention, is etched to form an electrode forming region material (FIG. 17).

Furthermore, the n-layer of the FD is exposed and the positive electrode formation region 45 of the FD is formed.
(FIG. 18) 0 Refer to FIG. 19 Finally, electrodes are formed in each predetermined region using a known method. First, gold/germanium (Au-Go)
/ FET source made of nickel (Ni) double layer,
A P-rain electrode 37 and a positive electrode 40 of the FD are formed simultaneously, and then an electrode for applying a desired potential to the negative electrode 41 of the FD made of gold-zinc (au-Zn) and the p-type region 131 is formed. 42 at the same time, and furthermore, aluminum (A
1) A dirt electrode 39 is formed, and then the substrate 31 is polished from the back side to a thickness of about 100 (μm) to complete the manufacturing process. There is an equivalent circuit 1 of the mold base conductor device. In the figure, an area 51 surrounded by a dashed line is an integrated type base conductor device, and 151 is an FD.
152 is a FET resistor, and 153 is a p-type region receiver, which is a characteristic configuration of the present invention.

Since a positive market voltage will be applied to the gate of the p-type region 152, if the potential of the p-type region 153 is set to a negative potential, for example, the ground potential as shown in the figure, the expansion of the depletion layer will be prevented. In addition, in the first to third examples, the magnetic pole formation is performed using a three-step etching process and three types of materials. It goes without saying that the order of the steps is not limited to that shown above. Furthermore, since the control element section such as PET is completely separated from the light receiving element section by the high resistance layer, it is not affected by the layer structure below it. Therefore, as a light-receiving element, in addition to the PIN type PD shown in this example, a Shirotki gate type PD, and a 7-no-single-shifted PD (
APD) etc. can also be used, so it is clear that this can be applied in an extremely wide range.

With the above structure, the generation of parasitic capacitance is effectively prevented in the integrated type main conductor device, so the response speed is much improved compared to the conventional technology. It is possible to realize great benefits, such as the ease of manufacturing process and effective contribution to improving the degree of integration. As mentioned above, in the prior art, 0.
It has been confirmed that the value of the parasitic capacitance, which was about 1 (pF), is reduced to about 1/4, with an effect of 0.02 (pF'), in the integrated optical semiconductor device according to the present invention. There is.

(7) As described in the detailed description of the invention, according to the present invention, F
D and Il'l! In an integrated base conductor in which tT voltage and current control elements are arranged in parallel and is generally planar and easy to process, the response characteristics are improved by preventing the generation of parasitic capacitance between the gate and the substrate. It is possible to provide an integrated optical semiconductor device.

[Brief explanation of drawings]

1 and 2 are cross-sectional views showing an example of the basic structure of an integrated optical semiconductor device in the prior art, and FIGS. 3 to 10 are cross-sectional views of an integrated optical semiconductor device according to a first embodiment of the present invention. It is a sectional view of the substrate after completion of the main 9′#i construction of the semiconductor device,
FIG. 11 is a sectional view of the completed integrated type base conductor device according to the second embodiment of the present invention, and FIG.
FIG. 9 is a cross-sectional view of the substrate after the volume manufacturing process of the integrated type base conductor device according to the third embodiment of the present invention is completed. Further, FIG. 20 is a circuit diagram showing an equivalent circuit of the integrated optical semiconductor device according to the embodiment of M3.
-G a As s 1', 31 is tangled GaAs
), ill, 111', 131...-p type region, 2
．． 12.32 ・-n N (n-GaAs), 3.
13.33-” layer (n--GaAs), 4.14.3
4 ・P layer (p evil impurity diffusion layer territory), 5.15.35
...High resistance layer (S-nee GaAs or oxygen-doped Ga
Aa), 16.36. -=F RT Layer serving as active layer (n-GaAs), 6.16.36-F If: T
Operating layer (n-GaAs), 7.17.37...Source electrode (Au-Ge/Ni), 8.18.3B-...Drain electrode (Au-Ge/Ni), 9.19.3
9...Gate electric & (Al), 10.20.40...
Positive electrode of PD (Au-Ge/Ni),], 0,21.
41 ・F D negative electrode (Au-Zn), 42...
P-type head area negative electrode (Au/Zn,), 22.45 ・F
D positive electrode formation region, 43 ・F groove-shaped opening for separating the D section and the FET section, 44 . . . electrode formation region of p-type head region, 51 . . . integrated optical semiconductor device, 151 .・
FD, 152...F, BT, 153...p type head area, 61.62...resistance, A, A...FET section, B,
B...FD section.

Claims (1)

[Claims] A semiconductor element electrically connected to the optical conductor element via a high-resistance semiconductor layer is disposed in a part of the semiconductor laminate constituting the optical conductor element, and the semiconductor laminate corresponds to the semiconductor element part. A semiconductor integrated circuit device, in which one of the semiconductor layers constituting the semiconductor layer is provided with a region having a conductivity type different from that of the semiconductor layer.