JPH0496375A - Semiconductor device - Google Patents

Abstract

PURPOSE:To make a semiconductor device proper to the formation of different kinds of semiconductor elements such as an HET and a MESFET on the same substrate, and to improve the controllability of threshold voltage by forming a first conductivity type semiconductor layer onto a semiconductor substrate, forming an ohmic-contacted ohmic electrode at the stepped section of the semiconductor layer, shaping a first conductivity type semiconductor layer onto the first conductivity type semiconductor layer through an intrinsic type semiconductor layer, forming a Schottky-joined Schottky electrode at a center on the latter semiconductor layer and forming an ohmic electrode onto the latter semiconductor layer so as to further hold the Schottky electrode. CONSTITUTION:An HET 30a on the left side is a vertical type device. An ohmic electrode 32a is used as a collector electrode, a Schottky electrode 35a is employed as an emitter electrode, and ohmic electrodes 36a and 36b are connected in common and used as base electrodes. A MESFET 30b on the light side is a lateral type device. A Schottky electrode 35b is employed as a gate electrode, and ohmic electrodes 36b and 36b are used as a source electrode and a drain electrode respectively. An N-GaAs layer 34b is used as an active layer.

Description

Detailed Description of the Invention [Summary] Regarding a semiconductor device, particularly a semiconductor device in which a high-speed semiconductor element using hot carriers and a semiconductor element with a large current gain can be formed on the same substrate, for example, HET and MESFE
It is suitable for forming various types of semiconductor elements such as T on the same substrate, has good controllability of threshold voltage, and aims to create a semiconductor device that does not increase the overall thickness. a semiconductor substrate, a first first conductivity type semiconductor layer formed on the semiconductor substrate, an ohmic electrode formed on the first first conductivity type semiconductor layer, and the first first conductivity type semiconductor layer. an intrinsic semiconductor layer formed on the layer, a second first conductivity type semiconductor layer formed on the intrinsic semiconductor layer, and a second first conductivity type semiconductor layer formed on the second first conductivity type semiconductor layer. The semiconductor device is configured to include a Schottky electrode and a plurality of ohmic electrodes formed on the second first conductivity type semiconductor layer so as to sandwich the Schottky electrode.

[Industrial Field of Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device in which a high-speed semiconductor element using a photo-gamma photocarrier and a semiconductor element with a large current gain can be formed on the same substrate.

[Prior Art] A hot electron transistor (HET) is a device that utilizes pallitic conduction by injecting high-energy electrons (hot electrons) into a base layer, and has attracted attention as a device capable of realizing ultrahigh-speed operation. There is.

However, although HET operates at high speed, its current gain is small, so it is often used in combination with MESFET, which has a large current gain.

FIG. 3 shows a conventional example in which a HET and a MESFET are formed on the same substrate.

HF and T are formed in the left region on the semi-insulating GaAs substrate 50, and MESFET is formed in the right region.

The HET region on the semi-insulating GaAs substrate 50 has approximately 300
n-G with a thickness of nm and an impurity concentration of 1×1011018C
An aAS collector layer 51 is formed and is made of n-GaAs.
A u that is in ohmic contact with the stepped portion of the collector layer 51
A collector electrode 52 of Ge/Au is formed. On the n-GaAs collector layer 51, about 200n
Through the m-thick 1-AIGaAs=r rectangle barrier layer 53, the impurity concentration is lXl0 cm with a thickness of about 3Q nm.
An n-GaAs base layer 54 is formed. n
- A base electrode 55 of Au Ge/Au that is in ohmic contact is provided at the stepped portion of the GaAs base layer 54 . About 10 nm thick on the n-GaAs base layer 54
An n-GaAs emitter layer 57 with a thickness of about 200 nm and an impurity concentration of 1X1018-m3 is formed through a 1-A I GaAs emitter barrier layer 56 with a thickness of 1-A I GaAs. n
- On the GaAs emitter layer 57, an AuGe/Au emitter electrode 58 is provided in ohmic contact.

On the other hand, an n-GaAs active layer 59 is formed in the MESPET region on the semi-insulating GaAs substrate 50. n-G
A recess is formed in the center of the aAs active layer 59, and a TiPtAu gate electrode 6 with a Schottky junction is formed on the bottom of the recess.
On both sides of the gate electrode 60, a source electrode 61 and a drain electrode 62 of AuGe/Au are formed in ohmic contact.

[Problem to be solved by the invention] However, in the conventional example shown in FIG.
At T, the m-resistance increases significantly, so the same semi-insulating GaA
There has been a problem in that it is difficult to efficiently form pixel elements on the s-substrate 50.

Furthermore, in the conventional example shown in FIG. 3, the central part of the n-GaAs active layer 59 epitaxially grown in the MESFET region is etched to form a recess for forming the gate electrode 60. layer 5
There was a problem in that the thickness of the central concave portion 9 varied, making it difficult to control the threshold voltage to a desired value. moreover,
In the conventional example shown in FIG. 3, the overall thickness in the HETW4 region is as thick as 1 μm or more, which has the problem of lowering the manufacturing yield.

An object of the present invention is to provide a semiconductor device that is suitable for forming various types of semiconductor devices such as HET and MBSFET on the same substrate, has good controllability of threshold voltage, and does not increase the overall thickness. The goal is to provide equipment.

[Means to solve the problem] The principle of the present invention will be explained using FIG.

The present invention realizes a transistor using hot carriers, such as a HET'PHHT (hot hole transistor), and a transistor with a large current gain, such as a MESFET, using the same basic structure.

A first conductive type semiconductor layer 11 is formed on a semiconductor substrate 10 . An ohmic electrode 12 is formed on the step portion of the first conductive type semiconductor layer 11 in ohmic contact. 1st
A first conductive type semiconductor layer 14 is formed on the conductive type semiconductor layer 11 with an intrinsic type semiconductor layer 13 interposed therebetween. A Schottky junction is formed at the center of the first conductivity type semiconductor layer 14 [! 15 is formed, and an ohmic electrode t1=16.17 is further formed on the first conductive type semiconductor layer 14 so as to sandwich the Schottky electrode 15 therebetween.

To configure HET or HHT with this basic structure,
The Schottky electrode 15 is used as an emitter electrode, the ohmic electrodes 16 and 17 are used as base electrodes, and the ohmic electrode 12
is the collector electrode. HET or HHT is realized in which the first conductive type semiconductor layer 11 becomes a collector layer, the intrinsic type semiconductor layer 12 serves as a collector barrier layer, and the first conductive type semiconductor layer 14 serves as a base layer.

To configure a MESFET with this basic structure, the Schottky pole 15 is the gate electrode, and the ohmic electrode 1 is the gate electrode.
6.17 are the source electrode and drain electrode, respectively. A MESFET is realized in which the ohmic electrode 12 is not used and the first conductivity type semiconductor layer 14 is the active layer. The intrinsic semiconductor layer 13 functions as an element isolation insulating layer.

[Operation] As described above, according to the present invention, HE
High-speed operation transistors such as T and HHT and ME
A transistor with a large current gain, such as an SFET, can be realized.

[Example] A semiconductor device according to an example of the present invention will be described with reference to FIG. The figure (a) is a cross-sectional view of the semiconductor device, and the figure (b) is a cross-sectional view of the semiconductor device.
is its plan view.

H with the same basic structure on the left and right sides of the semi-insulating GaAs substrate 20
ET30a and MESFET30b are formed.

The basic structures of the HET 30a and MESFET 30b will be explained.

lXl with a thickness of about 300 nm on a semi-insulating GaAs substrate 20.
n-GaAs layer 31 with an impurity concentration of 0 cm
a, 31b are formed. n GaAs layers 31a, 31
A u G e / A u ohmic electrodes 32 a and 32 b are formed at the step portion b.

On the n-GaAs layers 31a and 31b, about 200
n with an impurity concentration of I×10 18 cm −3 and a thickness of about 1100 nm through the 1-AI GaAs layers 33 a and 33 b with a thickness of 1 nm.
-GaAs layers 34a and 34b are formed. n-G
In the center on the aAs layers 34a and 34b, (Cr)/
Schottky electrodes 35a, 35b of Pt/Au
is formed. Ohmic electrodes 36a, 37a, 36b, 37b are formed on the n-GaAs layers 34a, 34b so as to sandwich Schottky electrodes 35a, 35b therebetween. Ohmic electricity [! 36a, 37a, 36b
, 37b is AuGe, /Au or (Cr)/
3 after depositing Pt/Ge/Au etc.
It is formed by alloying at about 50°C.

The HET 30a on the left is a vertical device.

The ohmic electrode 32a is used as a collector electrode, the Schottky electrode 35a is used as an emitter electrode, and the ohmic electrode 4m!
36a and 36b are commonly connected to form a base electrode.

The n-GaAs layer 31a becomes a collector layer, and the L-AIG
The aAs eyebrow 33a becomes a collector barrier layer, and the n-GaA
The s layer 34a becomes a base layer. Since a depletion layer of about 30 to 50 nm is formed in the base layer 34a under the emitter electrode 35a, the effective width of the base layer becomes very thin.

On the other hand, since the thickness of the base layer 34a under the base electrodes 36a and 36b is about 1100 nm, a low base resistance can be maintained.

The MBSFET 30b on the right is a horizontal device. The Schottky electrode 35b is used as a gate electrode, and the ohmic electrodes 36b and 36b are used as a source electrode and a drain electrode, respectively. The n-GaAs layer 34b becomes an active layer. Note that the 1-AIGaAs layer 33b serves as an element isolation insulating layer, and the n-GaAs layer 31b and ohmic electrode 32b are not used.

In this way, according to this embodiment, the HET, which is a vertical device, and the MES, which is a horizontal device, have the same basic structure.
FET can be realized. Furthermore, since the overall thickness of this basic structure is approximately 0.6 μm, the manufacturing yield will not be reduced.

The HET according to this embodiment has an emitter conductance ge
is large and the base travel time of hot electrons is short, making it an ultra-high-speed device that can operate at 1 psec or less.

In addition, the MESFET according to this embodiment has extremely good controllability of the threshold voltage, and since almost no current flows through the gate electrode, it becomes a high-gain device with a stable threshold voltage and an extremely large current gain. Note that the MESFE according to this example
Since T can be used as a so-called active load, it is very useful as a load element of HET.

Semiconductor device according to another embodiment of the present invention! will be explained using FIG. The figure (a) is a cross-sectional view of the semiconductor device, and the figure (b) is a cross-sectional view of the semiconductor device.
) is its plan view. Components that are the same as those in FIG. 2 are given the same reference numerals to omit or simplify the explanation.

This example uses HHT40a and ME using holes as carriers.
The SFET 40b is formed on the same substrate L; shaded.

1x1 with a thickness of about 300 nm on a semi-insulating GaAs substrate 20
p-GaAs layer 41 with an impurity concentration of 0 cm
a, 41b are formed. p-G, aAs layer 41
Ohmic electrodes 32a and 32b of A u Z n /A u are formed at the step portions a and 41b.

1-AIGaAs is formed on the p-GaAs layers 41a and 4ib.
p-G with an impurity concentration of 1x10 cm with a thickness of about 1100 nm through the layers 33a and 33b.
AAs layers 44a and 44b are formed. p-cra
Schottky electrodes 35a, 35b of AI<Au) are formed at the center of the As layers 44a, 44b. p-
A Schottky electrode 35 is provided on the GaAs layers 44a and 44b.
AuZn/Au ohmic electrodes 36a, 37a, 36b, and 37b are formed to sandwich the electrodes a and 35b.

In the left HHT 40a, the ohmic electrode 32a is used as a collector electrode, the Schottky electrode 35a is used as an emitter electrode, and the ohmic electrodes 36a and 36b are used as base electrodes. The p-GaAs layer 41a becomes a collector layer, and 1-A
The IGaAs layer 33a becomes a collector barrier layer, and the p-G
The aAs layer 44a becomes a base layer.

In the MESFET 40b on the right, the Schottky electrode 35
b is a gate electrode, and ohmic electrodes 36b and 37b are a source electrode and a drain electrode, respectively. p-GaA
The s layer 44b becomes an active layer.

In this way, according to this embodiment, an HHT using high-energy hot holes and a MESFET using holes as carriers are constructed.
can be realized on the same board.

The present invention is not limited to the above-mentioned embodiments, and various modifications are possible.

For example, the present invention can be applied to semiconductor devices using semiconductor materials other than those in the above embodiments.

[Effect of the invention] As described above, according to the present invention, HE
High-speed operation transistors such as T and HHT and ME
A transistor with a large current gain, such as an SFET, can be realized.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the principle of the present invention, FIG. 2 is a diagram showing a semiconductor device according to an embodiment of the present invention, FIG. 3 is a diagram showing a semiconductor device according to another embodiment of the present invention, and FIG. 4 is a diagram showing a HET. FIG. 3 is a diagram showing a conventional example in which a MBSFET and a MBSFET are formed on the same substrate. In the figure, 10... Semiconductor substrate 11... First conductivity type semiconductor layer 12... Ohmic electrode 13... Intrinsic type semiconductor layer 14... First
Conductive semiconductor layer 15... Schottky electrode 16.17... Ohmic electrode 20... Semi-insulating GaAs substrate 30a/NET 31 a--n-GaAs layer (collector layer) 32a/
・・Ohmic electrode (collector electrode) 33 a-i −
AlGaAs layer (collector barrier layer) 34a-n, -GaAs layer (base layer) 35a... Schottky electrode (emitter electrode) 36a, 37a...
Ohmic electrode (base electrode) 30b...MESFE
T3lb---n-GaAs layer 32b...Ohmic electrode 33b...-i -A IGaAs layer (element isolation insulating layer) 34b...n-GaAs layer (active layer) 35b...Schottky electrode (gate electrode) 36b...ohmic electrode (source electrode) 37b...
...Ohmic electrode (drain electrode) 40a--HH
T 41a--p-GaAs layer (collector layer) 44a-=
p-GaAs layer (base layer) 40b...MESFET 4 l b=-p-GaAs layer 44 b---p-GaAs layer (active layer) 5
0...Semi-gloss #! l-type GaAs substrate 51...n-G
aAs collector layer 52...collector electrode 53...i -AIGaAs collector barrier layer 54---n-GaAs base layer 55...
...Base electrode 56...1-AIGaAs emitter barrier layer 57...
・N-GaAs emitter layer 58...Emitter electrode 59---N-GaAs active layer 60...Gate electrode 61...Source electrode 62...Drain electrode Applicant: Fujitsu Limited Company agent Patent attorney Yoshihito Kitano 10--Intrinsic type wood board 1 Toe mirror 1 conductive type meridian 12--10,000-Mick electric wire 13---Intrinsic type cow conductor 9q grave 14-- 1st
Conductive type 1,000 yen 1 15---Yot key electric 1 hand 16.17--Omitsuku electric wire failure Japan-Yoko's source diagram Fig. 1 40a-HH 0b ESFET 6 in the embodiment of the present invention ．． Fig. 4 shows the whistle formed on the board of the present invention.

Claims (1)

[Scope of Claims] 1. a semiconductor substrate; a first first conductivity type semiconductor layer formed on the semiconductor substrate; an ohmic electrode formed on the first first conductivity type semiconductor layer; an intrinsic type semiconductor layer formed on the first first conductivity type semiconductor layer; a second first conductivity type semiconductor layer formed on the intrinsic type semiconductor layer; and the second first conductivity type semiconductor layer. a Schottky electrode formed on a type semiconductor layer; and a plurality of ohmic electrodes formed on the second first conductivity type semiconductor layer so as to sandwich the Schottky electrode. Characteristic semiconductor devices. 2. The semiconductor device according to claim 1, wherein the first first conductivity type semiconductor layer is a collector layer, the ohmic electrode on the first first conductivity type semiconductor layer is a collector electrode, and the intrinsic type semiconductor layer is a collector barrier layer, the second first conductivity type semiconductor layer is a base layer, the Schottky electrode on the second first conductivity type semiconductor layer is an emitter electrode, and the second first conductivity type semiconductor layer is an emitter electrode. a first semiconductor element in which a plurality of ohmic electrodes on a first conductivity type semiconductor layer are base electrodes; the intrinsic type semiconductor layer is an element isolation insulating layer; and the second first conductivity type semiconductor layer is an active layer, a Schottky electrode on the second first conductivity type semiconductor layer is a gate electrode, one of the plurality of ohmic electrodes on the second first conductivity type semiconductor layer is a source electrode, and the other is an active layer; and a second semiconductor element whose drain electrode is a drain electrode. 3. The semiconductor device according to claim 1 or 2, wherein the first first conductivity type semiconductor layer is an n-type semiconductor layer, and the second first conductivity type semiconductor layer is an n-type semiconductor layer. Characteristic semiconductor devices. 4. The semiconductor device according to claim 1 or 2, wherein the first semiconductor layer of the first conductivity type is a p-type semiconductor layer, and the second semiconductor layer of the first conductivity type is a p-type semiconductor layer. Characteristic semiconductor devices.