JPS59178759A - マルチチツプパツケ−ジ - Google Patents

マルチチツプパツケ−ジ

Info

Publication number
JPS59178759A
JPS59178759A JP58052944A JP5294483A JPS59178759A JP S59178759 A JPS59178759 A JP S59178759A JP 58052944 A JP58052944 A JP 58052944A JP 5294483 A JP5294483 A JP 5294483A JP S59178759 A JPS59178759 A JP S59178759A
Authority
JP
Japan
Prior art keywords
wiring
wiring layer
layer
chip
alumina ceramic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58052944A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6159534B2 (cs
Inventor
Toshihiko Watari
渡里　俊彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP58052944A priority Critical patent/JPS59178759A/ja
Priority to DE8484103423T priority patent/DE3479463D1/de
Priority to EP84103423A priority patent/EP0120500B1/en
Priority to CA000450758A priority patent/CA1229155A/en
Publication of JPS59178759A publication Critical patent/JPS59178759A/ja
Priority to US06/758,951 priority patent/US4652970A/en
Priority to US06/896,348 priority patent/US4744007A/en
Publication of JPS6159534B2 publication Critical patent/JPS6159534B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
JP58052944A 1983-03-29 1983-03-29 マルチチツプパツケ−ジ Granted JPS59178759A (ja)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP58052944A JPS59178759A (ja) 1983-03-29 1983-03-29 マルチチツプパツケ−ジ
DE8484103423T DE3479463D1 (en) 1983-03-29 1984-03-28 High density lsi package for logic circuits
EP84103423A EP0120500B1 (en) 1983-03-29 1984-03-28 High density lsi package for logic circuits
CA000450758A CA1229155A (en) 1983-03-29 1984-03-28 High density lsi package for logic circuits
US06/758,951 US4652970A (en) 1983-03-29 1985-07-25 High density LSI package for logic circuits
US06/896,348 US4744007A (en) 1983-03-29 1986-08-14 High density LSI package for logic circuits

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58052944A JPS59178759A (ja) 1983-03-29 1983-03-29 マルチチツプパツケ−ジ

Publications (2)

Publication Number Publication Date
JPS59178759A true JPS59178759A (ja) 1984-10-11
JPS6159534B2 JPS6159534B2 (cs) 1986-12-17

Family

ID=12928975

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58052944A Granted JPS59178759A (ja) 1983-03-29 1983-03-29 マルチチツプパツケ−ジ

Country Status (1)

Country Link
JP (1) JPS59178759A (cs)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6269648A (ja) * 1985-09-24 1987-03-30 Nec Corp 多層配線基板
JPH0525497U (ja) * 1991-09-06 1993-04-02 株式会社三協精機製作所 小型発音装置
JPH06295977A (ja) * 1992-10-02 1994-10-21 Internatl Business Mach Corp <Ibm> 電子パッケージにおける電力及び信号の配線

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6269648A (ja) * 1985-09-24 1987-03-30 Nec Corp 多層配線基板
JPH0525497U (ja) * 1991-09-06 1993-04-02 株式会社三協精機製作所 小型発音装置
JPH06295977A (ja) * 1992-10-02 1994-10-21 Internatl Business Mach Corp <Ibm> 電子パッケージにおける電力及び信号の配線

Also Published As

Publication number Publication date
JPS6159534B2 (cs) 1986-12-17

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