JPS59178759A - Multi-chip package - Google Patents

Abstract

PURPOSE:To obtain a package of high speed for signal propagation and to which fine wiring is enabled by a method wherein a multilayer wiring layer, a power source wiring layer, and a ground wiring layer parallel with each other are buried while being insulated with organic polymer material in an alumina ceramic substrate provided with a plurality of pins to the back surface, and a plurality of leadless chip carriers are mounted on the surface of the substrate, which are connected to a fixed wiring layer. CONSTITUTION:While being insulated with a polyimide resin layer, the multilayer wiring layer 2, power source wiring layers 13, and ground wiring layer are buried in parallel with each other in the alumina ceramic substrate 1 provided with a plurality of input-output terminal pins 11 to the lower surface. Next, a plurality of leadless chip carriers 3 consistion of substrates 31, IC chips 32, terminals 34, and covers 33 are mounted on the surface of the substrate 1, which carriers are connected to fixed wiring layer via through hole wirings 12. Thus, a multi terminal multi chip package of high speed, high density, and high heat dissipating property is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical field to which the invention pertains The present invention relates to a high-density LSI (Large 5cale
In particular, with regard to integrated (Inte-gration) packages, we have made it possible to mount multiple IC chips at high density, increased the signal propagation speed on connection wiring to achieve high performance, and also made the heat generated by LSI chips extremely efficient. The present invention relates to a multi-chip LSI package that can be used in a wide range of 7iQ.

Conventional technology Conventionally, this f11+ multi-chip package.

Proceedings 1981 31th
Electronic Components Con
fevence’s “ManufacturingTe”
chnology of )Iigh C1rcuD
strengthMulti-Layer 5ubst
Page 337 of the paper entitled “Rates” F
As indicated by lg, lO.

An alumina ceramic substrate is used as the base plate of the multi-step package.On the surface of this substrate, multilayer signal wiring layers and source bus wiring are formed and an IC chip is mounted.On the other hand, the back side of the alumina ceramic substrate is , which has a structure in which a heat sink is bonded to dissipate the heat generated by the IC chip.

In the case of such a multilayer wiring board of ('I4 construction), there are the following drawbacks.

(1) For the insulating layer of the multilayer wiring layer, a 1ζ glass/ceramic inorganic paste is printed and fired. The specific current visit rate εr of inorganic insulation paste is generally 8 to 9.
In order to take the value of , the signal propagation delay per unit length of the signal wiring formed on this insulating layer (where C is the speed of light)
3.3 X I Q 10Cm/lX'c )td=9
ns/mf is calculated as 4 for common coaxial cable.
The signal propagation speed is approximately twice as slow as ns/m.

(2) Since the wiring layer is made of gold paste and the conductor wiring is formed by screen printing,
The wiring width and wiring pitch are 50 μm (microns) and 10
The limit is 0 μm, and it is not suitable for finer wiring.

The heat generated by the +311c test is radiated to the heat sink on the back side via the alumina ceramic substrate. Generally, alumina ceramic substrates are 2mm thick to provide strength.
Therefore, heat from the IC chip is blocked by the thick alumina substrate and cannot be efficiently radiated to the heat sink.

(4) Provide input/output DNA molecules in the multi-chip package. In some cases (not detailed in this example), it cannot be formed on the outer surface of an alumina ceramic substrate. This is because a heat sink is connected to the entire back surface of the alumina ceramic substrate. Therefore, input/output terminals must be formed on the surface of the alumina ceramic substrate, that is, the surface on which wiring and IC chips are mounted. There is a drawback that terminals cannot be taken out from the entire surface of the substrate, and therefore a large number of input/output terminals cannot be formed.

OBJECTS OF THE INVENTION It is an object of the present invention to solve the drawbacks of the conventional embodiments and to enable a high signal propagation speed and finer wiring. An object of the present invention is to provide a multi-chip package that has high heat dissipation efficiency and can form a large number of input/output terminals.

Structure of the Invention The multi-chip package according to the present invention includes an alumina ceramic substrate that includes power supply and ground wiring layers inside and has input/output pins arranged in a grid on the back surface.

A plurality of thin film wiring layers formed on the surface of this alumina ceramic substrate.

In a plurality of insulating layers made of an organic polymer material that insulate between the plurality of wiring layers, and in the uppermost layer of the thin film wiring layer,
'I'A B' has multiple grid-shaped terminal pads on the back side and is connected face down inside.
It includes a reedless step carrier having a gold rice grain cover with good thermal conductivity to which an IC chip and an mJ TABIC chip are adhered.

Embodiments of the Invention Next, the present invention will be described in detail with reference to the drawings.

Referring to FIG. 1, one embodiment of the present invention shows an alumina ceramic substrate 1. A multilayer wiring layer 2 made of an organic polymer material and a plurality of lead-less step carriers 3 are formed on the surface of this base 81. On the outer surface of the alumina ceramic substrate 1, a plurality of input/output terminal pins 11 are bonded to the back surface of the alumina ceramic substrate 1 by a well-known brazing technique.

The through-hole wiring 12 is a wiring that penetrates the inside of the substrate l from the back surface to the front surface and connects the input/output terminal 11 to the wiring formed on the front surface in an airtight manner.

The power supply wiring layer +3 and the ground wiring layer 14 formed inside the substrate 1 are connected to the input/output pins 11 designated as input/output pins 11, pins, and ground, respectively, and are connected to one surface of the IC chip. It is used to connect the box, source and ground potential to the box. As is clear from the above description, the multi-chip package according to the present invention includes an alumina ceramic substrate l having a plurality of input/output pins 11 on the back surface, a multilayer wiring layer 2 made of an organic polymer material formed on the surface, and the multilayer It is composed of a plurality of (17ri) leadless step carriers 3 connected and bonded to the surface of the wiring layer.

Among the input/output pins 11 on the outer surface, those used as signal bins are connected to the surface of the substrate 1 by through-hole wiring 12, and are further connected to the wiring in the multilayer wiring layer 2.

On the other hand, among the input/output pins 11, those used as a power supply and a ground are a power supply wiring layer 13 and a ground wiring layer 14 inside the ceramic substrate 1, respectively.
is connected to.

The signal wiring in the multilayer wiring layer 2 connects any one of the chip carrier terminals 34 of the lead-less step carrier 3 and any one of the signal terminals of the lead-less step carrier 3 and any of the input/output pins 11. It is for the purpose of The lead-less step carrier 3 has a chip carrier substrate 31. IC tip 32. Chip carrier cover 3
3 and full preparation.

The IC chip 32 is lead-bonded to the chip carrier substrate 31 in a face-down state, and is further die-potted/deinked to the chip carrier cover 33. The chip carrier cover 33 is made of a metal with good thermal conductivity, such as an iron-nickel alloy or a cobalt-nickel alloy, so that all the heat generated by the IC chip 32 can be transmitted to the cover surface extremely efficiently. . Therefore, a heat sink may be attached to the surface of the chip carrier cover 33, or a heat exchanger in which cooling liquid circulates may be attached, making it possible to dissipate heat extremely efficiently. Regarding the heat dissipation mechanism that contacts or is connected to the chip carrier cover 33.

It is not described in detail in FIG. 1, which is irrelevant to the gist of the present invention.

As explained above, the following excellent features of the 91st order can be realized by one multi-chip package according to the present invention as shown in FIG. That is, (1) an organic polymer insulating material, specifically polyimide, is used for the insulating layer of the multilayer wiring layer. The specific frost of this material,
The rate ε is as low as 3.5, so the signal propagation time of the signal wiring is as described above, Ld=77r/C and td=5.7.
ns/m, which is a 16 times improvement in propagation speed compared to 9 ns/m in the conventional example described above.

(2) The application source 1i necessary for forming the non-wire layer of polyimide has a maximum temperature of 400°C. Therefore, if the conductor wiring is a thin film wiring, it is possible to form a thinner wiring than a wiring using gold paste, such as copper plating on a chromium vapor deposited film and further formation of a chromium vapor deposited film. Therefore, the wiring width and wiring pitch are 20 μm wide compared to the limit of 50 μm width and 100 μm pitch for thick film wiring using gold paste.

It becomes possible to create fine wiring up to a pitch of about 50 μm, making it possible to improve the wiring density by about twice.

The heat generated by the +311c Teff 320 is radiated to the upper part of the board via the chip carrier cover 33 made of metal with good thermal conductivity. Chip carrier cover trap 1For example, when using cobalt-nickel alloy, the thickness of the cover should be set to 0.
．． Since sufficient strength can be obtained even if the thickness is reduced to about 5 cylinders, the total thermal resistance up to the heat sink can be improved by about 4 times compared to the alumina substrate of the conventional example.

This is because, compared to the conventional alumina substrate that requires a plate thickness of 2 m, the chip carrier cover 33 of the present invention may have a thickness of 0.5 rnM, and the thermal conductivity of the alumina substrate and cobalt-nickel alloy is 0.5 rnM. This is because the case #1 is equal.

(41 output pins 11' can be provided on the entire back surface of the alumina ceramic substrate 1. Therefore, compared to the case where they are arranged on the outer periphery of the surface of the board as in the conventional embodiment, the area where input/output terminals can be formed is reduced. It has the advantage of being able to take much more.

Figure 2 shows a multi-chip package according to the present invention.
The IC chip 32 is lead-boarded/gained face-down on the chip carrier board 31 inside the lead-less step carrier 32 and the chip carrier cover 33
is die-bonded to the inner surface. Furthermore, the leadless step carrier 3 is connected to the chip carrier terminal 34 on the surface of the multilayer #i1 layer 20 by the multilayer #i1 layer 20.
Connected to internal wiring inside. Furthermore, the input/output bins 11 on the front side of the alumina ceramic substrate 1 are connected to wiring in the multilayer wiring layer 2 through through-hole wiring 12.

Referring to FIG. 3, inside the alumina ceramic substrate l there is a power wiring layer 13 and a ground wiring layer 1.
4 as well as through-hole wiring 12 that connects between the input/output bin 11 on the back surface and the multilayer wiring layer. IEE has shown that such alumina ceramic substrates can be formed by the well-known multilayer lamination method of raw alumina sheets.
E'l'rhnsact 1oz on Compo
nents, ) Iybrid.

and Manufacturing Technology
ogy, vol.

C) IM'l'-3, No, l, March
Page 1980089 "PnOCE88" section and 9
Shown in 1-page FIG. 3. Multilayer wiring IN
2 as mentioned above.

A thin film formed on an insulating film 21 made of an organic polymer material
A first wiring layer consisting of a wiring 24 made of a HiX conductor and a plurality of guia holes 27 for connection with the through-hole wiring in the lower layer, and a wiring 25 made of a thin film conductor and the wiring 24 similarly formed on the insulating film 22. A second wire having a plurality of via holes 28 for connecting the wire 25 and the wiring 25
, a plurality of terminal pads 26 for connecting the chip carrier terminals 34 of the leadless chip carrier 3 on the insulating film 23 and the surface thereof, and a guia hole 2 for connecting the terminal pads 26 and the wiring 25.
9 and a third wiring layer. Therefore, the TEF carrier terminals 34 of any leadless chip carrier 3 can be arbitrarily connected to each other, and any chip carrier terminal 34 and any input/output bin 11 can be connected to each other by the multilayer wiring N42.

Referring to FIG. 4, the IC chip 32 has a well-known TAI3 (Tape Auto
ted Bonding) type glue 37 is used as an inner lead bonder.

Therefore, the assembly of the lead-less step carrier shown in FIG. After adjusting the position of the outer lead bonding pad 38, all the leads are bonded at once. In this state, the IC
All the terminal bumps 311 of the chip 32 have an outer lead bonding pad 381 surface layout of 1M39. It is electrically connected to all of the chip carrier terminals 34 via the chip carrier through-hole wiring 310.

The chip carrier cover 33 is coated with a die bonding adhesive 35. A substrate adhesive 36 is applied, and the IC chip 32 is placed over the chip carrier substrate 31 to which the IC chip 32 is face-down bonded.
contact with the die.

Thereafter, heat necessary for solidifying the adhesives 35 and 36 is applied from the outside to complete the bonding. In this way, by using a leadless chip carrier that is small and has extremely good heat dissipation efficiency, the aforementioned high-density, high-performance multi-chip package can be constructed.

For details of the leadless chip carrier of the embodiment shown in FIG.
Please refer to Item No. 19 (■).

Effects of the Invention The multi-chip package according to the present invention has a ceramic substrate with a power output on the entire back surface, high-speed multi-layer wiring using an organic polymer material on the surface, and heat dissipation that allows direct die bonding of IC chips. By constructing a leadless step carrier having a cover with extremely good characteristics, it is possible to produce a multi-chip package with high speed, high density, high heat dissipation, and multiple terminals.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a simple embodiment of the present invention, FIG. 2 is a diagram showing a diagonal cross section of the multi-chip package shown in FIG. 1, and FIG. 3 is a diagram showing the substrate and multilayer structure shown in FIG. 1. FIG. 4 is a detailed cross-sectional view of the leadless chip carrier shown in FIG. 1. In Figures 1 to 4, 1...Alumina ceramic substrate Sll...Input/output pin, 12...Through hole wiring, 13...
・・Power supply wiring layer 14...Dara/do wiring layer,
2... Multilayer wiring layer, 21... First layer heavy machinery polymer insulation film, 22... Second layer polygonal molecular insulation, 23... ...Third layer heavy machinery polymer insulation film, 2
4...First layer thin film wiring, 25...Second layer
Thin layer 1j〆Wiring, 26...Surface terminal pad, 2
7...No. Lj@Via Hall, 28...
・Second floor Via Hall. 29...3rd floor via hall, 3...
Leadless step carrier, 31...Chip carrier substrate, 32...IC chip,
33...Chip carrier cover, 34...
...Tep carrier terminal. Agent Patent Attorney Uchihara □U. ll Written amendment to the porridge procedure (voluntary) 1. Pa...Showa era 1 yen 1 month ['' Commissioner of the Patent Office 1, Indication of the case 1981 Patent Application No. 529
44 No. 2, Title of the invention: Multi-chip package 3,
Relationship with the case of the person making the amendment Applicant: Shiba 1, Minato-ku, Tokyo
1.1° [133 sounds 1';) (423) NEC Corporation representative Tadahiro Sekimoto 4, agent 17 Shiba, Minato-ku, Tobu, 108. I' l-137 sound 85; Sumitomo-U L11 Building'"* 'R$l+k
A k +11'J yo (6591) Patent attorney 1-
Atsushi Uchi 〒 Telephone Tokyo (03) 456-3111 (main representative) ＼ (Contact information r+* Denki Co., Ltd. Patent Department) 5. Subject of amendment (1) Drawings (2) Scope of claims in the specification ( 3) Detailed explanation of the invention in the specification 6 Contents of amendment (1) Figure 1 of the drawings will be replaced with a new drawing. (2) Attachment page (3) Fill out the column for detailed explanation of the invention in the specification as follows.
I'll correct it. Note] The entry "33" on page 4, line 5 will be corrected to "30". 2. The entry “9” in line 6 of the same page will be corrected to “lO”. 3. Correct the statement “wo” in the third line of page 8 to “ni”. 4. The entry "metal" in line 6 of the same page will be corrected to "material." 5. The statement "alloy" in the 6th line of the same page has been corrected to "alloy or Berria porcelain." 6. r 6.2 J for the entry “57” on page 9, line 18
I will correct it. 7. The entry "9" in the same item on the same page will be corrected to "10". 8 The entry "Na-kin" in the fourth row of page 10 is corrected to "Na-kin". 9. In line 11 of the same page, Ftl, + "metal" is corrected to "material." 10 Change “de” to “de” in line 9 of page 11
I will correct it. Agent Patent Attorney Susumu Uchihara Multiple input/output bins set up in a grid pattern on the back of the patent claims. Multiple power and ground wiring layers internally. and an alumina ceramic substrate including a plurality of through-hole wirings for conductively connecting each of the human output pins on the back side from the front side to the front side, and a plurality of thin film conductor wirings on the surface of the alumina ceramic substrate. , an insulating layer made of an organic polymer material for insulating each other between the thin film conductor wiring layers, a plurality of guia holes for electrically connecting the wiring layers inside the insulation 1@,
and a plurality of surface terminal pads for connecting the leadless chip carrier formed in the top layer, and each of the through-hole wiring in the alumina ceramic substrate and the surface terminal pads are formed by connecting the thin film conductor wiring 1 and the via hole. a multilayer wiring layer having a structure such that each of the multilayer wiring layers can be connected to each other and arbitrarily;
TA, B IC chip mounted face down, chip carrier substrate with multiple chip carriers yjM+, and chip carrier with IC chip die directly bonded using material with good thermal conductivity. A multi-chip package comprising a plurality of glue-dressed chip carriers in which each of the wiring I-front terminal pads and each of the chip carrier terminals on the surface between the tip carrier substrate are connected by breaking the cover. //Me/Figure

Claims (1)

[Claims] A plurality of input/output bins arranged in a grid pattern on the back surface. Multiple power and ground wiring layers internally. and an alumina ceramic substrate including a plurality of through-hole wirings for electrically connecting each of the input/output bins on the back surface from the back surface to the front surface. On the surface of the alumina ceramic substrate. a plurality of thin film conductor wiring layers; an insulating layer made of an organic polymer material for insulating each other between the thin film conductor wiring layers;
It has a plurality of via holes for conductively connecting the wiring layers inside the insulating layer and a plurality of surface terminal pads for connecting a leadless step carrier formed in the uppermost layer, and the thin 11-layer conductor Wiring IN
and a multilayer wiring layer having a structure in which each of the through-hole wirings in the alumina ceramic substrate and each of the surface terminal holes can be connected to each other and arbitrarily by means of a Guia hole. The chip carrier substrate is arranged on the surface of the multilayer wiring layer, has TABIC chips mounted face down inside, and has a plurality of lattice-shaped tip carrier terminals on the back surface, and is made of a material with good thermal conductivity. . A plurality of A same leadless step carriers each having a chip carrier cover to which an IC chip die is directly adhered, and each of the terminal pads on the surface of the wiring layer and each of the chip carrier terminals on the back surface of the chip carrier substrate are connected. A multi-step cage characterized by including.