JPS59177921A - Adhesion of film - Google Patents

Adhesion of film

Info

Publication number
JPS59177921A
JPS59177921A JP58052995A JP5299583A JPS59177921A JP S59177921 A JPS59177921 A JP S59177921A JP 58052995 A JP58052995 A JP 58052995A JP 5299583 A JP5299583 A JP 5299583A JP S59177921 A JPS59177921 A JP S59177921A
Authority
JP
Japan
Prior art keywords
mask
film
insulating substrate
substrate
linear expansion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58052995A
Other languages
Japanese (ja)
Inventor
Yasuo Kishi
岸 靖雄
Atsuo Mizukami
水上 敦夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Sanyo Denki Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Sanyo Denki Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd, Sanyo Denki Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP58052995A priority Critical patent/JPS59177921A/en
Publication of JPS59177921A publication Critical patent/JPS59177921A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02Details
    • H01L31/0224Electrodes
    • H01L31/022466Electrodes made of transparent conductive layers, e.g. TCO, ITO layers

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Photovoltaic Devices (AREA)

Abstract

PURPOSE:To enable to make a mask to be adhered closely and to cover the surface of an insulating substrate even in a heated condition, to enable to prevent a film from oozing at the edge part, and to contrive to enhance precision of a process by a method wherein a material having nearly the same coefficient of linear expansion is used as a mask to cover the surface of the insulating substrate. CONSTITUTION:One main surface of an insulating substrate 10 manufactured of transparent glass is covered with a mask 11 having nearly the same coefficient of linear expansion with the substrate 10. First electrode layers 13a, 13b, 13c consisting of a transparent oxide electrode material of SnO2, In203-SnO2, etc. patterned in the previously decided pattern are adhered according to electron beam evaporation on the insulating substrate 10 through opening parts 12a, 12b, 12c dug in the mask 11. The temperature of the substrate at this time is held to the degree of 300 deg.C to obtain the desired transparency.

Description

【発明の詳細な説明】 (イ)産業上の利用分野 本発明はマスクを利用した膜の被着方法に関する。[Detailed description of the invention] (b) Industrial application field The present invention relates to a method of depositing a film using a mask.

(ロ)従来技術 基板表面C二被着される半導体膜は、半導体クエへ−で
は適さない大面積化C:好適であり、その製造性にも優
れているために、近年その利用が急速に発展している。
(b) Conventional technology The semiconductor film deposited on the surface of the substrate is large-area C, which is not suitable for semiconductor substrates.Since it is suitable and has excellent manufacturability, its use has rapidly increased in recent years. It is developing.

斯る半導体膜を利用した装置の一例として、大面積化が
要求される光起電力装置、所謂太陽電池が存在する。
An example of a device using such a semiconductor film is a photovoltaic device that requires a large area, a so-called solar cell.

第1図は上記光起電力装置を示し、(1)はガラス・透
光性プラスチック等の絶縁基板、(2a)(21))C
20)は該絶縁基板(1)の−主面C:並設された複数
の光電変換領域で、該変換領域(2a)(2b)(2Q
)の各々は、絶縁基板(1)側から酸化ヌ;l’(Sn
02)、酸化インジウムスズ(Inz05−8nO2)
等の透明酸化電極材の第1電極膜(5a)(3’b)(
3c)と、例えば光入射側からPIN接合を有するアモ
ルファスシリコン等の光半導体膜(4a)(41))(
40)と、該光半導体膜(4a)(4b)(40)とオ
 !。
FIG. 1 shows the photovoltaic device described above, in which (1) is an insulating substrate made of glass or transparent plastic, (2a) (21))C
20) is the main surface C of the insulating substrate (1): a plurality of photoelectric conversion regions arranged in parallel, the conversion regions (2a) (2b) (2Q
) is oxidized from the insulating substrate (1) side;
02), indium tin oxide (Inz05-8nO2)
The first electrode film (5a) (3'b) (
3c) and, for example, an optical semiconductor film (4a) (41)) such as amorphous silicon having a PIN junction from the light incidence side.
40), the optical semiconductor film (4a) (4b) (40) and O! .

グ接触するアルミニウムAI!等の第2電極膜(51L
)(51))(5C)と、を順次重畳せしめた積層構造
を成している。更に、上記並設された光電変換領域(2
a)(21))C2Q)は右隣りの光半導体膜(4b)
C40)下面から絶縁基板(1)上に露出した第1電極
膜(51))C5Q)の露出部(6舊)(!IC′)に
、左隣りの光半導体膜(4a) (41))上面から延
出して来た第2電極膜(5a)(51))の延長部(5
a’)(51)’)が直接結合し、従って複数の光電変
換領域(2a)(21))(20)は電気的に直列接続
される。
Aluminum AI that comes into contact with the robot! The second electrode film (51L
)(51))(5C) are sequentially stacked to form a laminated structure. Furthermore, the above-mentioned parallel photoelectric conversion regions (2
a)(21))C2Q) is the optical semiconductor film (4b) on the right
C40) The exposed part (6) (!IC') of the first electrode film (51)) C5Q) exposed on the insulating substrate (1) from the bottom surface is covered with the adjacent optical semiconductor film (4a) (41)) on the left. The extension part (5) of the second electrode film (5a) (51)) extending from the upper surface
a′)(51)′) are directly coupled, and thus the plurality of photoelectric conversion regions (2a)(21))(20) are electrically connected in series.

この様な装置に於いて、光利用効率を左右する一つの要
因は、装置全体の受光面積(即ち、基板面積)に対し、
実際に発電C″−−寄与光電変換領域(2a)(21)
)(20)の総面積の占める割合いである。然るに各光
電変換領域(2N) (21))(20)の隣接間隔に
必然的に存在する分離領域は上記面積割合いを低下させ
る。
In such a device, one factor that affects the light utilization efficiency is the light receiving area (i.e. substrate area) of the entire device.
Actual power generation C″--contributing photoelectric conversion area (2a) (21)
) (20) is the proportion of the total area. However, the separation regions that inevitably exist at adjacent intervals between the photoelectric conversion regions (2N), (21), and (20) reduce the above-mentioned area ratio.

従って、光利用効率を向上させるためには各光電変換領
域(21L)(21))(20)の隣接間隔である分離
領域を小さくしなければならない。
Therefore, in order to improve the light utilization efficiency, it is necessary to reduce the separation region, which is the interval between adjacent photoelectric conversion regions (21L), (21), and (20).

斯る間隔縮小は6膜の加工精度で決まり、従って、細密
加工性に優れている写真蝕刻技術が有望である。この技
術による場合、基板(1)全面への第1電極膜の被着工
程と、フォトレジスト及びエツテングによる各個別の第
1電極膜(31L)(31))(50)の分離、即ち各
第1電極膜(3a)(311)(30)の隣接間隔部分
の除去工程と、を順次経た後、同様の被着工程及び除去
工程を光半半導体膜(4a)(41))(40)並びI
Jj&2電極膜(5tL)(5’b)(5c)について
も各々再度縁り返し行なうことになる。
Such a reduction in the spacing is determined by the processing accuracy of the six films, and therefore, photolithography, which has excellent precision processing properties, is promising. In the case of this technique, the first electrode film is deposited on the entire surface of the substrate (1), and the individual first electrode films (31L), (31), and (50) are separated by photoresist and etching. 1 electrode films (3a) (311) (30), and then the same deposition and removal steps are performed on the optical semi-semiconductor films (4a) (41)) (40) and I
Jj & 2 electrode films (5tL) (5'b) (5c) will also be turned over again.

然し乍ら、上記写真蝕刻技術は水洗い等のクエソトプロ
セスを含むために、光半導体膜(4a)(4b)(4C
)にピンホールが形成されることがあり、次工程で被着
される第2電極材が斯るピンホールを介して第1電極膜
(3a)(3b)(30) l二到達する結果、該第1
電極膜(3a)(3’b)(3c)は当該光電変換領域
(21L) (2b)(20)(7)光半導体膜(4a
)(4’b)(4C)を挾んで対向する第2電極膜(5
a)(511)(50)と電気的に短絡する事故ン招い
ていた。
However, since the photo-etching technique described above includes a process such as washing with water, the photo-semiconductor film (4a) (4b) (4C
), and the second electrode material deposited in the next step reaches the first electrode film (3a) (3b) (30) through the pinhole. The first
The electrode films (3a) (3'b) (3c) are the photoelectric conversion regions (21L) (2b) (20) (7) and the optical semiconductor films (4a).
) (4'b) (4C) and the second electrode film (5
a) (511) and (50) caused an electrical short circuit accident.

また、第2電極膜(5a)(51))(50)がオーミ
ッグ接触する光半導体膜(4a)(41))(40)の
接触面は上記写真蝕刻技術によるフォトレジストの塗付
・剥離及び水洗いに於いてビンボールが形成されないま
でも膜質が劣化せしめられると共に、水洗いに使用した
水が僅かながら残留し次工程で被着される第2電極膜(
5a)(5b)(5o)v腐食する危惧ビ有していた。
Further, the contact surfaces of the optical semiconductor films (4a) (41)) (40) with which the second electrode films (5a) (51)) (50) come into Ohmig contact are coated and peeled off with photoresist using the photolithography technique described above. Even if no bottles are formed during washing, the film quality deteriorates, and a small amount of the water used for washing remains, causing the second electrode film to be deposited in the next process.
5a) (5b) (5o)v There was a risk of corrosion.

一方、写真蝕刻技術を使用せず6膜の被着工程の際、被
着面馨マスクで覆い該マスクに穿たれた開口部を介して
予め定められたパターンの膜!直接被着せしめるマスク
技術も存在するが、斯るマスク技術は製造工程が簡単に
なるにも拘らず、特に加熱状態にある基板表面に膜を被
着せしめる場合、その膜の工7ヂ部が浸み出すために加
工精度が悪く此の種装置の間隔縮小に適さない。
On the other hand, during the process of depositing six films without using photo-etching technology, the surface to be applied is covered with a mask and the film in a predetermined pattern is formed through the openings made in the mask. Direct deposition mask technology also exists, but although such mask technology simplifies the manufacturing process, it is difficult to process the 7th part of the film, especially when depositing the film on a heated substrate surface. Because of the seepage, processing accuracy is poor and it is not suitable for reducing the spacing of this type of equipment.

し1 発明の目的 本発明は斯る点に鑑みて為されたものであって、その目
的は、製造工程が簡単となるマスク技術を使用するにも
拘らず、加工精度を向上せしめた膜の被着方法を提供す
ること(二ある。
1. Purpose of the Invention The present invention has been made in view of the above, and its purpose is to create a film that improves processing accuracy despite using mask technology that simplifies the manufacturing process. Providing a deposition method (there are two).

に)発明の構成 本発明膜の被着方法は、加熱状態にある絶縁基板表面を
、該基板とほぼ等しい線膨張率を有するマスクで覆い、
該マスクの開ロ部ン介して上記基板表面に半導体膜・電
極膜等の膜を被着せしめる構成にある。
B) Structure of the Invention The method for depositing a film of the present invention includes covering the surface of an insulating substrate in a heated state with a mask having a coefficient of linear expansion approximately equal to that of the substrate;
The structure is such that a film such as a semiconductor film or an electrode film is deposited on the surface of the substrate through the opening of the mask.

―)実施例 第2図、第3図及び第5図乃至第8図は本発明7光起電
力装置の製造に適用したー実施例Z示し、第2図の第1
の工程では透明なガラス製絶縁基板(10)の−主面を
該基板00)とほぼ等しい線膨張率を有するマスク11
11で覆い、該マスク(Illに穿たれた開口部(12
a)(12b)(12C)Y介L”C上記絶縁基板(1
)上に予め定られたパターンにパターニングされた厚み
2000〜5000AのSnO2、In2O!t−8n
02等の透明酸化電極材から成る第1電極層(13a)
(15b)(13c)が電子ビーム蒸着により被着され
る(第3図)。この時の基板温度は所望の透明度を得る
べく300℃程度に保持される。
-) Embodiment 2, 3, and 5 to 8 show Embodiment Z, which was applied to the manufacture of the present invention 7 photovoltaic device.
In the process, the main surface of the transparent glass insulating substrate (10) is covered with a mask 11 having a coefficient of linear expansion approximately equal to that of the substrate (00).
11, and the opening (12
a) (12b) (12C) Y through L”C above insulating substrate (1
) SnO2, In2O with a thickness of 2000-5000A patterned in a predetermined pattern on top! t-8n
A first electrode layer (13a) made of a transparent oxidized electrode material such as 02
(15b) (13c) are deposited by electron beam evaporation (FIG. 3). At this time, the substrate temperature is maintained at about 300° C. to obtain the desired transparency.

ここで、絶縁基板(IQ)が300℃程度の加熱状態に
あること、及びマスク(Illが該基板(10)の線膨
張率とほぼ等しいことに注目すべきである。即ち、従来
のマスク技術は絶愕基板αQとマスクCLfJとの線膨
張率について何ら考慮されておらず、例えば線膨張率8
0 X 10−7 〜110X10  娩 のソ−ダ石
灰ガラス製の絶縁基板(10)に対し、170X’10
−7〜180 X 10−’/−Cのステンレス等から
成る金属製のマスクODが用いられていた。従って、絶
縁基板(10)が加熱状態に保持されると、常温では上
記絶縁基板flo)の表面に対し密着被覆状態にあった
マスクaυは、温度上昇に伴なって基板(10)に比し
て大きく線膨張し、第4回置及び同図tBlの如く基板
(10)表面との間(二値かな間隙dy影形成る。斯る
間隙dは、基板(1(eの線膨張率tα1、マスクのそ
れをα2、温度差をT、膨張部の長さを2Lとすると、
下式C二より近似的に求められる。
Here, it should be noted that the insulating substrate (IQ) is heated to about 300° C. and that the mask (Ill) is approximately equal to the coefficient of linear expansion of the substrate (10). That is, the conventional mask technology does not take into account the coefficient of linear expansion between the substrate αQ and the mask CLfJ, for example, the coefficient of linear expansion is 8.
170X'10 for a soda lime glass insulating substrate (10) of 0X10-7 to 110X10
A metal mask OD made of stainless steel or the like with a size of -7 to 180 x 10-'/-C was used. Therefore, when the insulating substrate (10) is kept in a heated state, the mask aυ, which was in a state of tightly covering the surface of the insulating substrate (flo) at room temperature, becomes smaller than the substrate (10) as the temperature rises. As shown in the fourth rotation and tBl in the same figure, a (binary gap dy) is formed between the surface of the substrate (10).Such a gap d is , let α2 be that of the mask, T be the temperature difference, and 2L be the length of the expansion part.
It can be obtained approximately from the following formula C2.

従って、α+ = 80 x 10  /T、、α2=
180X  10−’/C,、T=300℃、 2L=
10(1)(二於ける間隙dは約4調となる。即ち、第
4図(Blに示す如く、各光電変換領域の隣接間隙部を
長手方向10側に亘すマスクしようとすれば、最大約4
Mの間隙dが理論上形成されることになる。
Therefore, α+ = 80 x 10 /T, α2=
180X 10-'/C, T=300℃, 2L=
10 (1) (The gap d at 2 is approximately 4 tones. That is, as shown in FIG. Maximum about 4
A gap d of M is theoretically formed.

この様にして従来に於いては、常温では被覆すべき部分
を完全に密着被覆せしめていた!=も拘らず、膜被着時
僅かながらも間隙dを形成するために、該間隙dに蒸気
流が回り込む結果、膜のエッチ部に加工精度の低下をも
たらす浸み出しを発生せしめていたのである。
In this way, in the past, the parts to be covered were completely covered at room temperature! =However, when the film was deposited, a small gap d was formed, and as a result, the vapor flow went around the gap d, causing seepage in the etched part of the film that caused a decrease in processing accuracy. be.

即ち、本実施例の如く線膨張率のほぼ等しい材料から成
るマスクaυを使用するとたとえ膜被着時絶縁基板(1
〔が加熱されても間隙dは形成されるに至らずマスクa
υは上記絶縁基板(10)の表面(二対し常温と同じく
密着被覆状態を継続し、膜のエッチ部に於いて浸み出し
を発生せしめない。この実施例に用いられるマスク材料
としてはガラスや部分結晶化ガラス及び該部分結晶化ガ
ラスを更に結晶化したガラス・セラミックが好適であり
、例えばコーニング社から商品名「フォトフオーム」、
同「フォトフオーム・オパール」、同「フォトセラム」
として販売されている。斯るマスク材料の線膨張孫子は
順次84X1[1−シ飄89X10℃痘lG4X10−
%と絶縁基板(10)材料のそれとほぼ等しい。
That is, if a mask aυ made of a material with approximately the same coefficient of linear expansion is used as in this example, even if the insulating substrate (1
Even if [ is heated, the gap d is not formed and the mask a
υ continues to be tightly coated on the surface (2) of the insulating substrate (10) as at room temperature, and no seepage occurs in the etched portion of the film.The mask material used in this example is glass or Partially crystallized glass and glass/ceramics obtained by further crystallizing the partially crystallized glass are suitable, such as the product name "Photoform" from Corning Corporation;
"Photoform Opal" and "Photoceram"
It is sold as. The linear expansion of such a mask material is sequentially 84X1 [1-shi 89X10℃ 1G4
% is approximately equal to that of the insulating substrate (10) material.

更に、上記コーニング社製のガラス乃至ガラス・セラミ
ックは紫外線の照射された部分とそうでない部分とでは
酸C二溶ける速度が異なる感光性を呈し、従ってマスク
CIl+形成に写真蝕刻技術を利用し、該マスク材料に
フォトレジストを使用することなく直接マスクパターン
を露光することができるので、正確なエツデング加工を
施すことができ微細なマスクパターンを有するマスク圓
が得られる。
Furthermore, the glass or glass-ceramic manufactured by Corning Co., Ltd. exhibits photosensitivity in which the rate at which acid C2 dissolves differs between the portions irradiated with ultraviolet rays and the portions not irradiated with ultraviolet rays. Since the mask pattern can be directly exposed without using photoresist as the mask material, accurate etching processing can be performed and a mask circle having a fine mask pattern can be obtained.

次いで第5図の工程ではマスク■によって各第1電極膜
(15凰)(13’b)(130)の左端部のみを被覆
した状態で、シラン雰囲気中でのプラズマ反応により開
口部(15IL)(151))(150)を介して厚み
5000A〜1μm程度のPIN接合を有するアモルフ
ァスシリコンから成る半導体膜(16&)(161))
(160)を被着する(第6図)。斯る半導体膜(16
&)(16b)(16G)の被着工程に於いて、絶縁基
板ellは約300℃g=保持されるにも拘らず、該基
板0(2)と線膨張率がほぼ等しいために半導体膜(1
6’) (16′b) (160)ノ工yチg1m浸ミ
出シは発生しない。
Next, in the process shown in FIG. 5, with only the left end of each first electrode film (15 凰) (13'b) (130) covered with a mask 2, an opening (15IL) is formed by a plasma reaction in a silane atmosphere. (151)) Semiconductor film made of amorphous silicon having a PIN junction with a thickness of about 5000A to 1μm through (150) (16&) (161))
(160) is applied (Fig. 6). Such a semiconductor film (16
&) (16b) In the deposition process of (16G), even though the insulating substrate ELL is held at approximately 300°C, the semiconductor film (1
6') (16'b) (160) No leaching or seeping occurs during the process.

第7図の最終工程では、マスク(17)が隣接間隔部(
18a’b)(1131:lo)lニー於いて露出せる
第1電極膜(151))(130)の露出部(131)
)(,13Q’)の根元部分(13b“)(13Q“)
及び基板α0の端部な覆った状態で、開口部(19a)
(19’b)(19c)を介して厚み5000A〜1μ
m程度の1/かう成る第2電極膜(20tL)(201
))(20(1)が真空蒸着により被着される。第8図
は被着後の状態を示している。斯る臭突蒸着工程に於け
る基板0Qは直接熱源により加熱されていないが、Al
t加熱蒸発せしめている関係で約100〜120″C1
=温度上昇している。
In the final step in FIG. 7, the mask (17)
18a'b) (1131: lo) Exposed part (131) of the first electrode film (151)) (130) exposed at the knee
) (, 13Q') root part (13b") (13Q")
and the opening (19a) in a state where the end of the substrate α0 is covered.
(19'b) Thickness 5000A ~ 1μ via (19c)
The second electrode film (20 tL) (201
)) (20(1) is deposited by vacuum evaporation. Figure 8 shows the state after deposition. Although the substrate 0Q in this odor deposition process is not directly heated by a heat source, , Al
t Approximately 100 to 120"C1 due to heating and evaporation
=Temperature is rising.

尚、第7図に於いてマスクαηと基板(10)との間に
間隙δが図面の都合−L、第4図(Blに示したマスク
(11)の熱膨張による間隙dよりも大きく描かれてい
るが、実際上記間隙δは$1電極膜(13”)(13’
tl)(130)と半導体膜(16&)(161+)(
160)との厚みの和C二相当し、従って1〜2μm程
度であって、上記具体例の如く一オーダのdとの間には
δ(dの関係にあり、μmオ−ダの間隙δはほとんど問
題とならない。
In addition, in FIG. 7, the gap δ between the mask αη and the substrate (10) is drawn larger than the gap d due to thermal expansion of the mask (11) shown in FIG. However, in reality, the above gap δ is $1 electrode film (13") (13'
tl) (130) and semiconductor film (16 &) (161+) (
160), and is therefore about 1 to 2 μm, and as in the above example, there is a relationship of δ(d) with d, which is on the order of μm, and the gap δ is on the order of μm. is hardly a problem.

(へ)発明の効果 本発明は以上の説明から明らかな如く、絶縁基板表面V
覆うマスクは、上記基板とほぼ等しい線膨張率を有して
いるので、加熱状態に於いてもマスクは基板表面を密着
被覆することができ、従って製造工程が簡単となるマス
ク技術を使用するにも拘らず、膜のエッチ部に於ける浸
み出し’vV!A止することができ、加工精度の向上が
図れ、特に光起電力装置の製造に用いて有益である。
(f) Effects of the Invention As is clear from the above description, the present invention provides an insulating substrate surface V
Since the covering mask has approximately the same coefficient of linear expansion as the substrate, the mask can closely cover the surface of the substrate even in a heated state. Therefore, using mask technology that simplifies the manufacturing process. Despite this, seepage in the etched area of the membrane is still low! A can be stopped, the processing accuracy can be improved, and it is particularly useful for manufacturing photovoltaic devices.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は基本的な光起電力装置の要部を示す斜視図、第
2図・第3図及び第5図乃至第8図は本発明を光起電力
装置の製造方法に適用した実施例を工程別に示す断面図
、第4図体)は従来例を示す上面図、第4図(Blは同
図内に於けるB−d線断面図、である。 0.0) ・・・絶縁基板、(11)(111(141
(17)−? スフ、(13&)(151))(13Q
)・・・第1電極膜、(161L)(161) ) (
160) ・・・半導体膜、(201(20’b)(2
00)・・・第2電極膜。 第1図 第2図 O 第3図 第4図 第5図
FIG. 1 is a perspective view showing the main parts of a basic photovoltaic device, and FIGS. 2, 3, and 5 to 8 are examples in which the present invention is applied to a method for manufacturing a photovoltaic device. Fig. 4 is a top view showing a conventional example, and Fig. 4 (Bl is a sectional view taken along line B-d in the same figure. 0.0) ... Insulating substrate , (11) (111 (141
(17)-? Sufu, (13 &) (151)) (13Q
)...first electrode film, (161L) (161) ) (
160)...Semiconductor film, (201(20'b)(2
00)...Second electrode film. Figure 1 Figure 2 O Figure 3 Figure 4 Figure 5

Claims (1)

【特許請求の範囲】[Claims] (1)加熱状態にある絶縁基板表面を、該基板とほぼ等
しい線膨張率を有するマスクで覆い、該マスクの開口部
を介して上記基板表面に半導体膜・電極膜等の膜を被着
せしめることを特徴とした膜の被着方法。
(1) Covering the heated insulating substrate surface with a mask having a coefficient of linear expansion approximately equal to that of the substrate, and depositing a film such as a semiconductor film or an electrode film on the substrate surface through the opening of the mask. A film deposition method characterized by:
JP58052995A 1983-03-28 1983-03-28 Adhesion of film Pending JPS59177921A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58052995A JPS59177921A (en) 1983-03-28 1983-03-28 Adhesion of film

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58052995A JPS59177921A (en) 1983-03-28 1983-03-28 Adhesion of film

Publications (1)

Publication Number Publication Date
JPS59177921A true JPS59177921A (en) 1984-10-08

Family

ID=12930503

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58052995A Pending JPS59177921A (en) 1983-03-28 1983-03-28 Adhesion of film

Country Status (1)

Country Link
JP (1) JPS59177921A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6461908A (en) * 1987-09-02 1989-03-08 Fuji Electric Co Ltd Mask for thin-film formation
WO1998029902A1 (en) * 1996-12-27 1998-07-09 Radiant Technologies, Inc. Method for restoring the resistance of indium oxide semiconductors after heating while in sealed structures
US5840620A (en) * 1994-06-15 1998-11-24 Seager; Carleton H. Method for restoring the resistance of indium oxide semiconductors after heating while in sealed structures

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6461908A (en) * 1987-09-02 1989-03-08 Fuji Electric Co Ltd Mask for thin-film formation
US5840620A (en) * 1994-06-15 1998-11-24 Seager; Carleton H. Method for restoring the resistance of indium oxide semiconductors after heating while in sealed structures
WO1998029902A1 (en) * 1996-12-27 1998-07-09 Radiant Technologies, Inc. Method for restoring the resistance of indium oxide semiconductors after heating while in sealed structures

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