JPS59176943A - インタ−フエ−ス回路 - Google Patents

インタ−フエ−ス回路

Info

Publication number
JPS59176943A
JPS59176943A JP58051218A JP5121883A JPS59176943A JP S59176943 A JPS59176943 A JP S59176943A JP 58051218 A JP58051218 A JP 58051218A JP 5121883 A JP5121883 A JP 5121883A JP S59176943 A JPS59176943 A JP S59176943A
Authority
JP
Japan
Prior art keywords
circuit
pulse
signal
bipolar
signal line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58051218A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0147064B2 (enrdf_load_stackoverflow
Inventor
Yutaka Takahashi
裕 高橋
Tetsuichiro Sasada
哲一郎 笹田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP58051218A priority Critical patent/JPS59176943A/ja
Publication of JPS59176943A publication Critical patent/JPS59176943A/ja
Publication of JPH0147064B2 publication Critical patent/JPH0147064B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Dc Digital Transmission (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
JP58051218A 1983-03-26 1983-03-26 インタ−フエ−ス回路 Granted JPS59176943A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58051218A JPS59176943A (ja) 1983-03-26 1983-03-26 インタ−フエ−ス回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58051218A JPS59176943A (ja) 1983-03-26 1983-03-26 インタ−フエ−ス回路

Publications (2)

Publication Number Publication Date
JPS59176943A true JPS59176943A (ja) 1984-10-06
JPH0147064B2 JPH0147064B2 (enrdf_load_stackoverflow) 1989-10-12

Family

ID=12880781

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58051218A Granted JPS59176943A (ja) 1983-03-26 1983-03-26 インタ−フエ−ス回路

Country Status (1)

Country Link
JP (1) JPS59176943A (enrdf_load_stackoverflow)

Also Published As

Publication number Publication date
JPH0147064B2 (enrdf_load_stackoverflow) 1989-10-12

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