JPH0147064B2 - - Google Patents

Info

Publication number
JPH0147064B2
JPH0147064B2 JP58051218A JP5121883A JPH0147064B2 JP H0147064 B2 JPH0147064 B2 JP H0147064B2 JP 58051218 A JP58051218 A JP 58051218A JP 5121883 A JP5121883 A JP 5121883A JP H0147064 B2 JPH0147064 B2 JP H0147064B2
Authority
JP
Japan
Prior art keywords
circuit
signal
pulse
timing
waveform
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP58051218A
Other languages
English (en)
Japanese (ja)
Other versions
JPS59176943A (ja
Inventor
Yutaka Takahashi
Tetsuichiro Sasada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP58051218A priority Critical patent/JPS59176943A/ja
Publication of JPS59176943A publication Critical patent/JPS59176943A/ja
Publication of JPH0147064B2 publication Critical patent/JPH0147064B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Dc Digital Transmission (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
JP58051218A 1983-03-26 1983-03-26 インタ−フエ−ス回路 Granted JPS59176943A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58051218A JPS59176943A (ja) 1983-03-26 1983-03-26 インタ−フエ−ス回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58051218A JPS59176943A (ja) 1983-03-26 1983-03-26 インタ−フエ−ス回路

Publications (2)

Publication Number Publication Date
JPS59176943A JPS59176943A (ja) 1984-10-06
JPH0147064B2 true JPH0147064B2 (enrdf_load_stackoverflow) 1989-10-12

Family

ID=12880781

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58051218A Granted JPS59176943A (ja) 1983-03-26 1983-03-26 インタ−フエ−ス回路

Country Status (1)

Country Link
JP (1) JPS59176943A (enrdf_load_stackoverflow)

Also Published As

Publication number Publication date
JPS59176943A (ja) 1984-10-06

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