JPS59175733A - Insulated type semiconductor device - Google Patents

Insulated type semiconductor device

Info

Publication number
JPS59175733A
JPS59175733A JP58048882A JP4888283A JPS59175733A JP S59175733 A JPS59175733 A JP S59175733A JP 58048882 A JP58048882 A JP 58048882A JP 4888283 A JP4888283 A JP 4888283A JP S59175733 A JPS59175733 A JP S59175733A
Authority
JP
Japan
Prior art keywords
layer
plate
metal
semiconductor device
solder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58048882A
Other languages
Japanese (ja)
Inventor
Yasutoshi Kurihara
保敏 栗原
Tadashi Minagawa
皆川 忠
Komei Yatsuno
八野 耕明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP58048882A priority Critical patent/JPS59175733A/en
Publication of JPS59175733A publication Critical patent/JPS59175733A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612Auxiliary members for layer connectors, e.g. spacers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/291Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/8385Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06Polymers
    • H01L2924/078Adhesive characteristics other than chemical
    • H01L2924/07802Adhesive characteristics other than chemical not being an ohmic electrical conductor

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)
  • Thyristors (AREA)

Abstract

PURPOSE:To eliminate the possibility of denaturation or damage based on thermal strain by bonding a metallic plate for loading a semiconductor base body onto a metallic layer consisting of a plurality of inorganic insulating members with a metallic solder. CONSTITUTION:An alumina plate 2 is bonded with one main surface of a metallic support plate 1, and a metallized layer 201 and a copper layer 203 are formed on the bonding surface. A metallized layer 202 and a copper layer 204 are shaped on one surface of the plate 2. A metallic plate 3 is bonded on the layer 204 with a solder layer 102. The layers 203, 204 are unified, and a thermal expansion coefficient as the whole of the composite alumina plate 2 is brought close to that of the metallic plate 3. According to such constitution, heat cycle resistance can be improved without substantially lowering radiant property.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は半導体装置に係勺、特に、半導体基体支持部材
とは電気的に絶縁された構造を有する絶縁型半導体装置
に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a semiconductor device, and particularly to an insulated semiconductor device having a structure electrically insulated from a semiconductor substrate support member.

〔従来技術J 従来のこの種の半導体装置は、これを支持する支持部材
を半導体装置の一電極として兼用させる場合が多かった
。近年、半導体装置の全ての電極を金属支持部材から電
気的に絶縁し、もって半導体装置の回路適用上の自由度
を増すことのできる構造が出現している。例えば、双方
向性3端子サイリスク(トライアック)基体をセラミッ
クス板上に載置し、このセラミックス板を金属パッケー
ジに封入してなる絶縁型トライアックは、トライアック
の全ての電極をセラミックス板にょシパッケージから絶
縁して外部へ引出した構成となっている。このような構
成であるために、一対の主電極が回路上の接地電位から
電気的に浮いている使用例であっても、電極電位とは無
関係にパッケージを接地電位部に固定することができる
ので、半導体装置の実装は容易になる。
[Prior Art J] In conventional semiconductor devices of this type, the supporting member that supports the device often doubles as one electrode of the semiconductor device. In recent years, structures have emerged that can electrically insulate all electrodes of a semiconductor device from a metal support member, thereby increasing the degree of freedom in circuit application of the semiconductor device. For example, an insulated triac is made by placing a bidirectional three-terminal TRIAC substrate on a ceramic plate and enclosing this ceramic plate in a metal package. The structure is such that it is drawn out to the outside. Because of this configuration, even in applications where the pair of main electrodes are electrically floating from the ground potential on the circuit, the package can be fixed to the ground potential regardless of the electrode potential. Therefore, mounting of the semiconductor device becomes easy.

また、混成集積回路装置あるいは半導体モジュール装置
(以下、混成ICと一括して略称する)では、一般に半
導体素子を含むあるまとまった電気回路が組込まれてい
るため、その回路の少なくとも一部と混成ICの支持部
材あるいは放熱部材等の金属部とを電気的に絶縁する必
要がある。代表的な混成ICでは、金属の支持部材上に
無機質あるいは有機質の絶縁層を配置し、この絶縁層上
に所定の電気回路を組立てることにょシ、上述の絶縁を
達成している。このような混成ICもまた絶縁型半導体
装置である。
In addition, since a hybrid integrated circuit device or a semiconductor module device (hereinafter collectively referred to as hybrid IC) generally incorporates a certain set of electric circuits including semiconductor elements, at least a part of the circuit and the hybrid IC It is necessary to electrically insulate metal parts such as supporting members or heat dissipating members. In a typical hybrid IC, the above-mentioned insulation is achieved by disposing an inorganic or organic insulating layer on a metal support member and assembling a predetermined electric circuit on this insulating layer. Such a hybrid IC is also an insulated semiconductor device.

一方、半導体装置を安牟がっ安定に動作させるためには
、半導体装置の動作時に生ずる熱をパッケージの外部に
有効に発散させる必要がある。この熱発散は、通常、発
熱源である半導体基体からこれと接着された各部材を通
じて気中へ熱伝達される。該絶縁型半導体装置は、この
熱伝導経路中部分や、絶縁層および絶縁層と半導体基体
とを接着する部分等に用いられた接着材層を含んでいる
On the other hand, in order to operate the semiconductor device safely and stably, it is necessary to effectively dissipate heat generated during the operation of the semiconductor device to the outside of the package. This heat dissipation is normally transferred from the semiconductor substrate, which is the heat source, to the air through the members bonded to the semiconductor substrate. The insulated semiconductor device includes an adhesive layer used in the middle of the heat conduction path, the insulating layer, and the part where the insulating layer and the semiconductor substrate are bonded.

また、半導体装置を含む回路の扱う電圧が高くなればな
るほど、あるいは要求される信頼性(経時的安定性、耐
湿性、耐熱性等)が高くなれはなるほど、完全な絶縁性
が要求される。さらに、半導体装置に要求される耐熱性
は、半導体装置の周囲の温度が外因にょシ上昇した場合
の耐熱性と、半導体装置の扱う電力が大きく、半導体基
体から発生する熱が大きくなった場合の耐熱性とを含ん
でいる。
Furthermore, the higher the voltage handled by a circuit including a semiconductor device, or the higher the required reliability (stability over time, moisture resistance, heat resistance, etc.), the more perfect insulation is required. Furthermore, the heat resistance required for semiconductor devices is the heat resistance when the temperature around the semiconductor device increases due to external causes, and the heat resistance when the semiconductor device handles a large amount of power and the heat generated from the semiconductor substrate increases. This includes heat resistance.

ところで、絶縁型半導体装置内での発熱が比較的小さく
、かつ耐圧や、要求される信頼性がさitど高くない場
合には、絶縁層や接着材層は、どのようなものを用いて
も特に問題が発生することはない。
By the way, if the heat generation within the insulated semiconductor device is relatively small and the withstand voltage and required reliability are not particularly high, then any insulating layer or adhesive layer may be used. No particular problems occur.

しかしながら、発熱が大きい場合や信頼性に対する要求
が高い場合には、絶縁層としては、セラミックスのよう
な無機質材料が選択されている。
However, in cases where heat generation is large or reliability is required to be high, inorganic materials such as ceramics are selected as the insulating layer.

また、接着材層としては、例えば、鉛−錫系はんだのよ
うな金属ろうが選択されている。
Further, as the adhesive layer, for example, a metal solder such as lead-tin solder is selected.

そのような場合に、次のような解決すべき問題点が発生
することになる。
In such a case, the following problems will arise that need to be solved.

すなわち、絶縁型半導体装置は、半導体基体を金属板を
介して絶縁層上に取付けられているのが一般的である。
That is, an insulated semiconductor device generally has a semiconductor substrate mounted on an insulating layer via a metal plate.

前記絶縁型半導体装置の金属板は半導体基体と外部の電
源とを結ぶ導電路として作用させると共に、半導体基体
からの発熱を絶縁層に効果的に伝える熱伝導路として作
用させている。
The metal plate of the insulated semiconductor device acts as a conductive path connecting the semiconductor substrate and an external power source, and also as a heat conduction path that effectively transfers heat generated from the semiconductor substrate to the insulating layer.

この金属板には、銅等の低抵抗、高熱伝導性を有する金
属が用いられている。ところが、この金属と絶縁層とは
熱膨張係数が異なっている。例えば、絶縁層がアルミナ
の場合の熱膨張係数は6.3×10−6/l:”である
のに対して、銅の熱膨張係数は18 X 10−6/U
であシ、銅の熱膨張係数の方が極めて太きい。
This metal plate is made of a metal having low resistance and high thermal conductivity, such as copper. However, this metal and the insulating layer have different coefficients of thermal expansion. For example, when the insulating layer is made of alumina, the thermal expansion coefficient is 6.3 x 10-6/l, whereas the thermal expansion coefficient of copper is 18 x 10-6/U.
However, the coefficient of thermal expansion of copper is extremely large.

したがって、この熱膨張係数の差によって、絶縁型半導
体装置は、その使用時に金属ろう部分が熱疲労で破壊さ
れるおそれがある。
Therefore, due to this difference in coefficient of thermal expansion, there is a risk that the metal solder portion of the insulated semiconductor device will be destroyed due to thermal fatigue during use.

さらに詳説すると、半導体装置は、通電、休止の動作の
繰シ返しに伴なって、上述の接合部には、高温状態(約
100〜150t:)と、低温状態(周囲温度)とが繰
返し訪れることになる。このような高温−低源の繰返し
くその1周期をヒートサイクルと呼ぶ)毎に、該半導体
装置における各部材は、それらに固有の熱膨張係数に基
づく膨張、収縮を繰返すことになる。各部材は互いに固
着されているから、各部材の熱膨張係数の違いに基づく
、膨張と収縮量との差は、最も軟かい部材であるはんだ
層に熱歪として加わることになる。そして、ヒートサイ
クル数が多くなると、はんだ層は、引張シ歪、圧縮歪の
周期的かつ夏型なる印加によシ、次第にもろくなシ、つ
いには熱疲労現象を生ずるに至る。例えば、はんだ層に
クラックが生じ、接着力の低下、熱伝導性の低下等を引
起す。このような現象は、はんだ層の露出端面において
顕著である。
To explain in more detail, as the semiconductor device is repeatedly energized and stopped, the above-mentioned junction is repeatedly brought into a high temperature state (approximately 100 to 150 tons) and a low temperature state (ambient temperature). It turns out. Each period of such high-temperature and low-temperature cycles is called a heat cycle, each member of the semiconductor device repeats expansion and contraction based on its own coefficient of thermal expansion. Since the members are fixed to each other, the difference in the amount of expansion and contraction based on the difference in the coefficient of thermal expansion of each member is applied as thermal strain to the solder layer, which is the softest member. As the number of heat cycles increases, the solder layer gradually becomes brittle due to the periodic and summer-like application of tensile strain and compressive strain, eventually leading to thermal fatigue phenomena. For example, cracks occur in the solder layer, causing a decrease in adhesive strength, a decrease in thermal conductivity, and the like. Such a phenomenon is remarkable at the exposed end face of the solder layer.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、上述した問題点を解決し、運転時に接
着部に生ずる熱歪を低減し、変性あるいは破損の恐れが
ない改善された絶縁型半導体装置を提供することにある
SUMMARY OF THE INVENTION An object of the present invention is to provide an improved insulated semiconductor device that solves the above-mentioned problems, reduces thermal strain occurring in the bonded portion during operation, and is free from deterioration or damage.

〔発明の概要〕[Summary of the invention]

本発明は、上記目的を達成するため、絶縁型半導体装置
において、無機質絶縁部材表面に形成された金属化層上
に金属層を形成してなる複数無機質絶縁部材の金属層上
に、金属ろうをもって、半導体基体を導電的に接着する
ための金属板を接着したことを特徴とする。
In order to achieve the above object, the present invention provides an insulated semiconductor device in which a metal solder is provided on the metal layer of a plurality of inorganic insulating members in which a metal layer is formed on a metallized layer formed on the surface of an inorganic insulating member. , is characterized in that a metal plate for conductively bonding the semiconductor substrate is bonded.

〔発明の実施例〕[Embodiments of the invention]

以下、本発明の実施例を図面に基づいて説明するが、そ
の前に本発明の詳細な説明する。
Embodiments of the present invention will be described below with reference to the drawings, but before that, a detailed explanation of the present invention will be given.

本発明においては、後述するように、特に耐ヒートサイ
クル性を向上させるために、無機質絶縁部材と、この絶
縁部材上に接着された金属板との間に介在する金属ろう
の熱疲労を防止する手段を構したものである。すなわち
、前記手段は、無機質絶縁部材の表面に湿式法によシ焼
結された金属化層と、この金属化層上にめっき形成され
た銅層等の金属層とを設けたシ、金属板を前記金−属層
上に金属ろうをもって接着して構成したものである、こ
の際、金属層を一体化した無機質絶縁部材の全体として
の熱膨張係数αを可及的に金属板の熱膨張係数に近づけ
、もって金属ろう接着部の熱疲労を軽減しようとするも
のである。この複合化された無機質絶縁部材の全体とし
ての熱ハタ脹係数αとは、複合化無機質絶縁部材の見か
けのそれである。
In the present invention, as will be described later, in order to particularly improve heat cycle resistance, thermal fatigue of the metal solder interposed between the inorganic insulating member and the metal plate bonded on the insulating member is prevented. It is a means. That is, the above-mentioned means includes a metal plate having a metallized layer sintered by a wet method on the surface of an inorganic insulating member, and a metal layer such as a copper layer plated on the metallized layer. is formed by bonding the metal layer onto the metal layer using a metal solder. At this time, the thermal expansion coefficient α of the entire inorganic insulating member with the metal layer integrated therein is adjusted to the thermal expansion of the metal plate as much as possible. The aim is to reduce thermal fatigue of metal solder joints by bringing the coefficient close to that of the metal solder. The overall thermal expansion coefficient α of the composite inorganic insulating member is the apparent value of the composite inorganic insulating member.

しだがって、複合化無機質部材がn層の素材からなる場
合、各層の素材の熱膨張係数をαI(C−り縦弾性係数
をE i (Kg/ltm ) 、厚さをt t (能
)とすれば、熱膨張係数αは、次式(1)で近似される
ものである、。
Therefore, when the composite inorganic member is made of n layers of material, the coefficient of thermal expansion of the material of each layer is αI (C), the longitudinal elastic modulus is E i (Kg/ltm), and the thickness is t t (capacity). ), the thermal expansion coefficient α is approximated by the following equation (1).

Σ 1=IBiti 特に、大型の混成ICでは、半導体基体での発熱も多い
ため、大きな熱拡散板が必要どなること、また複数の半
導体基体が用いられるということもあって、金属板の面
積、したがって絶縁部材との接着面積は、通常の個別半
導体装置での半導体基体と支持電極間の接着面積と比較
して非常に大きくなる。このような場合、金属ろうの熱
疲労を防ぐためには、上述の金属化層上にめっきされた
銅層を設けることが極めて有効なことがわかった。
Σ 1=IBiti In particular, in large hybrid ICs, there is a lot of heat generation in the semiconductor substrate, so a large heat diffusion plate is required, and multiple semiconductor substrates are used, so the area of the metal plate, and therefore the The bonding area with the insulating member is much larger than the bonding area between the semiconductor substrate and the support electrode in a normal individual semiconductor device. In such cases, it has been found that providing a plated copper layer on the metallized layer is extremely effective in preventing thermal fatigue of the solder metal.

以下、本発明に係る実施例を混成ICを例にとって図面
に基づいてさらに詳細に説明する。
Hereinafter, embodiments of the present invention will be described in more detail with reference to the drawings, taking a hybrid IC as an example.

第1図は本発明に係る実施例を、1200 V 。FIG. 1 shows an embodiment of the present invention at 1200 V.

60A級混成ICの要部を示す斜視図である。図におい
て、銅板からなる金属支持板1上に2枚のアルミナ板2
が並んで接着され、各アルミナ板2上に、このアルミナ
板2と略同形の銅板からなる金属板3がそれぞれ接着さ
れている。なお、第1図では図面の簡単化のために各部
材間の金属ろう等は図示されていない。
FIG. 2 is a perspective view showing the main parts of a 60A class hybrid IC. In the figure, two alumina plates 2 are placed on a metal support plate 1 made of a copper plate.
are lined up and adhered, and on each alumina plate 2, a metal plate 3 made of a copper plate having approximately the same shape as this alumina plate 2 is adhered, respectively. Note that, in FIG. 1, metal solder between each member is not shown for the purpose of simplifying the drawing.

一上述の金属板3上には、図示の如く半導体基体が接着
され、これらによシ第2図に示す回路が組立てられてい
る。すなわち、サイリスク401、フライホイル用ダイ
オード402がそれぞれ金属板3上に直接はんだ刊けさ
れている。各回路素子いる。また、符号4101.41
02および4103は外部端子であり、外部端子410
1は金属板3上に直接接着され、他の外部端子4102
および4103は金属板3上に接着された絶縁用アルミ
ナ板420の上に接着された配線用金属片430上に設
置されている。
As shown in the figure, a semiconductor substrate is adhered onto the metal plate 3 mentioned above, and the circuit shown in FIG. 2 is assembled therewith. That is, the cyrisk 401 and the flywheel diode 402 are each directly soldered onto the metal plate 3. There are each circuit element. Also, code 4101.41
02 and 4103 are external terminals, and external terminal 410
1 is directly glued on the metal plate 3, and the other external terminal 4102
and 4103 are installed on a wiring metal piece 430 bonded to an insulating alumina plate 420 bonded to the metal plate 3.

本実施例において重要なことは、金属板3の大きさがア
ルミナ板2と略同じでアシ、その上に全ての回路素子が
載置されておシ、この際載置されたサイリスタ401や
ダイオード402の周縁には金属板3が熱拡散板として
作用するに十分な面積を持って連なっていることにある
What is important in this embodiment is that the size of the metal plate 3 is approximately the same as that of the alumina plate 2, and all the circuit elements are placed on it. The metal plate 3 is continuous around the periphery of the metal plate 402 with a sufficient area to function as a heat diffusion plate.

第3図は、本発明に係る実施例の構造のうち、金属支持
板1から金属板3に至る部分のみを模式的に示す断面図
である。図において、金属支持板lは、厚さ3.2〔■
〕、幅30〔閣〕、長さ92〔調〕の大きさを有する銅
板である。金属支持板1の一方の主表面には、2枚のア
ルミナ板2が、40%鉛−60%錫からなるはんだ層1
01によシ接着されている。はんだ層101の厚さは約
・0、1 tmである。アルミナ板2の接着面には金属
化層201が形成され、さらにその上にめっきによシ形
成された金属層としての銅層203が形成されて、はん
だに対するぬれ性が付与されている。
FIG. 3 is a cross-sectional view schematically showing only the portion from the metal support plate 1 to the metal plate 3 of the structure of the embodiment according to the present invention. In the figure, the metal support plate l has a thickness of 3.2 [■
It is a copper plate with dimensions of 30 mm in width and 92 mm in length. On one main surface of the metal support plate 1, two alumina plates 2 are attached with a solder layer 1 made of 40% lead-60% tin.
It is glued by 01. The thickness of the solder layer 101 is approximately 0.1 tm. A metallized layer 201 is formed on the adhesive surface of the alumina plate 2, and a copper layer 203 as a metal layer formed by plating is further formed thereon to provide wettability to solder.

各アルミナ板2は、幅が25〔■〕、長さが30〔■〕
、厚さが0.3[:m)の大きさである。
Each alumina plate 2 has a width of 25 [■] and a length of 30 [■]
, the thickness is 0.3[:m].

各アルミナ板2の銅層204の上には、金属板3が、は
んだ層101と同組成、同厚さのはんだ層102をもっ
て、それぞれ接着されている。アルミナ板2の一方の面
には、上述と同様の金属化層202が形成され、さらに
その上にめっきによシ金属化層としての銅層204が形
成されている。
A metal plate 3 is bonded onto the copper layer 204 of each alumina plate 2 with a solder layer 102 having the same composition and thickness as the solder layer 101. A metallized layer 202 similar to that described above is formed on one side of the alumina plate 2, and a copper layer 204 as a metallized layer is further formed by plating thereon.

この金属板3は、厚さ2〔甜〕、幅22〔璽〕、長さ2
7 (am ]の大きさである。上述の金属化層201
や202は周知の湿式法により形成されたタングステン
を主成分とするものである。また、金属層としての銅層
203,204はそれぞれ金属化層201,202上に
直接電気めっきされたもので、厚さ約10100C]で
ある。
This metal plate 3 has a thickness of 2 [tall], a width of 22 [tall], and a length of 2
7 (am).The above-mentioned metallization layer 201
and 202 are made of tungsten as a main component and formed by a well-known wet method. Further, the copper layers 203 and 204 as metal layers are directly electroplated on the metallized layers 201 and 202, respectively, and have a thickness of about 10100 C].

ここで重要な点は、金属屑としての銅層203゜204
を一体化して複合化されたアルミナ板2の全体としての
熱膨張係数を金属板3のそれに近ずけた点にある。例え
ば、本実施例における複合化されたアルミナ板のそれは
約9.7 X 10−’、/l:’であシ、金属層とし
ての銅層203,204を形成しないアルミナ板の約6
.3 X 10−6/l:’よシ金属板3としての銅板
の熱膨張係数18X10’″6/Cに近接するように調
整されている。
The important point here is that the copper layer 203°204 as metal scrap
The thermal expansion coefficient of the alumina plate 2 as a whole, which is made into a composite by integrating the two, is made close to that of the metal plate 3. For example, the composite alumina plate in this embodiment has a thickness of about 9.7 x 10-', /l:', and the alumina plate that does not form the copper layers 203 and 204 as metal layers has a thickness of about 6.
.. 3.times.10.sup.-6/l: The coefficient of thermal expansion of the copper plate as the metal plate 3 is adjusted to be close to 18.times.10.about.6/C.

複合化された無機質絶縁部材の見かけの熱膨張係数は、
無機質絶縁部材の素材の種類や厚さを、そしてめっき形
成される銅層等の金属層の厚さを変えることによシ、調
整することが可能である。
The apparent coefficient of thermal expansion of the composite inorganic insulating material is
It can be adjusted by changing the type and thickness of the material of the inorganic insulating member and the thickness of the metal layer such as the copper layer formed by plating.

本実施例によれば、サイリスタ401から金属支持板1
に至る経路の熱抵抗が0.35’[tr/WEであシ、
金属支持板1上にアルミナ板2、金属板3、半導体基体
を順次はんだ伺けして積層した従来構造の絶縁型半導体
装置の(i、3〔C/W)と比較して、放熱性を実質上
問題となるほど低下させずに、耐ヒートサイクル性を向
上させることができた。この効果は複合化されたアルミ
ナ板の面積したがって金属板(鏑の熱拡散板の面積)が
大きくなるf止ど顕著であった。その−例を第4図によ
シ具体的に説明する。
According to this embodiment, from the thyristor 401 to the metal support plate 1
The thermal resistance of the path leading to is 0.35'[tr/WE,
Compared to (i, 3 [C/W)], an insulated semiconductor device with a conventional structure in which an alumina plate 2, a metal plate 3, and a semiconductor substrate are sequentially soldered and laminated on a metal support plate 1, the heat dissipation property is substantially improved. It was possible to improve the heat cycle resistance without lowering it to the extent that it became a problem. This effect was most noticeable when the area of the composite alumina plate and therefore the metal plate (the area of the heat diffusion plate of the kabura) became large. An example of this will be explained in detail with reference to FIG.

第4図は、本実施例構造囚および従来の構造(ト)を有
する混成ICにおいて、1枚のアルミナ板の面積に対す
る所定のヒートサイクル印加後の混成ICの故障発生率
の関係を示すグラフである。第4図において、横軸には
面積〔−〕が、縦軸には故障回数が、それぞれ示されて
いる。ヒートサイクルは、−55〜+150Cの温度の
間を150回繰返し加えたものである。第4図によれば
、アルミナ板の面積が約500[mi〕までは、構造A
1及びB共に故障発生率は0チであるが、約500−を
越えると、構造Bでは加速的に故障発生率が増加するの
に対し、構造Aでは依然として0チである。なお、ここ
で言う故障とは主としてはんだ層のクラック発生、ある
いは部分的剥離を生じた場合をいう。
FIG. 4 is a graph showing the relationship between the failure rate of the hybrid IC after applying a predetermined heat cycle to the area of one alumina plate in the hybrid IC having the structure of this embodiment and the conventional structure (G). be. In FIG. 4, the horizontal axis shows the area [-], and the vertical axis shows the number of failures. The heat cycle was repeated 150 times between temperatures of -55 and +150C. According to Figure 4, structure A is used until the area of alumina plate is about 500 [mi].
Both No. 1 and B have a failure rate of 0, but when the value exceeds about 500, the failure rate increases at an accelerating rate in Structure B, while in Structure A it is still 0. Note that failure here mainly refers to the occurrence of cracks or partial peeling of the solder layer.

第5図は、本発明の他の実施例を示す断面図である。同
図において、アルミナ板2上に2枚の金属板3が並んで
接着されておバ金属板3上には前記実施例と同様の半導
体基体がはんだ付けされて、第2図に示した電気回路が
構成されている。
FIG. 5 is a sectional view showing another embodiment of the present invention. In the same figure, two metal plates 3 are glued side by side on an alumina plate 2, and a semiconductor substrate similar to that of the previous embodiment is soldered onto the metal plate 3. The circuit is configured.

この際、アルミナ板2の金属板3に対向する面には、前
記実施例と同様の金属化層202とめつきによる銅層2
04が形成されている。アルミナ板2は幅25〔■〕、
長さ70〔叫〕、厚さ0.4〔咽〕の大きさであり、金
属層としての銅層204の厚さは約0.1[mi:]で
ある。またはんだ層102(厚さ0.1 mm )を介
して接着された金属板3は幅22〔■〕、長さ27〔簡
〕、厚さ2〔叫〕の大きさである。以上のように一体化
された構造物は採機部材4の中空部にはめこまれ、シリ
コーン樹脂からなる接着材5によシ保護部材4と一体化
されている。この保護部材4は厚さ10[m)、幅40
[mi:)、長さ92[w++)の銅板の中央部に中空
孔を設けたものである。保護部材4とアルミナ板2とで
形成された空間には最終的に樹脂が充填されて気密封止
されることになる。
At this time, on the surface of the alumina plate 2 facing the metal plate 3, a metallized layer 202 and a copper layer 2 formed by plating, similar to those in the previous embodiment, are provided.
04 is formed. Alumina plate 2 has a width of 25 [■],
It has a length of 70 mm and a thickness of 0.4 mm, and the thickness of the copper layer 204 as a metal layer is about 0.1 mm. The metal plate 3 bonded via the solder layer 102 (thickness: 0.1 mm) has a width of 22 [■], a length of 27 [Simplified], and a thickness of 2 [Extreme]. The structure integrated as described above is fitted into the hollow part of the sampling member 4, and is integrated with the protection member 4 by an adhesive 5 made of silicone resin. This protective member 4 has a thickness of 10 [m] and a width of 40 [m].
[mi:), a hollow hole is provided in the center of a copper plate with a length of 92 [w++]. The space formed by the protection member 4 and the alumina plate 2 is finally filled with resin and hermetically sealed.

本実施例において重要なことは、アルミナ板2の電気回
路が形成されない面は外部に露出していて、混成ICの
使用時にはアルミナ板2の露出面が直接放熱手段と接触
すること、つまシアルミナ板2の電気回路が形成されな
い面には上述の金属化層やめつきによる銅層等の金属層
が形成されていないことである。
What is important in this embodiment is that the surface of the alumina plate 2 on which no electric circuit is formed is exposed to the outside, and that the exposed surface of the alumina plate 2 comes into direct contact with the heat dissipation means when a hybrid IC is used. No. 2, the surface on which no electric circuit is formed has no metal layer such as the above-mentioned metallized layer or copper layer formed by bonding.

本実施例によれば、アルミナ板2が金属支持板1に接着
されておらず、直接放熱手段に接触する構造を有するた
め、前記実施例の場合よシ放熱性が向上するという効果
もある。しかも、アルミナ板2にはんだ伺けされる金属
部材は金属板3のみで、接着層が少ない簡素化された構
造になるため耐ヒートサイクル性も高い。
According to this embodiment, since the alumina plate 2 is not bonded to the metal support plate 1 and has a structure in which it directly contacts the heat radiating means, there is also the effect that heat dissipation is improved compared to the case of the previous embodiment. Furthermore, the metal plate 3 is the only metal member that is soldered to the alumina plate 2, resulting in a simplified structure with fewer adhesive layers, and therefore has high heat cycle resistance.

次に、本発明の各種変形例について例示する。Next, various modified examples of the present invention will be illustrated.

本発明は上述した実施例の外、種々の態様にて実施する
ことが可能である。
The present invention can be implemented in various embodiments other than the embodiments described above.

まず、無機質絶縁部材としては、アルミナの外室化アル
ミニウム(A2N)、窒化硼素(BN)、炭化シリコン
(SiC)、窒化シリコン(Si3N4)、酸化ベリリ
ウム(Bed)等、あるいはこれらを成分として含む混
合物等が使用できる。この際、金属化層としては蒸着法
のごとき方法で形成されたクロム−ニッケル・銀、クロ
ム−銅−金、チタン−ニッケルー銀のような多層積層金
属膜が有効である外、無機質絶縁部材が炭化シリコンの
場合はモリブデン−タングステン系ペースト焼料法(乾
式法)によ“る金属層や銅−マンガン共晶合金で銅箔を
接着したような金属層でもよい。また、無機質絶縁部材
がアルミナでおる場合でも、前述の多層積層金属膜やモ
リブデン−タングステンペースト焼付法(乾式法)によ
る金属層を用いてもよい。
First, as an inorganic insulating material, alumina aluminum (A2N), boron nitride (BN), silicon carbide (SiC), silicon nitride (Si3N4), beryllium oxide (Bed), etc., or a mixture containing these as components. etc. can be used. In this case, multilayer metal films such as chromium-nickel-silver, chromium-copper-gold, and titanium-nickel-silver formed by a method such as vapor deposition are effective as the metallization layer, as well as inorganic insulating materials. In the case of silicon carbide, a metal layer formed by a molybdenum-tungsten paste firing method (dry method) or a metal layer bonded with copper foil using a copper-manganese eutectic alloy may also be used. Even in the case where the metal layer is formed by a multi-layer laminated metal film or a metal layer formed by a molybdenum-tungsten paste baking method (dry method), it is also possible to use the metal layer described above.

金属化層上に形成する金属層は金属化層上に直接形成さ
れてもよいが、例えは、ニッケル層をめっき法等により
形成した後、このニッケル層上に設けても何等支障はな
い。なお、金属化層を銅層とした場合、保存時の銅層表
面の変質を防止するために、銅層上にニッケル等の金属
?被覆しておくことは好ましいことである。接着に用い
るはんだとしては、40%鉛−60チ錫の組成の外、例
えば95%鉛−5%錫のもの、おるいはこれらに第3成
分として銀等を含むものが使用できる。その厚さも0.
1(mm〕に限られず、それよシ厚くても薄くても良い
。一般にはんだ層が厚いと熱歪を良く吸収するが、はん
だそのものの熱伝導率がさほど高くないことから、混成
ICの熱放散性は低下する。上述の実施例のように銅め
っきを施して複合化した無機質絶縁部材を使用すること
によって熱歪の発生を抑制し得るから、はんだ層の厚さ
を効果的に減少し混成ICの熱放散性を高め得たことも
、本発明の効果である。
The metal layer formed on the metallized layer may be formed directly on the metallized layer, but for example, it may be formed on the nickel layer after forming a nickel layer by a plating method or the like without any problem. In addition, when the metallized layer is a copper layer, in order to prevent deterioration of the surface of the copper layer during storage, a metal such as nickel may be placed on the copper layer. It is preferable to keep it coated. As the solder used for bonding, in addition to the composition of 40% lead-60% tin, for example, a composition of 95% lead-5% tin, or a solder containing silver or the like as a third component can be used. Its thickness is also 0.
The thickness is not limited to 1 (mm) and may be thicker or thinner.Generally, a thicker solder layer absorbs thermal distortion better, but since the thermal conductivity of the solder itself is not very high, the heat of the hybrid IC The dissipation performance is reduced.By using a composite inorganic insulating material with copper plating as in the above embodiment, the occurrence of thermal strain can be suppressed, so the thickness of the solder layer can be effectively reduced. Another advantage of the present invention is that the heat dissipation properties of the hybrid IC can be improved.

次に、金属板上に載置される半導体基体の種類および回
路構成については、任意の半導体素子(シリコン以外の
半導体を用いたものを含む)、および回路について適用
できることはいうまでもない。
Next, it goes without saying that the present invention can be applied to any semiconductor element (including those using semiconductors other than silicon) and circuits as to the type of semiconductor substrate placed on the metal plate and the circuit configuration.

さらに、金属板や金属支持板として、例えば銅とインド
(鉄−36%ニッケル合余)を直接一体化した複合金属
板や炭素繊維を含む銅板等の複合材料を用いるととも有
効である。この場合の複合金属板や複合材料は熱膨張係
数が無機質絶縁部材のそれに近い側に調節されているた
め、はんだ層に生ずる熱歪が軽微になり、耐ヒートサイ
クル性が一層向上するからである。
Furthermore, it is also effective to use a composite material such as a composite metal plate made by directly integrating copper and India (iron-36% nickel mixture) or a copper plate containing carbon fibers as the metal plate or metal support plate. In this case, the thermal expansion coefficient of the composite metal plate or composite material is adjusted to be close to that of the inorganic insulating material, so the thermal distortion that occurs in the solder layer becomes slight, and the heat cycle resistance is further improved. .

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明によれば、平板上無機質無
縁物の少なくとも一方の面上に形成した金属化層上に金
属層を形成し、これに半導体基体塔載用金属板を金属ろ
うをもって接着したので、熱歪に基く変性あるいは破損
の恐れがない改善された絶縁型半導体装置を提供できる
効果がある。
As explained above, according to the present invention, a metal layer is formed on the metallized layer formed on at least one surface of the flat inorganic inorganic material, and a metal plate for mounting a semiconductor substrate is attached to the metal layer using a metal solder. Since they are bonded together, it is possible to provide an improved insulated semiconductor device with no fear of deterioration or damage due to thermal strain.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明に係る絶縁型半導体装置の実施例を示す
斜視図、第2図は第1図の構造によって得られる電気回
路を示す回路図、第3図は本発明の一実施例の要部を示
す断面図、第4図は本発明の一実施例囚を従来例■の無
機質絶縁部材の接着面積に対する混成ICの故障発生率
の関係を示すグラフ、第5図は本発明の他の実施例の要
部を示す断面図である。 1・・・金属支持板、2・・・アルミナ板、3・・・金
属板。 鱗 1菌 某20 41θ3         qllJコ¥3図 / 14図 竿り閃
FIG. 1 is a perspective view showing an embodiment of an insulated semiconductor device according to the present invention, FIG. 2 is a circuit diagram showing an electric circuit obtained by the structure of FIG. 1, and FIG. 4 is a cross-sectional view showing the main parts, FIG. 4 is a graph showing the relationship between the failure rate of a hybrid IC and the bonding area of the inorganic insulating member of conventional example ①, and FIG. FIG. 2 is a sectional view showing the main parts of the embodiment. 1... Metal support plate, 2... Alumina plate, 3... Metal plate. Scale 1 bacteria certain 20 41θ3 qllJ Ko ¥3 figure / 14 figure rod flash

Claims (1)

【特許請求の範囲】 1、金属板上に半導体基体を導電的に接着し、かつ該金
属板に、これとは絶縁された配線用金属片を有する配線
部材を接着し、前記半導体基体の該金属板とは反対側の
面に形成された電気領域を前記配線用金属片に電気的に
接続してなる半導体装置において、前記金属板は、平板
状無機質絶縁物の少なくとも一方の面上に形成された金
属化層上に金属層を形成してなる複数無機質絶縁部材の
前記金属層に、金属ろうをもって接着されたことを特徴
とする絶縁型半導体装置。 2、特許請求の範囲第1項記載の絶縁型半導体装置にお
いて、前記平板状無機質絶縁物はアルミナ板であること
を特徴とする絶縁型半導体装置。 3、特許請求の範囲第1項記載の絶縁型半導体装置にお
いて、前記金属化層は、前記平板状絶縁物の少なくとも
一方の面にモリブデン又はタングステンを焼結して形成
したことを特徴とする絶縁型半導体装置。
[Claims] 1. A semiconductor substrate is conductively bonded onto a metal plate, and a wiring member having a wiring metal piece insulated from the metal plate is bonded to the metal plate, and the semiconductor substrate is bonded to the semiconductor substrate. In a semiconductor device in which an electrical region formed on a surface opposite to the metal plate is electrically connected to the wiring metal piece, the metal plate is formed on at least one surface of the flat inorganic insulator. An insulated semiconductor device, characterized in that the insulated semiconductor device is bonded to the metal layer of a plurality of inorganic insulating members formed by forming a metal layer on a metallized layer using a metal solder. 2. The insulated semiconductor device according to claim 1, wherein the flat inorganic insulator is an alumina plate. 3. The insulated semiconductor device according to claim 1, wherein the metallized layer is formed by sintering molybdenum or tungsten on at least one surface of the flat insulator. type semiconductor device.
JP58048882A 1983-03-25 1983-03-25 Insulated type semiconductor device Pending JPS59175733A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58048882A JPS59175733A (en) 1983-03-25 1983-03-25 Insulated type semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58048882A JPS59175733A (en) 1983-03-25 1983-03-25 Insulated type semiconductor device

Publications (1)

Publication Number Publication Date
JPS59175733A true JPS59175733A (en) 1984-10-04

Family

ID=12815651

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58048882A Pending JPS59175733A (en) 1983-03-25 1983-03-25 Insulated type semiconductor device

Country Status (1)

Country Link
JP (1) JPS59175733A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0434264A2 (en) * 1989-12-22 1991-06-26 Westinghouse Electric Corporation Package for power semiconductor components

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0434264A2 (en) * 1989-12-22 1991-06-26 Westinghouse Electric Corporation Package for power semiconductor components
US5814880A (en) * 1989-12-22 1998-09-29 Northrop Grumman Corporation Thick film copper metallization for microwave power transistor packages

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