JPH11233671A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH11233671A
JPH11233671A JP10027500A JP2750098A JPH11233671A JP H11233671 A JPH11233671 A JP H11233671A JP 10027500 A JP10027500 A JP 10027500A JP 2750098 A JP2750098 A JP 2750098A JP H11233671 A JPH11233671 A JP H11233671A
Authority
JP
Japan
Prior art keywords
copper plate
stress
thickness
insulating substrate
terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP10027500A
Other languages
Japanese (ja)
Inventor
Akira Morozumi
両角  朗
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP10027500A priority Critical patent/JPH11233671A/en
Publication of JPH11233671A publication Critical patent/JPH11233671A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • H01L2924/13055Insulated gate bipolar transistor [IGBT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Abstract

PROBLEM TO BE SOLVED: To suppress the stress acting on ceramics and to prevent the deterioration of insulation owing to a crack by providing the junction part of an outer lead-through terminal and one copper plate by means of solder on a side further inside than the edge of the copper plate by a specified dimension. SOLUTION: Copper plates 2b and 2c are stuck on both faces of a ceramics substrates 2a (thickness of 0.635 mm). A semiconductor chip 3 is mounted on a copper plate 2c (thickness of 0.3 mm). The other copper plate 2b (thickness 0.2 mm) is fixed to the inner side of a heat discharge metal base 1. An outer lead-through terminal 4 is mounted on the copper plate 2c. The junction part of the outer lead-through terminal 4 and the copper plate 2c by solder is set to the side further inside than the edge of the copper plate 2c by at least 3 mm. Thus, maximum main stress deteriorates as the position of the solder connection part of the terminal becomes further than the edge part of the copper plate, and generated stress becomes 130 Mpa by setting it further into the inner side by 3 mm from the edge part. The stress generated is not more than the breaking stress of ceramics (aluminum nitride), and substrate damage can be prevented.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、モータ制御、エア
コン等のインバータあるいはNC制御等に用いられるパ
ワーモジュールのように、表面に銅板(銅箔)が張られ
たセラミックスからなる絶縁基板上に半導体素子が実装
される半導体装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device on a ceramic insulating substrate having a copper plate (copper foil) on its surface, such as a motor control, an inverter for an air conditioner or the like, or a power module used for NC control. The present invention relates to a semiconductor device on which elements are mounted.

【0002】[0002]

【従来の技術】近年の電力変換・制御技術を主とするパ
ワーエレクトロニクスの発展にはめざましいものがあ
り、産業,交通,情報および民生などの分野で適用が拡
がっている。このパワーエレクトロニクスを支えている
のはパワーデバイスであり、今日のパワーデバイスの主
要素子であるIGBTは、年々大容量化が進んできてい
る。特に大容量電力変換の一つである鉄道車両分野では
電力変換装置のIGBT化の進展が著しい。
2. Description of the Related Art In recent years, there has been a remarkable development in power electronics mainly in power conversion and control technology, and applications thereof have been expanding in fields such as industry, transportation, information and consumer use. Power devices support the power electronics, and IGBTs, which are the main elements of today's power devices, have been increasing in capacity year by year. Particularly in the field of railway vehicles, which is one type of large-capacity power conversion, the use of IGBTs in power conversion devices has been remarkably progressing.

【0003】一方、地球環境問題が厳しくなるなかで、
クリーンな電気エネルギは、今後ますます需要が増大し
ていくことと思われ、太陽光,風力,燃料電池など新エ
ネルギ発電の実用化や電気自動車の普及により、装置の
大容量化,分散化などが進み、高性能な電力変換装置が
ますます必要性を増していくことは確実である。このよ
うな市場環境は、パワーモジュールのより一層の高機能
・高性能・高信頼度の必要性をも意味しており、特に高
信頼度においては、市場におけるトラブルの際には悪い
な事態を招く可能性があるため、パワーモジュールにお
けるパッケージの信頼性設計が重要である。
[0003] On the other hand, as global environmental problems become more severe,
The demand for clean electric energy is expected to increase further in the future, and practical use of new energy generation such as solar, wind, and fuel cells and the spread of electric vehicles will increase the capacity and decentralization of equipment. And the need for high-performance power converters will surely increase. Such a market environment also implies a need for higher performance, higher performance, and higher reliability of power modules. Particularly in high reliability, bad situations occur in the event of a trouble in the market. Therefore, it is important to design the reliability of the package in the power module.

【0004】図2はIGBTを搭載したパワートランジ
スタモジュールの構成断面図である。図2において、放
熱金属ベース1上にはんだ等で固着された絶縁基板2
と、この上にマウントされたIGBT等の半導体チップ
3と、先端部が絶縁基板2の表面銅板2cの回路パター
ンにはんだ付けされた外部導出端子4と、複数の外部導
出端子4を相互固定する蓋8と、半導体チップ3と外部
導出端子4の先端部が固着した回路パターンとをボンデ
ィングで接続するアルミワイヤ6と、放熱金属ベース1
と樹脂ケース5を接着剤等で固着し、その内部空間に充
填されたシリコーンのゲル状樹脂7とを有している。そ
して、必要に応じてゲル状樹脂7上をさらにエポキシの
封止樹脂で閉塞する。また、外部導出端子4は、蓋8か
ら導出する他に樹脂ケース5から導出するようにしても
よい。
FIG. 2 is a sectional view showing the configuration of a power transistor module on which an IGBT is mounted. In FIG. 2, an insulating substrate 2 fixed on a heat dissipating metal base 1 with solder or the like.
And a semiconductor chip 3 such as an IGBT mounted thereon, an external lead terminal 4 whose tip is soldered to a circuit pattern of a surface copper plate 2c of the insulating substrate 2, and a plurality of external lead terminals 4 mutually fixed. An aluminum wire 6 for bonding the lid 8, a semiconductor chip 3 and a circuit pattern to which the tip of the external lead-out terminal 4 is fixed, and a heat dissipating metal base 1;
And a resin case 5 fixed with an adhesive or the like, and a silicone gel resin 7 filled in the internal space. Then, if necessary, the top of the gel resin 7 is closed with an epoxy sealing resin. The external lead-out terminal 4 may be led out of the resin case 5 in addition to the lead-out terminal 4.

【0005】ここで、絶縁基板2は、アルミナ(Al2
3 )又は窒化アルミニウム(AlN)等のセラミック
ス基板2aに対し、その表裏面に箔状の薄い銅板2b,
2cを例えばダイレクトボンド・カッパ−法(接合材を
用いずに銅と微量の酸素との反応により生成するCu−
O共晶液相を接合剤として用いて直接反応により接合す
る方法)により直接接合したものであり、主面側(表面
側)の銅板2cに回路パターン(厚膜回路パターン)が
形成されている。セラミックス基板2aは、その優れた
絶縁性(体積固有抵抗>1014Ω・cm2 )と、絶縁材
料の中では熱放散が良好(熱伝導率:20〜200W/
mK)であるといった特徴が備わった材料である。パワ
ーモジュール用のセラミックス基板は、厚さ0.25〜
0.8mm程度のセラミックス板の表裏に厚さ0.2〜
0.3mm程度の銅板を接合した構造が一般的である。
このセラミックス板と銅板との接合には、前記接合法の
他に、チタンやジルコニウム等の活性金属を添加したろ
う材を用いる活性金属接合法が適用されている。ダイレ
クトボンド・カッパー法は、主にアルミナ等の酸化物系
セラミックスに用いられ、活性金属接合法は、窒化アル
ミニウム等の窒化物系セラミックスに用いられる。被接
合材の銅は、ダイレクトボンド・カッパー法には無酸素
銅またはタフピッチ銅が、活性金属接合法には無酸素銅
がそれぞれ用いられている。また、銅の他にアルミニウ
ムを用いたものもある。
Here, the insulating substrate 2 is made of alumina (Al 2
O 3) or to the ceramic substrate 2a such as aluminum nitride (AlN), foil thin copper plates 2b on the front and back surfaces,
2c is produced, for example, by direct bond kappa method (Cu-forming by a reaction between copper and a small amount of oxygen without using a bonding material).
(A method of bonding by direct reaction using an O eutectic liquid phase as a bonding agent), and a circuit pattern (thick film circuit pattern) is formed on the copper plate 2c on the main surface side (front surface side). . The ceramic substrate 2a has excellent insulating properties (volume resistivity> 10 14 Ω · cm 2 ) and good heat dissipation among insulating materials (thermal conductivity: 20 to 200 W /
mK). The ceramic substrate for the power module has a thickness of 0.25 to
0.8mm thickness on the front and back of ceramic plate of about 0.8mm
A structure in which a copper plate of about 0.3 mm is bonded is general.
For joining the ceramic plate and the copper plate, an active metal joining method using a brazing material to which an active metal such as titanium or zirconium is added is applied in addition to the joining method described above. The direct bond copper method is mainly used for oxide ceramics such as alumina, and the active metal bonding method is used for nitride ceramics such as aluminum nitride. As the copper to be joined, oxygen-free copper or tough pitch copper is used for the direct bond copper method, and oxygen-free copper is used for the active metal joining method. In addition, there is one using aluminum in addition to copper.

【0006】図2に示したパッケージ構造では、半導体
チップ3の下面電極(コレクタ)と放熱金属ベース1は
絶縁基板2により絶縁され、3000〜6000Vの絶
縁耐圧が確保されている。また、パッケージ材料は、金
属,セラミックスおよびプラスチック等さまざまな物性
が用いられており、特に熱膨張係数に関しては、半導体
チップ3より下層に向かって大きくなるような積層構成
となっている。
In the package structure shown in FIG. 2, the lower electrode (collector) of the semiconductor chip 3 and the heat dissipating metal base 1 are insulated by the insulating substrate 2, and a withstand voltage of 3000 to 6000 V is secured. Further, various physical properties such as metal, ceramics, and plastic are used for the package material. In particular, the package has a laminated structure in which the thermal expansion coefficient increases toward the lower layer from the semiconductor chip 3.

【0007】このように、パワーモジュールのパッケー
ジ技術は、半導体チップ3の性能を最大限に生かしなが
ら、これに信頼性を含めた各種性能を付加し、市場要求
に応えられる形にまとめあげられている。パワーモジュ
ールの信頼性において、パッケージには各種接合部信頼
性や絶縁信頼性等が必要である。はんだ接合部では、構
造部品材料間の熱膨張係数差に起因して発生する熱応力
により、はんだにひずみが生じる。はんだに許容値を超
えて過大なひずみが加わるとはんだ部に亀裂が発生し、
熱応力の繰り返しにより亀裂は進展する。この亀裂の進
展は、半導体チップ3下及び絶縁基板2下のはんだで
は、熱抵抗の増大を招き放熱効果の低下を生じ、半導体
チップ3を破壊に至らしめる。また、端子接合部のはん
だにおいては、端子取れ(端子オープン)に至ることに
なる。
As described above, the package technology of the power module is summarized in such a form that it can respond to market demands by adding various performances including reliability while maximizing the performance of the semiconductor chip 3. . Regarding the reliability of the power module, the package needs various kinds of joint reliability and insulation reliability. At the solder joint, the solder is distorted by thermal stress generated due to the difference in thermal expansion coefficient between the structural component materials. If excessive strain is applied to the solder beyond the allowable value, cracks will occur in the solder,
The crack grows by repeated thermal stress. The propagation of the cracks causes an increase in thermal resistance and a decrease in the heat radiation effect in the solder under the semiconductor chip 3 and under the insulating substrate 2, resulting in destruction of the semiconductor chip 3. In addition, in the soldering of the terminal joining portion, the terminal is detached (terminal open).

【0008】一方、絶縁基板2は、半導体チップ3の直
下に位置しており、そのため絶縁基板2は、半導体チッ
プ3実装のための基体,半導体チップ3発熱時の熱放
散,対地間絶縁の確保及び半導体チップ電極と外部電極
間接続のための中継体としての機能を具備する必要があ
る。絶縁基板2には、熱膨張係数の異なる半導体チップ
3や金属(銅)ベースが接合されるため、組立工程内の
熱履歴や実稼動での動作ならびに使用環境の温度変化に
より、熱応力が発生する。そのため、絶縁基板2に、こ
れら発生応力に耐えられる機械的特性が要求される。そ
して、セラミックスの破壊は、そのほとんどが引張応力
の作用によって起こり、しかもこの応力は、冷却時だけ
でなく昇温時においても発生する。このため、一般的に
行われている曲げ強度評価の他に、高温引張強度の評価
も重要である。特にシミュレーションによる応力解析に
おいて引張強度値は、真の強度であること等より、曲げ
強度値を用いた場合よりも精度の高い強度設計を行うこ
とができ、重要な特性である。
On the other hand, the insulating substrate 2 is located immediately below the semiconductor chip 3. Therefore, the insulating substrate 2 is a base for mounting the semiconductor chip 3, dissipates heat when the semiconductor chip 3 generates heat, and ensures insulation between the semiconductor chip 3 and the ground. In addition, it is necessary to have a function as a relay for connection between the semiconductor chip electrode and the external electrode. Since the semiconductor chip 3 and the metal (copper) base having different coefficients of thermal expansion are joined to the insulating substrate 2, thermal stress is generated due to heat history in the assembly process, operation in actual operation, and temperature change in the use environment. I do. Therefore, the insulating substrate 2 is required to have mechanical properties that can withstand the generated stress. Most of the breakdown of ceramics is caused by the action of tensile stress, and this stress occurs not only at the time of cooling but also at the time of temperature rise. For this reason, it is important to evaluate the high-temperature tensile strength in addition to the commonly performed bending strength evaluation. In particular, in the stress analysis by simulation, the tensile strength value is a true strength, so that it is possible to perform a strength design with higher accuracy than in the case of using the bending strength value, which is an important characteristic.

【0009】図3は、各種セラミックスにおける高温引
張強度の評価結果を示した図である。図3より、窒化ア
ルミニウム等の窒化物系セラミックスは、アルミナ等の
酸化物系セラミックスに比べて、高温域での強度低下が
少ないことが分かる。また、これらのなかで、窒化アル
ミニウムは特に強度が低いことが分かる。半導体チップ
3で発生した熱流束は、セラミックス基板2aを経由し
て放熱金属ベース1に伝えられ、放熱フィンに逃がされ
る。このため、モジュールの低熱抵抗化には、大量の熱
流束を放熱金属ベース1に移動させる必要があることよ
り、セラミックス基板2aには、高熱伝導・高熱放散性
が求められる。このため、低熱抵抗化には、窒化アルミ
ニウム等熱伝導率の高いセラミックスの適用や、セラミ
ックス板の薄板化等が行われている。
FIG. 3 is a diagram showing the evaluation results of high-temperature tensile strength of various ceramics. From FIG. 3, it can be seen that the nitride ceramics such as aluminum nitride have less decrease in strength in a high temperature region than the oxide ceramics such as alumina. Also, it can be seen that among these, aluminum nitride has particularly low strength. The heat flux generated in the semiconductor chip 3 is transmitted to the radiating metal base 1 via the ceramic substrate 2a, and is released to the radiating fins. For this reason, it is necessary to transfer a large amount of heat flux to the heat-dissipating metal base 1 in order to reduce the thermal resistance of the module. Therefore, the ceramic substrate 2a is required to have high heat conduction and high heat dissipation. For this reason, to reduce the thermal resistance, ceramics having high thermal conductivity, such as aluminum nitride, have been applied, and ceramic plates have been made thinner.

【0010】[0010]

【発明が解決しようとする課題】従来は、特開平5−1
66969号公報に記載されているように、組立熱履歴
で絶縁基板に亀裂の発生するのを防ぐために、セラミッ
ク基板の端面と銅箔の縁との関係について研究が成され
ていた。しかし、回路パターンとその上にはんだによっ
て固着する外部導出端子との関係については考慮されて
いなかった。また、モジュールの小形化のために絶縁基
板も小形化が図られたので、絶縁基板上の外部導出端子
とのはんだ接合部の回路パターンもはんだ接合面積しか
確保されていなかった。
Conventionally, Japanese Unexamined Patent Application Publication No.
As described in Japanese Patent No. 66969, a study has been made on the relationship between the end face of the ceramic substrate and the edge of the copper foil in order to prevent the insulating substrate from cracking due to the heat history of assembly. However, no consideration has been given to the relationship between the circuit pattern and an external lead-out terminal fixed on the circuit pattern by soldering. In addition, since the size of the insulating substrate has been reduced in order to reduce the size of the module, the circuit pattern of the solder bonding portion with the external lead-out terminal on the insulating substrate has only a solder bonding area.

【0011】図4は外部導出端子の固着部分の断面図で
ある。この図4の構造における熱応力解析(二次元弾性
解析)を行ったところ、銅板2c端部のセラミックス基
板2aとの接合界面であるA点に集中応力が発生してい
ることが分かった。この応力について表したのが図5で
ある。図5は外部導出端子の接合部の部分拡大図であ
り、(a)は常温での状態図であり、(b)は昇温での
状態図であり、(c)は降温での状態図である。回路パ
ターン側において、温度サイクルの昇温過程(233K
〜398K)では圧縮,降温過程(398K〜298
K)では引張りの応力が働いている。温度サイクルによ
る基板損傷は、降温過程において熱膨張係数差によりモ
ジュール全体が変形し、外部導出端子に引張応力が作用
するため、端子はんだ接合部近傍のセラミックス表面に
は、モジュールの変形に伴う一様な引張応力に加えて、
外部導出端子の引張作用に伴う局所的な引張応力が作用
することになる。これら応力が破壊強度に達し、基板損
傷に至る場合がある。
FIG. 4 is a sectional view of a portion where the external lead-out terminal is fixed. When thermal stress analysis (two-dimensional elasticity analysis) was performed on the structure of FIG. 4, it was found that concentrated stress was generated at point A, which is a bonding interface between the end of the copper plate 2c and the ceramic substrate 2a. FIG. 5 shows this stress. FIGS. 5A and 5B are partially enlarged views of the joining portion of the external lead-out terminal. FIG. 5A is a state diagram at normal temperature, FIG. 5B is a state diagram at elevated temperature, and FIG. It is. On the circuit pattern side, the temperature rise process of the temperature cycle (233K
398K to 398K) during compression and cooling (398K to 298K).
In K), tensile stress is acting. Substrate damage due to temperature cycling is caused by the difference in thermal expansion coefficient during the cooling process, and the entire module is deformed, and a tensile stress is applied to the external lead terminals. In addition to high tensile stress,
A local tensile stress acts on the external lead terminal due to the tensile action. These stresses may reach the breaking strength and damage the substrate.

【0012】図6は、窒化アルミニウムの絶縁基板に外
部導出端子を実装した状態での温度サイクル試験後の断
面図である。図6において、窒化アルミニウムのセラミ
ックス基板2aは、セラミックスの厚さが0.635m
mであり、外部導出端子4が搭載される一面側の銅板2
Cの厚さが0.3mmであり、他面側の銅板の厚さが
0.2mmである。この絶縁基板について、−40℃で
1時間,常温(23〜25℃)で30分,125℃で1
時間,常温で30分を1サイクルとして温度サイクル試
験を行ったところ、100サイクルで外部導出端子4の
はんだ接合部直下のセラミックス部分に、面方向に平行
なクラックBの発生が見られた。このクラックは、銅板
2cとセラミックス基板2aとの接合界面の銅板縁部を
起点に基板中央部に向かって進展している。
FIG. 6 is a cross-sectional view after a temperature cycle test in a state where an external lead terminal is mounted on an aluminum nitride insulating substrate. In FIG. 6, an aluminum nitride ceramic substrate 2a has a ceramic thickness of 0.635 m.
m, the copper plate 2 on one side on which the external lead-out terminal 4 is mounted
The thickness of C is 0.3 mm, and the thickness of the copper plate on the other side is 0.2 mm. The insulating substrate was heated at -40 ° C for 1 hour, at room temperature (23 to 25 ° C) for 30 minutes, and at 125 ° C for 1 hour.
When a temperature cycle test was performed for one cycle of 30 minutes at time and normal temperature, cracks B parallel to the surface direction were observed in the ceramic portion immediately below the solder joint of the external lead-out terminal 4 in 100 cycles. The crack extends from the edge of the copper plate at the joint interface between the copper plate 2c and the ceramic substrate 2a toward the center of the substrate.

【0013】この基板損傷は、絶縁耐圧の低下を引き起
こすものではないが、鉄道系車両に搭載されるCVC
F,VVVF等のコンバータ・インバータに用いられる
パワーモジュールでは前記試験で行われたような動作環
境を想定して考慮する必要がある。高信頼性パワーモジ
ュールにおける、より一層の絶縁信頼性の向上を図るた
めには、基板損傷を防ぐ構造として、(1)高強度のセ
ラミックス基板の採用,(2)低熱膨張・高弾性率ベー
ス材の採用,(3)絶縁基板への外部導出端子のはんだ
接続の廃止,(4)応力緩和・吸収効果のある外部導出
端子形状等が考えられる。しかし、前記(1)及び
(2)は、高価な材料を使わなければならず、コストア
ップの要因となり、(3)及び(4)は、内部配線の引
き回しが複雑になるため、内部インダクタンスの上昇に
伴うスイッチング速度等の電気特性に影響を及ぼすとい
う課題がある。
Although this substrate damage does not cause a decrease in the dielectric strength, the CVC mounted on the railway vehicle
In a power module used for a converter / inverter such as F, VVVF, etc., it is necessary to consider the operating environment as performed in the above test. In order to further improve the insulation reliability of the high reliability power module, (1) use of a high-strength ceramic substrate, (2) low thermal expansion and high elastic modulus base material as a structure to prevent substrate damage , (3) abolition of the solder connection of the external lead-out terminal to the insulating substrate, (4) a shape of the external lead-out terminal having a stress relaxation / absorption effect. However, the above (1) and (2) require the use of an expensive material, which causes an increase in cost, and (3) and (4) complicate the routing of the internal wiring. There is a problem in that electrical characteristics such as switching speed due to the rise are affected.

【0014】この発明の目的は、前記の課題を解決し
て、絶縁基板への外部導出端子のはんだ接続を有する構
造で絶縁劣化を防止し、絶縁信頼性を向上させることに
ある。
An object of the present invention is to solve the above-mentioned problems and to prevent insulation deterioration in a structure having a solder connection of an external lead-out terminal to an insulating substrate and improve insulation reliability.

【0015】[0015]

【課題を解決するための手段】前記の目的を達成するた
めに、絶縁樹脂製のケース枠と、このケース枠の一方の
開口を閉塞する金属製の放熱ベースと、セラミックスか
らなる平板の両面に銅板が張られ一面の銅板上に半導体
素子が実装され他面の銅板が前記放熱ベースの内面に固
着された絶縁基板と、前記一面の銅板上に実装されて外
部に導出される外部導出端子と、前記絶縁基板を封止す
る樹脂封止材と、前記ケース枠の他方の開口を閉塞する
蓋とを有してなる半導体装置において、外部導出端子と
前記一面の銅板とのはんだによる接合部が銅板の縁より
少なくとも3mm内側であることとする。
In order to achieve the above object, a case frame made of an insulating resin, a metal heat dissipation base for closing one opening of the case frame, and a flat plate made of ceramic are provided on both surfaces. An insulating substrate on which a copper plate is stretched and a semiconductor element is mounted on one surface of the copper plate and the other surface of the copper plate is fixed to the inner surface of the heat dissipation base; and an external lead-out terminal mounted on the one surface of the copper plate and led out. In a semiconductor device having a resin sealing material for sealing the insulating substrate and a lid for closing the other opening of the case frame, a joint portion of the external lead-out terminal and the one-side copper plate by soldering is provided. It shall be at least 3 mm inside the edge of the copper plate.

【0016】また、絶縁基板は窒化アルミニウムとし、
セラミックス基板の厚さが0.25〜0.8mmであ
り、銅板の厚さが0.2〜0.3mmとする。この発明
の構成によれば、セラミックスに作用する応力を、セラ
ミックスの破壊応力以下に抑えることができ、絶縁劣化
を防止することができる。
Also, the insulating substrate is made of aluminum nitride,
The thickness of the ceramic substrate is 0.25 to 0.8 mm, and the thickness of the copper plate is 0.2 to 0.3 mm. According to the configuration of the present invention, the stress acting on the ceramic can be suppressed to be equal to or less than the fracture stress of the ceramic, and the deterioration of insulation can be prevented.

【0017】[0017]

【発明の実施の形態】図1はこの発明の実施例のパッケ
ージ構造における外部導出端子と銅板とのはんだによる
接合部と銅板(回路パターン)端部からの距離(X)を
種々変えてのセラミックス基板の最大主応力を表した図
である。用いたセラミックス基板は窒化アルミニウムで
あり、その厚さはセラミックス基板が0.635mmで
あり、外部導出端子が搭載される一面側の銅板の厚さが
0.3mmであり、他面側の銅板の厚さが0.2mmで
ある。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a ceramic structure of a package structure according to an embodiment of the present invention, in which a solder joint between an external lead-out terminal and a copper plate and a distance (X) from an end of the copper plate (circuit pattern) are variously changed. FIG. 3 is a diagram illustrating a maximum principal stress of a substrate. The ceramic substrate used was aluminum nitride, the thickness of the ceramic substrate was 0.635 mm, the thickness of the copper plate on one surface on which the external lead-out terminals were mounted was 0.3 mm, and the thickness of the copper plate on the other surface was The thickness is 0.2 mm.

【0018】図1において、端子のはんだ接続部の位置
が銅板縁部より内側になるのに従って最大主応力が低下
しており、縁部より3mm内側とすることにより発生応
力が130MPaとなる。この発生応力はセラミックス
(窒化アルミニウム)の破壊応力以下になり、基板損傷
を防止できた。
In FIG. 1, the maximum principal stress decreases as the position of the solder connection part of the terminal is located inside the edge of the copper plate, and the generated stress becomes 130 MPa when it is located 3 mm inside the edge. This generated stress was equal to or less than the breaking stress of ceramics (aluminum nitride), thereby preventing damage to the substrate.

【0019】[0019]

【発明の効果】この発明によれば、外部導出端子と銅板
とのはんだによる接合部を銅板の縁より3mm内側とす
ることで、セラミックスに作用する応力をセラミックス
の破壊応力以下に抑えることができ、クラックによる絶
縁劣化を防止することができた。
According to the present invention, the stress acting on the ceramics can be suppressed to below the breaking stress of the ceramics by setting the joint of the external lead-out terminal and the copper plate by solder to be 3 mm inside the edge of the copper plate. In addition, insulation deterioration due to cracks could be prevented.

【図面の簡単な説明】[Brief description of the drawings]

【図1】この発明の実施例のパッケージ構造における外
部導出端子と銅板とのはんだによる接合部と銅板端部か
らの距離(X)を種々変えてのセラミックス基板の最大
主応力を表した図
FIG. 1 is a diagram showing the maximum principal stress of a ceramic substrate when the distance (X) from a solder joint between an external lead terminal and a copper plate and an end of the copper plate in the package structure of the embodiment of the present invention is variously changed.

【図2】パワートランジスタモジュールの構成断面図FIG. 2 is a sectional view of the configuration of a power transistor module.

【図3】各種セラミックスにおける高温引張強度の評価
結果を示した図
FIG. 3 is a diagram showing evaluation results of high-temperature tensile strength of various ceramics.

【図4】外部導出端子の固着部分の断面図FIG. 4 is a sectional view of a fixing portion of an external lead-out terminal.

【図5】外部導出端子の接合部の部分拡大図で、(a)
は常温での状態図、(b)は昇温での状態図、(c)は
降温での状態図
FIG. 5 is a partially enlarged view of a joint portion of an external lead-out terminal, and (a).
Is a phase diagram at a normal temperature, (b) is a phase diagram at an elevated temperature, and (c) is a phase diagram at a decreased temperature.

【図6】窒化アルミニウムの絶縁基板に外部導出端子を
実装した状態での温度サイクル試験後の断面図
FIG. 6 is a cross-sectional view after a temperature cycle test in a state where an external lead terminal is mounted on an aluminum nitride insulating substrate.

【符号の説明】[Explanation of symbols]

1 放熱金属ベース 2 絶縁基板 2a セラミックス基板 2b 銅板 2c 銅板 3 半導体チップ 4 外部導出端子 5 樹脂ケース 6 アルミワイヤ 7 ゲル状樹脂 8 蓋 REFERENCE SIGNS LIST 1 heat radiation metal base 2 insulating substrate 2 a ceramic substrate 2 b copper plate 2 c copper plate 3 semiconductor chip 4 external lead-out terminal 5 resin case 6 aluminum wire 7 gel-like resin 8 lid

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】絶縁樹脂製のケース枠と、このケース枠の
一方の開口を閉塞する金属製の放熱ベースと、セラミッ
クスからなる平板の両面に銅板が張られ一面の銅板上に
半導体素子が実装され他面の銅板が前記放熱ベースの内
面に固着された絶縁基板と、前記一面の銅板上に実装さ
れて外部に導出される外部導出端子と、前記絶縁基板を
封止する樹脂封止材と、前記ケース枠の他方の開口を閉
塞する蓋とを有してなる半導体装置において、外部導出
端子と前記一面の銅板とのはんだによる接合部が銅板の
縁より少なくとも3mm内側であることを特徴とする半
導体装置。
1. A case frame made of an insulating resin, a metal heat dissipation base for closing one opening of the case frame, and a copper plate stretched on both sides of a flat plate made of ceramics, and a semiconductor element is mounted on one surface of the copper plate. An insulating substrate having a copper plate on the other surface fixed to the inner surface of the heat dissipation base, an external lead-out terminal mounted on the copper plate on the one surface and led out, and a resin sealing material for sealing the insulating substrate. A semiconductor device having a lid for closing the other opening of the case frame, wherein a solder joint between the external lead-out terminal and the one surface copper plate is at least 3 mm inside the edge of the copper plate. Semiconductor device.
【請求項2】絶縁基板のセラミックス基板が窒化アルミ
ニウムであることを特徴とする請求項1記載の半導体装
置。
2. The semiconductor device according to claim 1, wherein the ceramic substrate of the insulating substrate is aluminum nitride.
【請求項3】絶縁基板のセラミックス基板の厚さが0.
25〜0.8mmであることを特徴とする請求項1記載
の半導体装置。
3. The method according to claim 1, wherein the thickness of the ceramic substrate of the insulating substrate is 0.
2. The semiconductor device according to claim 1, wherein the thickness is 25 to 0.8 mm.
【請求項4】絶縁基板の銅板の厚さが0.2〜0.3m
mであることを特徴とする請求項1記載の半導体装置。
4. The thickness of a copper plate of an insulating substrate is 0.2 to 0.3 m.
2. The semiconductor device according to claim 1, wherein m is m.
JP10027500A 1998-02-09 1998-02-09 Semiconductor device Withdrawn JPH11233671A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10027500A JPH11233671A (en) 1998-02-09 1998-02-09 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10027500A JPH11233671A (en) 1998-02-09 1998-02-09 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH11233671A true JPH11233671A (en) 1999-08-27

Family

ID=12222874

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10027500A Withdrawn JPH11233671A (en) 1998-02-09 1998-02-09 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH11233671A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6690087B2 (en) * 2000-12-28 2004-02-10 Fuji Electric Co., Ltd. Power semiconductor module ceramic substrate with upper and lower plates attached to a metal base
JP2010021338A (en) * 2008-07-10 2010-01-28 Mitsubishi Electric Corp Semiconductor device, and method of manufacturing the same
CN110120375A (en) * 2014-05-20 2019-08-13 三菱电机株式会社 Power semiconductor apparatus

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6690087B2 (en) * 2000-12-28 2004-02-10 Fuji Electric Co., Ltd. Power semiconductor module ceramic substrate with upper and lower plates attached to a metal base
US6914325B2 (en) 2000-12-28 2005-07-05 Fuji Electric Co. Ltd. Power semiconductor module
JP2010021338A (en) * 2008-07-10 2010-01-28 Mitsubishi Electric Corp Semiconductor device, and method of manufacturing the same
CN110120375A (en) * 2014-05-20 2019-08-13 三菱电机株式会社 Power semiconductor apparatus

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