JPS59175258A - Alarm control circuit - Google Patents

Abstract

PURPOSE:To obtain suitably an alarm output even if normal state and failure state are repeated irregularly by subtracting a counter circuit at each clock in the normal state and applying addition to the counter circuit at each clock in the faild state. CONSTITUTION:When a state signal (a) restores to the normal state again with a count output (f) reaching (5), the count output (f) becomes (6) and an addition/ subtraction signal (e) changes to logical value (1) at the same time, an addition/ subtraction counter circuit CNT2 starts subtraction and the output (f) changes from (6) to (5). Further, when the failed state is reached again, the circuit CNT2 starts additive count again and the output (f) is increased sequentially. Thus, when the failed state stays longer than the normal state, the alarm state is obtained.

Description

[Detailed Description of the Invention] (a) Technical Field of the Invention The present invention relates to an alarm control circuit, and in particular, outputs an alarm accurately even when an input status signal changes irregularly from a normal state to a fault state. Regarding alarm control circuits.

Technical Background For example, a PCM communication channel accommodated in a digital trunk of a digital exchange transmits a status signal indicating the operating status of the PCM communication channel to the digital trunk, and if the system is operated normally, the status signal changes to a normal state. If an abnormality such as loss of synchronization occurs, the status signal is immediately set to a failure status. A digital trunk is a digital trunk whose status signal is changed from a normal state to a fault state for a predetermined period of time (for example, 1
00 milliseconds), an alarm is output to the digital switch. However, in some cases, the status signal does not simply change from a normal state to a fault state, but may repeat irregularly between the normal state and the fault state.

(0) Prior art and problems Figure 1 is a diagram showing an example of a conventional alarm control circuit.
FIG. 2 is a diagram showing an example of the operation process in FIG. 1. In FIGS. 1 and 2, when the status signal a indicates a normal state (logical value 0) and the alarm output signal d is set to a non-alarm state (logical value 0), the exclusive OR circuit E
The output signal of the OR is set to a logical value of 0, and the output signal of the counting circuit CNT
The logical value is inverted and inputted to the terminal E of l, and to the terminal G with its logical value inverted. In this state, the count output of the counting circuit CNTl is set to "2." which is input to the terminals DO to D3, and a carry signal C having a logic value of 0 is output from the terminal CO.

In such a condition, the condition signal officer indicates a fault condition (logical value 1
), the output signal of the exclusive OR circuit EOR changes to logical value 1.

As a result, the counting circuit CNT1 starts counting by the clock signal cp with one period of 8 milliseconds, and the count output increases from "2" by 1 every clock. When the count output reaches "14" in this way, a carry signal C with a logical value of 1 is output by the next clock signal cp, and the flip-flop FF
It is input to terminals J and K of I. As a result, the flip-flop FFI is clocked by the inverted clock signal CP input to the terminal CP, and outputs the alarm output signal d from the terminal Q to the alarm output state! Set i3 (logical value 1) 4ζ. As described above, the alarm output signal d becomes the alarm state 100 to 108 milliseconds after the state signal a changes to the fault state.

However, if the state signal a repeats the logic values 0 and 1 irregularly as shown in FIG. Since the count output bl of the counting circuit CNTl is set to "2" each time, the carry signal C° maintains the logical value of 0 forever, and the alarm output signal d" remains in the alarm state forever. Not reached.

As is clear from the above explanation, in the conventional V width control circuit, when the status signal a repeats the normal state and the failure state irregularly, the alarm output signal d does not reach the II alarm state until any time. It had

+d) Object of the Invention The object of the present invention is to eliminate the drawbacks of conventional alarm control circuits as described above, and to provide an alarm that accurately reaches the alarm state even when the status signal changes irregularly between the normal state and the fault state. The purpose is to realize a control circuit.

(e) Structure of the Invention The object of the present invention is to set an addition/subtraction switching signal to be transmitted to the addition/subtraction counting circuit when the input status signal indicates a fault state, and to set the addition/subtraction switching signal to be transmitted to the addition/subtraction counting circuit on the addition side when the input status signal indicates a normal state. means for setting the addition/subtraction switching signal to the subtracting side, adding 1 every clock when the addition/subtracting switching signal is set to the addition side, and adding 1 every clock when the addition/subtraction switching signal e is set to the subtracting side; an addition/subtraction counting circuit that subtracts 1 for each addition/subtraction counting circuit; and when the count output of the addition/subtraction counting circuit during addition reaches a predetermined first value, an alarm output circuit is activated and addition/subtraction counting of the addition/subtraction counting circuit is stopped; and means for resetting an alarm output circuit and stopping the subtraction counting of the addition/subtraction counting circuit when the count output of the addition/subtraction counting circuit during subtraction reaches a second value that is smaller than the first value. This is achieved by providing

(fl　Embodiments of the invention An embodiment of the present invention will be described below with reference to the drawings.

FIG. 3 is a diagram showing an alarm control circuit according to an embodiment of the present invention, FIGS. 4 and 5 are diagrams showing an example of the operation process in FIG. 3, and FIG. FIG. 5 shows a case where the state signal changes irregularly. Note that the same reference numerals indicate the same objects throughout the figures. In FIG. 3, the addition/subtraction counting circuit CNT2 outputs a signal to the terminal CP when the count prohibition signal i inputted to the terminal EN is set to the logical value O and the addition/subtraction switching signal e inputted to the terminal UD is set to the logical value O. Manual clock signal cp
Accordingly, 1 is added every 1 clock, and when the addition/subtraction switching signal e has a logical value of 1, 1 is subtracted every 1 clock. Further, when the count prohibition signal i is set to the logical value 1, the addition/subtraction counting circuit CNT2 stops counting both addition and subtraction. 5 and 4, when the state signal a is in a normal state (logical value 0), the flip-flop F
F2 is in a reset state, and an addition/subtraction switching signal e having a logical value of 1 is output from the terminal QN, making the gates 1-Gl conductive. Furthermore, if the count output f of the addition/subtraction counting circuit CNT 2 is a predetermined second count value "3", the gate G
3 outputs a second count value signal g with a logic value of 1, and the gate 1
-G6 becomes conductive, and is transmitted to gate G3 via gate Gl. As a result, a count prohibition signal i with a logic value of 1 is output from the gate G3, and the addition/subtraction counting circuit CN
T2 stops counting when the count output f is "3". Furthermore, the clock signal cp inverted by the inverting triple circuit lNV is applied to the terminal R of the flip-flop FF3.
6, the flip-flop FF3 becomes a reset state, and the alarm output signal d output from the terminal Q is set to a non-alarm state (logical value O). In such a state, status signal a indicates a fault! When it changes to @ (logical value 1), flip-flop FF2 is set in synchronization with clock signal cp, changes the addition/subtraction switching signal e to logical value 0, and changes the output signal from terminal Q to logical value l. . As a result, G)Gl is in a blocked state, G)G2 is in a conductive state,
The count prohibition signal i outputted from the gate G3 changes to a logical value of 0, the addition/subtraction counting circuit CNT2 starts addition and counting by the clock signal cp, and the count output f increases by 1 every clock from "3". When the count output f becomes "4", the second count value signal g changes to the logical value 0, and when the count output f reaches the predetermined first count value "15", the game starts from G4. A first count signal having a logic value of 1 is output, makes gate G5 conductive, and is transmitted to gate G3 via gate G2. As a result, the count prohibition signal l output from the gate G3 changes again to the logical value 1, and the addition/subtraction counting circuit CNT2 stops counting. On the other hand, the inverted clock signal cp is connected to the terminal S of the flip-flop FF3.
is input through gate G5, and the flip-flop FF
3 is sent, and the alarm output signal d output from the terminal Q is set to the alarm state (logical value 1). As a result of the above, the alarm output signal d becomes the alarm state 100 to 108 milliseconds after the state signal a changes to the fault state. When the state signal a returns to the normal state in this state, the flip-flop FF2 is reset and changes the output signal from the terminal Q to a logic value of 0 and the addition/subtraction switching signal e output from the terminal QN to a logic value of 1. As a result, gate G1 becomes conductive, gate G2 becomes inhibited, and the count inhibit signal i output from gate G3 changes to a logic value of 0.

As a result, the addition/subtraction counting circuit CNT2 starts subtraction counting in response to the clock signal CP, and the count output f decreases by 1 every clock from "15". When the count output f reaches ``14'', the first count value signal changes to 0, and when the count output f reaches ``3'', the second count signal of logic value 1 changes from G1-G3. The count signal g is output, turns on the gate G6, and is transmitted to the gate G3 via the gate Gl.

As a result, the count prohibition signal i output from the gate G3 changes to logic 1 again, and the addition/subtraction counting circuit CNT2 stops counting. On the other hand, the inverted clock signal cp is input to the terminal R of the flip-flop FF3 via the gate 1-06, the flip-flop FF3 is reset, and the terminal Q
The alarm output signal d output from the alarm output signal d is set to a non-alarm state.

As a result of the above, the alarm output signal d becomes a non-alarm state 100 to 108 milliseconds after the state signal a changes to the normal state. Next, in FIGS. 3 and 5, the status signal a is set to the normal state, the alarm output signal d is set to the non-alarm state, the counting output f is "3", and the addition/subtraction counting circuit CNT2 has stopped counting. Once the signal a changes to a fault state, the addition/subtraction stitch count circuit CNT2 starts addition and counting as in FIG. 4, and when the count output f reaches 15, the state signal a returns to the normal state again. , the addition/subtraction switching signal e changes to the logical value l at the same time as the count output f becomes "6". In addition, since the counting prohibition signal i maintains a logical value of 0, the addition/subtraction counting circuit C
NT2 starts subtractive counting, and the counting output f changes from "6" to "
5". Note that when the state signal a changes to the fault state again at the time when the count output f shows "6", the addition/subtraction switching signal e changes to the logical value O at the same time as the count output f becomes "5", and the addition/subtraction counting circuit CNT2 Addition counting is started again, and the number of stitches and the output f- increase sequentially. Counting output f is "8"
When the state signal a returns to the normal state again at the time when the count output f becomes "9", the addition/subtraction switching signal e changes to the logical value 1, and the addition/subtraction counting circuit CNT2 starts subtraction counting and starts counting. The output f changes from "9" to "8". Note that when the status signal a changes to the fault state again at the time when the count output f shows "8", the addition/subtraction switching signal e changes to the logical value 0 at the same time as the count output f becomes "8", and the addition/subtraction counting circuit CNT2 Addition counting is started again, and the counting output f increases sequentially. In this way, when the counting output f reaches "15",
As in FIG. 4, the addition/subtraction counting circuit CNT2 stops counting, and the flip-flop FF3 sets the alarm output signal d to the alarm state.

As is clear from the above description, according to this embodiment, even when the status signal a changes irregularly between the normal state and the faulty state, the addition/subtraction counting circuit CNT 2 performs the subtraction count during the normal state. Since the addition count is repeated during the fault state, as long as the fault state is set longer than the normal state, the alarm output signal d will always reach the alarm state.

It should be noted that Figures C to 5 are only one embodiment of the present invention, and for example, the change process of the state signal a is not limited to what is shown in the figures, and many other modifications may be considered. However, the effects of the present invention remain the same in either case. Further, the configuration of the alarm control circuit is not limited to that shown in the drawings, and many other modifications may be considered, but the effects of the present invention will not change in any case.

(gl) Effects of the Invention As described above, according to the present invention, it is possible to realize an 11-report control circuit that accurately reaches the alarm state even when the status signal changes irregularly between the normal state and the fault state.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of a conventional alarm control circuit, FIG. 2 is a diagram showing an example of the operation process in FIG. 1, and FIG. 3 is a diagram showing an alarm control circuit according to an embodiment of the present invention. 4 and 5 are diagrams showing an example of the operation process in FIG. 3, and FIG. 4 shows the case where the state signal simply changes, and
The figures each show cases in which the state signal changes irregularly. In the figure, CNTl is a counting circuit, CNT2 is an addition/subtraction counting circuit, FOR is an exclusive OR circuit, FF1 to FF3 are flip-flops, Gl to G6 are gates, INV is an inverting circuit, a and a l are state signals, b, b ' and f
are count outputs, C and cl are carry signals, cp is a clock signal, d and d゛ are alarm output signals, e is an addition/subtraction switching signal, g is a second count value signal, and h is a first count value signal. Not shown. 〇－

Claims (1)

[Claims] means for setting an addition/subtraction switching signal to be transmitted to the addition/subtraction counting circuit on the addition side when the input status signal indicates a fault condition, and setting the addition/subtraction switching signal on the subtraction side when the status signal indicates a normal status; , when the addition/subtraction switching signal is set to the addition side, 1 is added every clock, and the addition "
When the subtraction switching signal e is set to the subtraction side, an alarm is issued when the counting output of the addition/subtraction counting circuit that subtracts 1 every clock and the addition/subtraction stitch count circuit during addition reaches a predetermined first value. means for stopping the addition of the number of stitches in the addition/subtraction counting circuit at the same time as setting the output circuit, and outputting an alarm when the count output of the addition/subtraction counting circuit during subtraction reaches a second value determined to be smaller than the first value. An alarm control circuit comprising means for resetting the circuit and stopping subtraction counting of the addition/subtraction counting circuit.