JPH04144440A - Signal transmitting equipment - Google Patents

Abstract

PURPOSE:To suppress a false input signal due to noise by combining an exclusive OR circuit and a D-type flip circuit for an input signal. CONSTITUTION:If a minus noise is applied when an input signal 100 is logic '1', an output signal 102 from the exclusive OR circuit 3 is turned to logic '0', AND gates 4, 5 are closed and the output signals 103, 104 of the gates 4, 5 are turned to logic '0'. Although only the output signal 103 of the gate 4 is changed out of the signals 103, 104, the status change of the D-type FF 8 is not generated and a D-type FF 9 also is not reset even if the signal 103 is turned from logic '1' to logic '0'. Since the status changes of the circuits 8, 9 are not generated, no noise is outputted to output signals 105, 106. Consequently, the generation of a false input due to noise can be suppressed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Fields] The present invention provides a method for receiving two signals complementary to each other,
The present invention relates to a signal transmission device that transmits signals, and particularly to a signal transmission device that can block false input signals due to noise.

[Prior Art] A conventional circuit for receiving two complementary signals has been used to prevent false input signals caused by noise by adding a filtering circuit to the circuit.

[Problems to be Solved by the Invention] The conventional method for blocking false input signals due to noise described above is as follows:
There is a drawback that a false input signal having the same characteristics as a normal input signal cannot be blocked and the circuit will operate.

[Means for Solving the Problems] A signal transmission device of the present invention includes an exclusive OR circuit that receives as input a first binary signal and a second binary signal that are complementary to each other; a first AND gate inputting the binary signal of 1 and the output of the exclusive OR circuit;
A second circuit whose inputs are the value signal and the output of the exclusive OR circuit.
a first D-type flip-flop circuit whose clock input is the output of the first AND gate and whose reset input is the output of the second AND gate; The second D-type flip-flop circuit has a clock input and an output of the first AND gate as a reset input.

[Example code] Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
Time chart 1. shown in the figure shows the normal operation, and FIGS. 3 to 6 are time charts showing the operation in FIG. 1.

Referring to FIG. 1, this signal transmission device includes application terminals 1 and 2 for applying input signals, an exclusive OR circuit 3, and an A
ND gates 4, 5 and D-type flip-flop circuits 8, 9
, voltage application terminals 6 and 7 for making the input of the D-type flip-flop circuit one clamp, and output terminal 1 for output signal.
0.11.

Next, the operation of this embodiment will be explained.

First, under normal conditions when the input signals 100 and 101 are free of noise, the input signals 100 and 101 are complementary to each other, so the output signal 102 of the exclusive OR circuit 3 becomes logic 1, and the AND gate 4, 5 opens the gate and input signal 1
00, 101 as is AND gate output signal 103
, 104. At that time, when the input signal 100 changes from logic O to logic 1, the output signal 103 of the AND gate also changes from logic O to logic 1, and the output signal 103 of the D-type flip-flop circuit 8 indicates that the voltage applied to the voltage application terminal 6 is Since it is applied and clamped at 1, it becomes logic 1.

At the same time, a reset signal that changes from logic 0 to logic 1 is also applied to the D-type flip-flop circuit 9, so the output signal 106 of the D-type flip-flop circuit 9 becomes logic 0. On the other hand, the input signal 101 changes from logic 1 to logic O,
The output signal 104 of the AND gate 5 also changes from logic 1 to logic 0, but the output signal 1 of the D-type flip-flop circuit 9
06 remains unchanged (however, the D-type flip-flop circuit 9
(The output signal 106 of the AND gate 4 is reset to logic O), and the D-type flip-flop circuit 8 is also not reset.

Next, when the input signal 100 changes from logic 1 to logic 0,
The output signal 103 of the AND gate 4 also changes from logic 1 to logic 0, but the output signal 105 of the I) type flip-flop circuit 8 does not change (however, the output signal 105 of the D type flip-flop circuit 8 changes from logic 1 to logic 0). As per AND game 1-5
is reset to logic 0 by the output signal 104 of
Also, the D-type flip-flop circuit 9 is not reset.

On the other hand, the input signal 101 changes from logic O to logic 1, and A
The output signal 104 of the ND gate 5 also changes from logic O to logic 1, and the output signal 10B of the D-type flip-flop circuit 9 becomes logic 1 because the voltage is applied to the voltage application terminal 7 and is efframped. At the same time, a reset signal that changes from logic 0 to logic 1 is also applied to the D-type flip-flop circuit 8, so the output signal 105 of the D-type flip-flop circuit 8 becomes logic 0.

As shown in (2) below, under normal conditions when there is no noise on the input signals 100, 101, the input signals 100, 101 are output as they are to the output terminals 10.11.

Second, the case where noise is added to the input signals 100 and 101 will be explained with reference to FIG. When input signal 100 is logic 1 and negative noise is added (Normally, when noise is added to input signal 100, noise is also added to input signal 101, but negative noise added to logic 0, logic 1)
The positive noise on the ``-'' is omitted because it does not cause any problem in circuit operation. The same applies below), the output signal 102 of the exclusive OR circuit 3 becomes logic O, the AND gates 4 and 5 close their gates, and the output signals 103 and 104 of the AND gates 4 and 5
becomes logical O. At that time, only the output signal 103 of the AND gate 4 changes, but even if the output signal 103 changes from logic 1 to logic O, No change in the state of the D-type flip-flop circuit 8 occurs;
Also, the D-type flip-flop circuit 9 is not reset. On the other hand, when the noise disappears and the input signal 100 returns from logic 0 to logic 1, the output signal 102 of the exclusive OR circuit 3 also returns to logic 1, opening AND gates 4 and 5, and
Only the output signal 103 of the ND gate 4 returns to logic 1 and is input to the D-type flip-flop circuit 8, but the output signal 103
5 remains at logic 1, no state change occurs, and although a reset signal is input to the D-type flip-flop circuit 9, the output signal 106 remains at logic 0, so no state change occurs either.

As described above, when the input signal 100 is logic 1, negative noise is added and the output signal 103 of the AND gate 4 changes, but since the state of the D-type flip-flop circuits 8 and 9 does not change, the output signal No noise is output up to 105 and 106.

[Effects of the Invention] As described above, the present invention has the effect of being able to prevent false input signals due to noise by combining an exclusive OR circuit for input signals and a D-type flip-flow circuit.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIGS. 2 to 6 are time charts showing the operation of FIG. 1. 1.2... Application terminal, 3... Exclusive OR circuit, 4
．． 5...AND game), 6.7... Voltage application terminal,
8.9...D-type flip-flop circuit, 10.11.
...Output terminal.

Claims (1)

[Claims] an exclusive OR circuit that receives as input a first binary signal and a second binary signal that are complementary to each other; and an exclusive OR circuit that receives as input the first binary signal and the output of the exclusive OR circuit. The first A
an ND gate; a second AND gate which receives the second binary signal and the output of the exclusive OR circuit; and a clock input which receives the output of the first AND gate;
a first D-type flip-flop circuit whose reset input is the output of the AND gate; and a second D-type flip-flop circuit whose clock input is the output of the second AND gate and whose reset input is the output of the first AND gate. A signal transmission device comprising a type flip-flop circuit.