JPS59175116U

JPS59175116U - Rotational position detection circuit

Info

Publication number: JPS59175116U
Application number: JP6880383U
Authority: JP
Inventors: 額田　泰明
Original assignee: 日本電気株式会社
Priority date: 1983-05-09
Filing date: 1983-05-09
Publication date: 1984-11-22

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of drawings]

第１図は本考案の一実施例の回路構成図、第２図は第１
図に示した回路構成図の入力及び出力波形を示す。第１図において１および２・・・入力端子、３，４およ
び１２・・・バッファ回路、５，６および１２・・・排
他的論抑和（ＥＸ・ＯＲ）、７・・・インバータ、８゜
１１．１５，２１，２２，２３，２４．２５および２７
・・・出力端子、９および１０・・・フリップフロップ
、１４・・・積算回路、１６．　１７．　１８．　１９
および２０・・・入力端子、Ｒ１およびＲ２・・・抵抗
、Ｃ１およびＣ２・・・コンデンサ。第２図においてａ・・・第１図入力端子１への入力信号
、ｂ・・・第１図入力端子２への入力信号、Ｃ・・・第
１図ＥＸ　−ＯＲ５の出力信号、ｄ・・・第１図ＥＸ・
ＯＲ５の出力信号、ｅ・・・第１図インバータ７の出力
信号、ｆ・・・第１図バッファ１３の出力信号、ｇ・・
・第１図出力端子２２の出力信号、ｉ・・・第１図出力
端子２３の出力信号、ｊ・・・第１図出力端子２４の出
力信号、ａ′・・・第１図Ｄタイプフリップフロップ１
０の出力信号。Fig. 1 is a circuit configuration diagram of one embodiment of the present invention, and Fig. 2 is a circuit diagram of an embodiment of the present invention.
The input and output waveforms of the circuit configuration diagram shown in the figure are shown. In FIG. 1, 1 and 2...input terminals, 3, 4 and 12...buffer circuits, 5, 6 and 12...exclusive logic suppression (EX/OR), 7...inverter, 8゜11.15, 21, 22, 23, 24.25 and 27
... Output terminal, 9 and 10... Flip-flop, 14... Integration circuit, 16. 17. 18. 19
and 20...input terminal, R1 and R2...resistor, C1 and C2...capacitor. In Fig. 2, a...input signal to input terminal 1 in Fig. 1, b... input signal to input terminal 2 in Fig. 1, C... output signal from EX-OR5 in Fig. 1, d.・Figure 1 EX・
Output signal of OR5, e...output signal of inverter 7 in Figure 1, f...output signal of buffer 13 in Figure 1, g...
- Output signal of the output terminal 22 in Figure 1, i... Output signal of the output terminal 23 in Figure 1, j... Output signal of the output terminal 24 in Figure 1, a'... D type flip-flop in Figure 1 Pu1
0 output signal.

Claims

[Scope of utility model registration request]

a first gate of two manual exclusive OR which receives as input a first pulse signal proportional to the rotation and a second pulse signal proportional to the rotation having a constant phase difference from the pulse signal; a time constant circuit which takes the output of the gate as an input; and a second gate of two-man exclusive OR, which takes the output of the time constant circuit as one input and the output of the first gate as the other input. , a first D type flip-flop inputting the output of the second gate to the C input and inputting the first pulse signal to the D input; and inputting the output of the first flip-flop to the D input; and a second flip-flop that inputs the output of the second gate to the C input, and a two-man power system that uses the output of the second flip-flop as one input and the second pulse signal as the other input. A rotational position detection circuit comprising: a third exclusive OR gate;