JPS59174962A - メモリアクセス制御方式 - Google Patents

メモリアクセス制御方式

Info

Publication number
JPS59174962A
JPS59174962A JP4987583A JP4987583A JPS59174962A JP S59174962 A JPS59174962 A JP S59174962A JP 4987583 A JP4987583 A JP 4987583A JP 4987583 A JP4987583 A JP 4987583A JP S59174962 A JPS59174962 A JP S59174962A
Authority
JP
Japan
Prior art keywords
circuit
signal line
shared area
control information
logic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4987583A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6315626B2 (enrdf_load_stackoverflow
Inventor
Yoshinori Yamamoto
義則 山本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP4987583A priority Critical patent/JPS59174962A/ja
Publication of JPS59174962A publication Critical patent/JPS59174962A/ja
Publication of JPS6315626B2 publication Critical patent/JPS6315626B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)
  • Multi Processors (AREA)
JP4987583A 1983-03-25 1983-03-25 メモリアクセス制御方式 Granted JPS59174962A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4987583A JPS59174962A (ja) 1983-03-25 1983-03-25 メモリアクセス制御方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4987583A JPS59174962A (ja) 1983-03-25 1983-03-25 メモリアクセス制御方式

Publications (2)

Publication Number Publication Date
JPS59174962A true JPS59174962A (ja) 1984-10-03
JPS6315626B2 JPS6315626B2 (enrdf_load_stackoverflow) 1988-04-05

Family

ID=12843216

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4987583A Granted JPS59174962A (ja) 1983-03-25 1983-03-25 メモリアクセス制御方式

Country Status (1)

Country Link
JP (1) JPS59174962A (enrdf_load_stackoverflow)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63301974A (ja) * 1987-06-01 1988-12-08 Minolta Camera Co Ltd 画像形成装置の表示装置
US5517625A (en) * 1992-10-30 1996-05-14 Fujitsu Limited System bus control system for multiprocessor system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63301974A (ja) * 1987-06-01 1988-12-08 Minolta Camera Co Ltd 画像形成装置の表示装置
US5517625A (en) * 1992-10-30 1996-05-14 Fujitsu Limited System bus control system for multiprocessor system

Also Published As

Publication number Publication date
JPS6315626B2 (enrdf_load_stackoverflow) 1988-04-05

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