JPS59174947A - System for controlling order of microprogram - Google Patents

Abstract

PURPOSE:To branch a microprogram without delaying the instruction executing time of central control equipment, by installing a means which selects an address to be inputted into a control memory out of plural addresses. CONSTITUTION:A micro-instruction address converting circuit MAC' can store four kinds of addresses (a) of M0-M3 correspondingly to one functioning section (f) for instruction to be executed. One which is assigned by the counted output (c) of a counting circuit MJC which is step-advanced by a branching signal j1 contained in a micro-instruction i1' extracted from a control memory CM, is outputted. Therefore, branched addresses a2, etc., of up to three pieces of the micro-instruction i1' accumulated in a micro-instruction register CMIR can be obtained from the micro-instruction address converting circuit MAC', by outputting the branching signal j1 while a prescribed logical operation circuit is controlled.

Description

DETAILED DESCRIPTION OF THE INVENTION (8) Technical Field of the Invention The present invention relates to a microprogram controlled processing device, and more particularly to a microprogram order control method for speeding up branching on a microprogram.

(b) Background of the technology For example, in a central control unit of an electronic switching system using storage program control, a microprogram is stored in a control memory corresponding to each instruction that makes up the program, and when an instruction is executed, the corresponding microprogram is stored in the control memory. Microprogram control systems have been widely put into practical use, in which microinstructions constituting the microprogram are sequentially read from the control memory to control logic circuits and the like within a central control unit.

(C1 Prior Art and Problems FIG. 1 is a diagram showing an example of a conventional microprogram order control system. In FIG. 1, the microinstruction address conversion circuit MAC converts the microprogram stored in the control memory CM. It is composed of a memory that can store up to 256 types of start addresses a, and is a functional part f of the instruction to be executed inputted from the instruction register IR.
Outputs the start address a stored at the address specified by (8 bits). In the current meeting register IR,
When the instruction to be executed by the central control unit is accumulated and the functional part f1 of the instruction is input to the microinstruction address conversion circuit MAC, the start address a1 is output and stored in the microinstruction address register CM A R? After being multiplied by jf,
Control input to fall memory CM.

The control memo 'JCM stores the first microinstruction 11 of my phantom coprogram corresponding to the instruction to be executed at address a.
1 and stores it in the microinstruction register CMIR. The microinstruction 11 controls a logic circuit (not shown) and the like. The address a1 stored in the microinstruction address register CM A R is incremented by 1 by the adder circuit IC, and then input to the control memory CM again, and the address a1 is
The next microinstruction 12 is successively issued from 1+1. The microinstruction 12 is a microinstruction that includes the address a2 in order to branch to the microinstruction i3 stored at the address a2 (≠a l +i), and does not control a logic circuit or the like. Microinstruction 12 is microinstruction register CM
Once stored in IR, address a2 included in microinstruction +2 is stored in microinstruction address register CM A R
and input to the control memory CM. As a result, the microinstruction i3 is read from the address a2 of the control memory CM, and is stored in the microinstruction register CMIR to control the logic circuit and the like.

As is clear from the above explanation, in the conventional microprogram order control system, after executing one instruction 11 from the microphone stored at address a1,
In order to branch to microinstruction i3 stored in
It is necessary to go through the branch microinstruction 12, which results in a delay in the instruction execution time of the central control unit, etc.

(dl) Purpose of the Invention The purpose of the present invention is to eliminate the drawbacks of the conventional microprogram order control method as described above, and to realize a means for branching a microprogram without delaying the instruction execution time of the central control unit. is in

(Q) Structure of the Invention The object of the present invention is to provide a microprogram-controlled processing device with a microinstruction address conversion circuit that holds a plurality of addresses on a control memory corresponding to instructions executed by the processing device; This is achieved by providing means for manually selecting an address to be input into the control memory from among the plurality of addresses in response to a branch signal included in a microinstruction to be read.

(fl　Embodiments of the invention An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 is a diagram illustrating a microprogram order control method according to an embodiment of the present invention. Note that the same reference numerals indicate the same objects throughout the figures. In FIG. 2, each microinstruction address conversion circuit M A C'' has 2564
Start address a of microprogram of ilEl'Jt
The first address a stored in each area M.0 to M3 for the functional part f of the instruction to be executed stored in the instruction register IR. correspond to one type of address, and among these, areas MO to M3 for outputting address a are specified by count outputs C of count circuits M and JC consisting of 2 bits. When the instruction to be executed is multiplied by N in the instruction register IR, the counting circuit MJC is also initialized. As a result, the count output c (=OO) specifies the area MO of the microinstruction address conversion circuit MAC, and the instruction register I R
The functional unit f1 outputs the address a1 in the area MO, and the microinstruction address register CM
is input to the control memory CM via AR, and the address a
Microinstruction 11° is extracted from microinstruction 1 and stored in microinstruction register CMIR. Furthermore, microinstruction 111
has a built-in branch signal j1 in t for controlling logic circuits (not shown), and microinstruction register CM I
When accumulated in R, it is input to the counting circuit MJC. The counting circuit MJC that is a skeleton of the branch signal j1 is the microinstruction 1
11 advances by one step at the next clock pulse of the one stored in the microinstruction register CMIR, and the count output c(-01
) is output. As a result, the area M1 of the microinstruction address conversion circuit MAC' is newly designated, and the address a2 corresponding to the functional unit f] in the area MI is outputted and sent to the control memory CM via the microinstruction address register CM A R. input, microinstruction 12 from address a2
1 is extracted and stored in the microinstruction register CMIR. Thereafter, when a microinstruction i' that changes the branch signal j1 to L is further read out in the same manner, the 8I number circuit MJC further advances by one step and specifies the area M2 of the microinstruction address conversion circuit MAC', and the functional unit Address a3 corresponding to f1
is output, and a branch can be made to microinstruction 13'.

As is clear from the above description, according to this embodiment, the microinstruction address conversion circuit MAC' can store four types of addresses a corresponding to one instruction to be executed (functional unit f), and the control memory A counting circuit M that increments based on a branch signal J included in a microinstruction i extracted from a CM.
What is specified by the count output C of JC is output.

Therefore, the microinstruction type stored in the microinstruction register CMIR controls a predetermined logic circuit and outputs the branch signal j1, thereby converting up to three branch destination addresses a2, etc. to the microinstruction address conversion circuit MAC. ' can be obtained from '.

It should be noted that FIG. 2 is only one embodiment of the present invention, and for example, the branch signal j1 is not limited to one that increments the counting circuit MJC by 1; Branch signal S J to set to a specific value (for example, 10)
It is also possible to immediately branch from microinstruction 11'' to microinstruction 13 by outputting 2, but the effect of the present invention does not change in such a case. The number of areas and storage capacity of the micro-instruction address conversion circuit MAC' are not limited to those shown in the drawings, and many other modifications may be considered, but the effects of the present invention will not change in any case. Furthermore, it goes without saying that the object of the present invention is not limited to central control units of electronic exchanges.

(g) Effects of the Invention According to the present invention, in the microprogram-controlled processing device, it is possible to branch 74 microprograms without using branch-specific microinstructions, and the instruction execution time of the processing device can be reduced. Speed is increased.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of a conventional microprogram order control method, and FIG. 2 is a diagram showing a microprogram order control method according to an embodiment of the present invention. In the figure, CM is control memory, CM A R is microinstruction address register, and CMIR is ? 】C is an adder circuit, IR is an instruction register, MO to M3 are v'j areas, MAC and MAC' are microinstruction address conversion circuits, MJC is a counting circuit M, a is an address, and C is a counting output. On the other hand, f is a functional unit, 1 and 11 are microinstructions, and J is a branch signal. Rin II21

Claims (1)

[Claims] In a microprogram-controlled processing device, a microinstruction address conversion circuit holds a plurality of addresses on a control memory corresponding to instructions executed by the processing device, and a branch signal included in a microinstruction read from the control memory. 1. A microprogram sequence control system, further comprising means for manually selecting an address to be stored in the control memory from among the plurality of addresses in response to the above.