JPS59174638U - Connected equipment validity check circuit - Google Patents
Connected equipment validity check circuitInfo
- Publication number
- JPS59174638U JPS59174638U JP1983068500U JP6850083U JPS59174638U JP S59174638 U JPS59174638 U JP S59174638U JP 1983068500 U JP1983068500 U JP 1983068500U JP 6850083 U JP6850083 U JP 6850083U JP S59174638 U JPS59174638 U JP S59174638U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- data
- check circuit
- validity check
- connected equipment
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Computer And Data Communications (AREA)
- Detection And Prevention Of Errors In Transmission (AREA)
- Maintenance And Management Of Digital Transmission (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図はこの考案の一実施例のブロック回路図、第２図
はＤＲ信号検出回路６の詳細回路図、第３図は動作を説
明するタイムチャートを示す図、第４図は同じくフロー
チャートを示す図である。
１・・・・・・ＣＰＵ、 ４・・・・・・ＲＡＭ、５・
・・・・・通信制御回路、６・・・・・・ＤＲ信号検出
回路、７・・・・・・タイマ、８・・・・・・ドライバ
、レシーバ、９・・・・・・通信回線、１０・・・・・
・相手機器、１１，１２．１４・・・・・・フリップフ
ロップ、１３・・・・・・排他的オアゲート、１５・・
・・・・コントロール／ステータスレジスタ。
第３図
ＤＲ伴ラう二」’： Ｌ−
ＦＦＩ Ｑ ’
ＦＦ２ Ｑ ” −−−−ＥＸＯＲ：
：−−−−−
ＦＦ３ Ｑ ”
第２図
■FIG. 1 is a block circuit diagram of an embodiment of this invention, FIG. 2 is a detailed circuit diagram of the DR signal detection circuit 6, FIG. 3 is a time chart explaining the operation, and FIG. 4 is a flow chart. FIG. 1...CPU, 4...RAM, 5.
... Communication control circuit, 6 ... DR signal detection circuit, 7 ... Timer, 8 ... Driver, receiver, 9 ... Communication line , 10...
- Destination device, 11, 12. 14... Flip-flop, 13... Exclusive OR gate, 15...
...Control/Status register. Figure 3 DR 2"': L-FFI Q' FF2 Q" -----EXOR:
:------FF3 Q" Figure 2■
Claims (1)
いて、データを送信する機器が該データを受信する機器
に対し出力するデータ送信可能信号を検出する検出回路
と、この検出回路の検出時間を計時する計時回路と、こ
の計時回路の計時時間が所定時間に達したか否かを判断
する判断回路とを備え、この判断回路が上記計時時間が
上記所定時間に達・したことを判断した場合にデータ授
受の開始を有効と見做すことを特徴とする接続機器の有
効性チェック回路。In a system that exchanges data between multiple devices, there is a detection circuit that detects a data transmission enable signal that a device that transmits data outputs to a device that receives the data, and a timer that measures the detection time of this detection circuit. and a judgment circuit that judges whether or not the time measured by the clock circuit reaches a predetermined time, and when the judgment circuit judges that the time measured reaches the predetermined time, the data is exchanged. A validity checking circuit for a connected device, characterized in that the start of the connected device is regarded as valid.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1983068500U JPS59174638U (en) | 1983-05-10 | 1983-05-10 | Connected equipment validity check circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1983068500U JPS59174638U (en) | 1983-05-10 | 1983-05-10 | Connected equipment validity check circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59174638U true JPS59174638U (en) | 1984-11-21 |
Family
ID=30198670
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1983068500U Pending JPS59174638U (en) | 1983-05-10 | 1983-05-10 | Connected equipment validity check circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59174638U (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4930782A (en) * | 1972-07-14 | 1974-03-19 | ||
| JPS5141911A (en) * | 1974-10-05 | 1976-04-08 | Nippon Erekutoronitsuku Shisut | JUSHINSOCHI |
| JPS5230304A (en) * | 1975-09-04 | 1977-03-08 | Nippon Telegr & Teleph Corp <Ntt> | Asynchronous terminal connection method |
-
1983
- 1983-05-10 JP JP1983068500U patent/JPS59174638U/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4930782A (en) * | 1972-07-14 | 1974-03-19 | ||
| JPS5141911A (en) * | 1974-10-05 | 1976-04-08 | Nippon Erekutoronitsuku Shisut | JUSHINSOCHI |
| JPS5230304A (en) * | 1975-09-04 | 1977-03-08 | Nippon Telegr & Teleph Corp <Ntt> | Asynchronous terminal connection method |
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