JPS58113151U - Data transfer error detection circuit - Google Patents
Data transfer error detection circuitInfo
- Publication number
- JPS58113151U JPS58113151U JP643482U JP643482U JPS58113151U JP S58113151 U JPS58113151 U JP S58113151U JP 643482 U JP643482 U JP 643482U JP 643482 U JP643482 U JP 643482U JP S58113151 U JPS58113151 U JP S58113151U
- Authority
- JP
- Japan
- Prior art keywords
- data
- data transfer
- error detection
- detection circuit
- timing signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Detection And Prevention Of Errors In Transmission (AREA)
- Signal Processing For Digital Recording And Reproducing (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は、従来のブロック図、第２図は、従来技術の動
作を示す信号のタイムチャート、第３図は、本考案の一
実施例のブロック図、第４図は、本考案の一実施例の回
路図、第５図は、本考案の動作を示す信号のタイムチャ
ートである。
１・・・・・・送信制御回路、２・・・・・・受信レシ
ーバ−１３・・・・・・アンドゲート、４・・・・・・
データーバッファ、５・・・・・・パリティチェック回
路、６・・・・・・データー転送タイミング信号異常検
出回路。FIG. 1 is a conventional block diagram, FIG. 2 is a signal time chart showing the operation of the prior art, FIG. 3 is a block diagram of an embodiment of the present invention, and FIG. 4 is an embodiment of the present invention. The circuit diagram of the embodiment, FIG. 5, is a time chart of signals showing the operation of the present invention. 1... Transmission control circuit, 2... Receiver-13... AND gate, 4...
Data buffer, 5... Parity check circuit, 6... Data transfer timing signal abnormality detection circuit.
Claims (1)
１本のデーター転送モード線とをもち、データー転送モ
ード中のみ、一定の周期のタイミング信号で前記データ
ー線上のデーターを受信する磁気テープ装置とのバイト
転送インターフニーλにおいて、複数データーラインの
パリティチェック回路と、前記タイミング信号の欠損を
監視、検出する回路と、複数データーラインの誤り検出
を行ない、さらに、その複数データーの時系列チェック
を前記データー転送モード中行なう回路とからなること
を特徴とするデーター転送誤り検出回路。Multiple data lines, one transfer timing signal,
Parity check of multiple data lines in byte transfer interface λ with a magnetic tape device that has one data transfer mode line and receives data on the data line using a timing signal of a constant period only during data transfer mode. A circuit for monitoring and detecting loss of the timing signal, and a circuit for detecting errors in a plurality of data lines and further checking the time series of the plurality of data during the data transfer mode. Data transfer error detection circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP643482U JPS58113151U (en) | 1982-01-22 | 1982-01-22 | Data transfer error detection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP643482U JPS58113151U (en) | 1982-01-22 | 1982-01-22 | Data transfer error detection circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58113151U true JPS58113151U (en) | 1983-08-02 |
Family
ID=30019213
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP643482U Pending JPS58113151U (en) | 1982-01-22 | 1982-01-22 | Data transfer error detection circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58113151U (en) |
-
1982
- 1982-01-22 JP JP643482U patent/JPS58113151U/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS58113151U (en) | Data transfer error detection circuit | |
| JPS5918763U (en) | Elevator abnormal storage device | |
| JPS59180577U (en) | Time axis correction device | |
| KR910000152Y1 (en) | Detecting circuit of overrun and underrun data error for magnetic tape | |
| JPS6071956U (en) | Multi-CPU system with version check function | |
| JPS5817635U (en) | magnetic recording and reproducing device | |
| JPS60643U (en) | Bus line parity error detection tester | |
| JPS5940940U (en) | Register check circuit | |
| JPS60139280U (en) | pulse monitoring device | |
| JPS60163529U (en) | Pause mode control device | |
| JPS5817692U (en) | playback device | |
| JPS5858641U (en) | Control device | |
| JPS5888487U (en) | Input circuit for remote monitoring and control equipment | |
| JPS6145793U (en) | tape recorder | |
| JPS5982345U (en) | magnetic recording and playback device | |
| JPS59100337U (en) | DMA control circuit | |
| JPS5869218U (en) | data recording device | |
| JPS59177013U (en) | magnetic disk controller | |
| JPH0351936A (en) | Input/output control system | |
| JPS60100853U (en) | I/O event recorder | |
| JPS5996610U (en) | Bus abnormality detection circuit | |
| JPS59146782U (en) | Continuity test equipment | |
| JPS5917091U (en) | data transfer system | |
| JPS5994393U (en) | Image processing device | |
| JPS6020655U (en) | Abnormality monitoring device for asynchronous bus-coupled computer system |