JPS59172059A - Electronic computer system - Google Patents

Abstract

PURPOSE:To apply software of any architecture by performing the program processing in a master processor in the first mode and performing the program processing in a slave processor in the second mode. CONSTITUTION:If it is decided that the second mode is designated, a slave processor 14 disconnects a master processor 11 from the system in accordance with an IPL routine. The slave processor 14 loads a system program and an input/output control program for the second mode, which are stored in a floppy disc drive FDD20, to a local memory 15. Then, the control is transferred to the system program in the local memory 15, and the system is started. As the result, all system operations are performed only by the slave processor 14 similarly to a personal computer or the like which is operated with a single processor.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a Kameko computer system having two types of processors with different computer architectures.

[Technical background of the invention and its problems]

In recent years, the development of microelectronic computers has been remarkable, and the market is rapidly expanding, especially in the field represented by personal computers. Typically, these personal computers are equipped with a world standard microprocessor, such as Intel's 8085.

8086, MC68000 manufactured by Moto O-7, etc. are often used. Software assets for personal computers are becoming increasingly vast and readily available as distributed software. On the other hand, these mainstream microprocessors are also being used in a field called office computers, which rank higher* than personal computers. However, office computers have a long history and have a huge amount of software assets. The architecture of these office computers is generally different from the mainstream microprocessors described above. Therefore, in reality, it is difficult to use these microprocessors as the main processor of an office computer, for example. That is, traditional office computers and personal computer software are often incompatible. In systems such as this, where the conventional computer architecture cannot be easily changed, there is a drawback that distribution software for personal computers, which has been increasing in size in recent years, cannot be used.3. [Object of the Invention] The present invention This was done in view of the circumstances of article E, and its purpose is to
An object of the present invention is to provide an electronic computer system in which software of either architecture can be applied in a system having two types of processors with different computer architectures.

[Summary of the invention]

The present invention provides, in a system including a mask processor having a first architecture and a slave processor having a second architecture, when the switching means switches to the first mode, the master processor executes program processing. On the other hand, if the slave processor performs input/output processing and is switched to the second mode by the switching means, the slave processor performs both the program processing and input/output processing in a time-sharing manner. This is what I did.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows the configuration of an electronic computer system, for example an office computer system. In the figure, 11 is the first
12 is a main memory in which programs, data, etc. used by the mask processor 11 are stored. 13 is a mask processor 11, a main memory 12, and a system bus 2 which will be described later.
The bus interface 14 is a slave processor of a second architecture (different architecture from the master processor 11).The slave processor 14 is, for example, a microprocessor. SW
is a mode switch. The mode switch SW is set to a first mode in which the master processor 1 is used as the main processor, a first mode in which the slave processor Z4 is used as the input/output processor, or a first mode in which the slave processor 14 is used as both the main processor and the input/output processor (
In other words, it is used to specify one of the second modes used as a single processor in a personal computer or the like. On/off information indicating the status of the mode switch SW is held by the bus interface 131.

15 is a program used by the slave processor 14;
Local memory where data etc. are stored. 16 is a CR'l' monitor, and 17 is a CLUr controller (hereinafter referred to as CR and TC).

18 is a keyboard (hereinafter referred to as KB), and 19 is a keyboard control I call (hereinafter referred to as KBc). 2θ is a floppy disk drive (hereinafter referred to as Fl)
), 21 is a floppy disk controller (under μ, referred to as FDC). 22 is a magnetic disk device (hereinafter referred to as DISK), and 23 is a disk controller (hereinafter referred to as DISKC). 24
is a printer (hereinafter referred to as PRT), 25 is a printer controller (hereinafter referred to as PH,'l''C), and 26 is a bus interface 13, a slave terminal.
)-14, local 7'mo'), 15.

CRTC17, KBC19, FDC21, DISKC2
This is a system bus that connects 31, PRTC 25, etc.

Next, the operation of one embodiment of the present invention will be explained with reference to the flowchart of FIG. When the system is powered on, an initial program loading routine (this is called an IPL routine) in a microprogram fixedly stored in a ROM (not shown) possessed by the slave processor 14 is activated (step S)
)The slave processor 14 executes the IPL routine, and first determines whether the first mode is designated by the mode switch SW (step S2).
). This means that the slave 7' resetter 14 is connected to the mode switch S held by the bus interface 131.
This is done by reading the on/off information of W.

When the slave processor 14 determines that the first mode is designated by the mode switch SW, it loads the input/output control program for the first mode stored in the DISK 22, for example, into the local memory 15 (step S3).

Then, control is transferred to the input/output control program, and the slave processor 1-14 executes the first input/output control program stored in, for example, the DISK 22 based on a predetermined routine of the program.
A system program for the mode is loaded into the main memory 12 (step S4). As a result, control is transferred to the system program, and the system is written (step S5). The mask processor 11 executes the system block, and activates the slave processor 14 when input/output processing is required. As a result, mask processor 1
1, the parallel operation of the system program processing and the input/output processing (based on the input/output control program) by the slave processor I4 is started. When the slave processor 14 finishes input/output processing, it applies a different color to the master processor 1.

On the other hand, if it is determined in step S2 that the first mode is not designated, that is, if it is determined that the second mode is designated, the slave processor 14 first restarts the startup mode according to the PL routine described above. Processor II is disconnected from the system (step S6).

This is accomplished by turning off the power to the master processor 11, or by controlling the bus interface 13 to disconnect the master processor 11 from the system bus 26. Next, the slave processor 14 loads the second mode system program and input/output control program stored in the FDD 2o, for example, a program compatible with the architecture of the slave processor 14, into the local memory 15 (step sy). Control is then transferred to the system program ζ in the local memory 15, and the system is started (step S8).As a result, similar to a personal computer that operates on a single processor, the slave processor 14 alone can perform system operations. That is, the slave processor 14 alone performs program processing based on the system program and input/output processing based on the input/output control program in a time-sharing manner.

In the above embodiment, the slave processor 14 disconnects the master processor 11 from the system when the second mode is specified, but the bus interface I3 disconnects the mask processor 1 from the system according to the on/off state of the mode switch SW. (In this case, it may be disconnected from the system bus 26).

〔Effect of the invention〕

As described in detail above, according to the present invention, a processor (1) of general (standard) computer architecture is required to play the role of an input/output processor in a conventional computer system. When using the processor, the processor can also have the role of the main processor, so commercially available distribution software can be run on the processor.Furthermore, since the present invention is not an emulation using a mask processor, According to the present invention, the software of the architecture of the mask processor can be applied in the same way as in the past.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG.
The figure is a flowchart for explaining the operation. 1...Mask processor, 12...Main memory, 14
...Slave processor, 15...Local memory, SW...Mode switch. Applicant's agent Patent attorney Takehiko Suzue Figure 1 Figure 2

Claims (3)

[Claims] (1) a master processor having a first architecture; a slave processor having a second architecture; and a first mode in which the master processor performs program processing and the slave processor performs input/output processing. means for causing the slave processor to perform the program processing and image processing of input/output processing in a time-sharing manner in the second mode; and switching means for switching between the first and second modes. An electronic computer system characterized by: (2) The computer system according to claim 1, wherein the master processor is separated from the system by being switched to the second mode by the switching means. (3) The computer system according to claim 1, wherein the master processor is separated from the system by the second means.