JPH03111961A - Program loading system for multi-cpu - Google Patents

Abstract

PURPOSE:To allow the system to optionally cope with a user's request by allowing a sub-CPU to execute a boot program loaded by a main CPU and load a program to be executed by the sub-CPU to a RAM in the sub-CPU. CONSTITUTION:The boot program for loading a program to be executed by the sub-CPU 2 is loaded to a 1st storage means 3 by the main CPU 1. Then, the sub-CPU 2 executes the loaded boot program and loads the program applied from the main CPU 1 to the RAM of the sub-CPU 2 by using a part of a 2nd storage means 4. When the boot program to be loaded from the main CPU 1 to the sub-CPU 2 is previously stored in the main CPU 1, the main CPU 1 can load the program to be executed to the sub-CPU 2 even if the program of the main CPU 1 or the program of the sub-CPU 2 is applied by a line or the like.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a multi-CPU system consisting of a plurality of CPUs, and more specifically, to a program loading method for a multi-CPU consisting of a main CPU and a sub-CPU. In a multi-CPU system consisting of a main CPU and at least one sub-CPU, a first memory connected to the bus of the main CPU and storing a boot program is provided. and a second storage means connected to the bus of the main CPU and the bus of the sub CPU,
The boot program is loaded into the second storage means by the PU, and the sub CPU executes the loaded boot program and stores the program to be executed by the sub CPU tJ in a RAM connected to the bus of the sub CPU. Configure to load.

[Industrial application field]

The present invention relates to a multi-CPU system comprising a plurality of CPUs, and more particularly to a program loading method for a multi-CPU comprising a main CPU and a sub-CPU.

[Conventional technology]

In each signal processing and control device, a so-called multi-CPU system using a plurality of CPUs is often used even in one device, for example, in order to speed up processing.

Such a multi-CPU system consists of a main CPU and a sub-CPU, and the main CPU transfers data from other devices and data generated within the main body, for example, via a line or the like. The sub-CPUs are connected to the main CPU through an I10 interface having a buffer, and each receives commands and data from the main CPU via the I10 interface.
Furthermore, the processing results and status of the sub CPU are added to the main CPU via the I10 interface.

Although data transfer between the main CPU and sub CPU has been described above, the main CPU and sub CPU also perform time monitoring and other controls. This multi-CPU system makes it possible to realize, for example, time control that is required in a short period of time.

The main CPU of the multi-CPU system described above has a ROM that stores a main control program, a RAM that stores data, a line device, and interfaces such as display output and printer output. In addition, the sub-CPU includes interfaces such as a clock for time management, a buzzer, keyboard control, etc., a ROM that stores programs that control these interfaces, a RAM, a control circuit that controls the power supply, etc., and a barcode reader. Each of these circuits includes a circuit for controlling each I10.

Conventionally, as mentioned above, multiple CPUs are provided,
By having each CPU perform multiple processes,
It provides fast and reliable control.

In particular, in systems that perform high-speed time control, it takes a very high-speed CPU to perform these tasks with a single CPU.
However, it has the characteristic that an inexpensive CPU can be used by distributing the processing.

[Problem to be solved by the invention]

In the multi-CPU system as described above, the main CPU and the control CPU are each provided with a ROM that stores a program to be executed, and each CPU executes and controls the program stored in the ROM.

Therefore, if each device is to have individual specifications for each user, it is necessary to change the program for each CPU. At this time, there was a problem in that the ROM mentioned above had to be replaced.

When executed on one CPU, for example, the main CPU
If the sub-CPU has a line interface, by loading the program to be executed from that line, it is possible to load a unique program (user-compatible) to correspond to the user's individual use. When changing the specifications even for the control, there was a problem in that the ROM had to be changed each time.

Further, even if the device is the same, the processing contents must be changed each time the control is different, and the ROM must be replaced.

The object of the present invention is to provide a multi-CPU program loading method that allows programs to be easily changed in response to user requests.

[Means to solve the problem]

FIG. 1 is a block diagram of the principle of the present invention.

The present invention provides a main CPU 1 and at least one sub CPU.
In a multi-CPU system consisting of U2.

The first storage means 3 stores a boot program for loading a program to be executed by the sub CPU 2 into the RAM of the sub CPU 2, and is connected to the bus 5 of the main CPU. For example, this first storage means is a ROM that stores the boot program in advance. Alternatively, an R that stores the boot program input via a line etc.
It is AM.

The second storage means 4 consists of a RAM etc.
A boot program is loaded that loads the program that U2 is to run. This second storage means 4 is a sub-CP
It is connected to buses 5 and 6 of U2 and the main CPUI, respectively, and after the boot program is loaded, the sub CPU
2 executes this program.

[For production]

A boot program that loads a program to be executed by the sub CPU 2 is loaded into the first storage means 4 by the main CPU. After loading the boot program, the sub CPU 2 executes the loaded boot program and loads the program added from the main CPU into the RAM in the sub CPU 2. Main C
A program added from the PUI is transferred to the RAM in the sub CPU 2 using a part of the second storage means 4, for example.

The main CPU is installed in the main CPU in advance as a sub CPU2.
By storing the boot program to be loaded into the computer, even if a main CPU program or even a sub CPU program is added via a line, for example, the program to be executed can be loaded to each CPU. .

〔Example〕

The present invention will be described in detail below using the drawings.

FIG. 2 is a system configuration diagram of an embodiment of the present invention, and FIG. 3 is an explanatory diagram of execution processing of each CPU in the embodiment of the present invention.

ROM1 is on the main (MAIN) CPUIO bus 11.
2. RAM 13, common RAM 16, and interface 1
A memory card 15 is connected via 4. In addition, the bus 17 of the sub CPU 1B includes a RAM 19 and a common RAM 16.
is connected. The ROM 12 contains ■ a main CPU 1.0 program that controls a control device (not shown);
The sub CPU 18 stores a boot program for loading the program from the main CPU 10 into the RAM 19, and the main CPU stores the main CPU boot program to be loaded into the sub CPU.

When the main CPU l0 starts executing when the power is turned on, first the sub CPU's boot program in the ROM12 is transferred to the common R.
Execute the process of storing in AM16 (■). Through this process, the boot program to be executed by the sub CP018 is stored in the common RAM 16. The common RAM 16 is located in the memory space within the main CPU 10, and also in the sub CPU 1.
This memory exists in common in the memory space of B, and the above-mentioned boot program is stored at an address to be executed by the sub CPU 18 after being reset.

When this boot program is stored in the common RAM 16, a reset signal is applied from the main CPU 10 to the sub CPU 18, and the sub CPU is in the 18 reset state (■). And the boot program is common RAM
16, the reset of the sub CPU 18 is released.

As described above, the boot program is loaded in the common RAM 16 at the address to be executed by the sub CPU 18 after the reset is released (the loaded address in the common RAM), so the sub CPU 18 executes this load program.

In executing this boot program, the sub CPU 1B executes the program to be booted using an area other than the boot program in the common RAMIG.

The aforementioned boot program is stored in a part of the common RAM 16. That is, first, a program to be executed by the sub CPU 8 stored in the memory card 15 is read from the main CPU 10 via the interface 14) and stored in the common RAM 16. Common RAM
The program to be executed by the sub CPU 18 stored in the sub CPU 16 is executed by the sub CPU 18 (by executing the boot program).
is read and loaded into the RAM 19 of the sub CPU 8 (■). This common RAM 16 is used by the sub CPU 18
It may be smaller than the capacity of RAM19 exclusively occupied by
For example, if the capacity of the program to be executed by the sub CPU 18 is larger than that of the common RAM 16, the main CPU 10
reads a part of the program from the memory card via the interface 14 and stores it in the common RAM, and the sub CPU 18 performs a plurality of steps to store the stored program in the RAM 19, and the target program is stored in the RAM 19.
Load into.

With the above operation, the sub CPU 1 in the memory card 15
Since the sub CPU 18 stores the program for 8 in the RAM 19 using the boot program described above, by executing that program, the sub CPU 1B can execute the target program even if it does not have a boot program or the like in advance. . In other words, loading can be executed even if no ROM exists at the execution address of the sub CPU.

In the above explanation, the boot program of the sub CPU 18 is stored in the ROM 12 in advance, the boot program is loaded and executed by the sub CPU, and the contents of the memory card 15 (the program of the sub CPU I B) are stored in the RAM 19 by the execution. However, it is not limited to this. For example, only an initial program loader that reads and executes a program from the memory card 15 is stored in the ROM 12 of the main CPU10, and the memory card 1
By sequentially loading the boot program of the sub CPU and further the sub CPU program using the program stored in the ROM 12 of the main CPU I
By storing only the initial program loader in the memory card and storing everything else in the memory card, the main program and sub-CPU programs can be changed freely.

FIG. 4 is a detailed configuration diagram of another embodiment of the present invention. The main CPU 20 has 2L of memory consisting of ROM and RAM.
A liquid crystal display device 22, a memory card 23, a line interface 24, and a printer 25 are connected via a bus.

A common RAM 26 is also connected to the bus. The main CPU 20 performs the main processing of the sub-terminal device connected to the line, and displays information sent from the line (output on the liquid crystal display device 22) and the printer 25.
For example, printing of displayed information, and furthermore, the line interface 24 for information added from the keyboard, which will be described later.
For example, information is output to the host computer via the host computer. These processing programs are stored in the memory (ROM) 21.
After the power is turned on, the main CPU 20 executes this processing program to perform various controls.

On the other hand, when the power is turned on, the sub CPU 27 performs a process of loading a boot program to be executed into the common RAM 26. FIG. 5 is a flowchart of the initial routine of the main CPU. When the power is turned on, the main CP
U reads out the start vector from the address where the start vector is stored and executes it (START). First, a program is executed to transfer the program from the ROM (ROM in which the boot program is stored) to the common RAM, and the boot program is loaded from "'1000" to "'IFFF" of the common RAM 26, for example. The first program to be transferred is a load program for the sub CPU, and is stored in the common RAM 26 connected to the bus connected to the main cPU 20 (Sl). In the embodiment of the present invention, 1. oooo'” IF on the address space in the main CPU 20
A total of 8 bytes of FF"' are the common RAM area.

FIG. 6 is a memory map diagram of the sub CPU 20 and the main CPU 27. By the process s1 described above, “FOOO
” to “FFFF” is stored in the common RAM from “’1000” to “”IFFF”. Although not shown, a ROM in the main CPU stores a processing program that performs the above-mentioned processing.

After the process S1, a process S2 for setting a vector area (Fooo) is executed. This vector area stores the address (FOOO) to be executed by the sub CPU after the reset is released, and the common RAM 26 on the memory in the main CPU is "from 'oooo'" to "IF".
However, in the memory map on the sub CPU 27, the common RAM is from "EOOO" to "FFF".
F”.Here, “'FF F F F’”
The previous 10 bytes, for example, store various vectors to be executed by the main CPU 20, and in order to use only this portion as the vector address for the sub CPU, a dedicated vector address is set in step S2. After this setting, the main CPU 20 cancels the reset of the sub CPU 26 (S3). By this cancellation, sub CPU2
6 is reset-released, for example, 16 of "FFFFE""FFFF" where the vector address is stored.
A value consisting of bits is read and processing is executed using that value as a start vector.

As mentioned above, the common RAM 26 is stored in the memory in the sub CPU 26 from "EOOO" to "F F F F".
Therefore, the process is executed from the area written in the above-mentioned process S2.

FIG. 7 is a flowchart of the sub CPU boot program. When the sub CPU is released from reset by the above-mentioned process S3, it starts execution, first starts the loader program from "Fooo" (Sll)L, and stores the regular program from "o o o o" to "'3FFF". SL2 is executed.

The keyboard control circuit 2 is connected to the sub CPU 27 via the bus.
8, a buzzer 29, a clock 30, a RAM 31, a power supply control circuit 32, and a barcode reader 33 are connected, and a program for controlling each of these circuits is loaded into the RAM 31. This data transfer between the main CPU and sub CPU is performed via the common RA, M26.

As mentioned above, the boot program is stored in "FOOO" to "FFFF", and "Eooo"
"E F F F" exists on the memory in the sub CPU 27 but is still an unused portion. Using this unused portion, the main CPU 20 first stores a program for the sub CPU 26 (S4).

The program is then stored on the RAM 31 of the sub CPU 27 in the aforementioned process S12. The sub CP tJ then determines whether the program loading has been completed (513), and if not (NO), repeats the process 312 again.

As mentioned above, the medium to be transferred is via the common RAM 26, and the area used for transfer on the common RAM 26 is from "oooo" to "IFFF" (sub CPU
From “E O00” to “E F F F”)
Therefore, the regular program is loaded in parts.

When the program loading is completed by the process (313), the vector area is set, that is, the vector area is set to "0000", for example, 10 bytes before "'FFFF" in the vector area "'FFFF'" from "'FOOO" where the loader program is stored. Stores the address to be executed from. In addition, if an interrupt or the like is to be performed, a program vector for the interrupt or the like is also stored (314). Then, the common RAM H area other than the area where the vector is stored is erased (from "F000" to "FFFO"), and the sub CPU ends the processing (315). For example, the processing of the software interrupter, etc. By executing the command, the vector automatically shifts to execution of the software interrupter. For example, if the software interrupter is preset to "OOOO", the loaded sub-CPU program is executed.

On the other hand, the main CPU 20 determines whether or not the loading of the program of the sub CPU 26 is completed in the above-described processes S12 and S1.
3, it reads the regular program and stores it in the common RAM 26 (S4), and also determines whether the subprogram has finished loading (S5).
) is executed, and if it is not the end, the process S4 is repeated again. This repetition is the process S12 of the sub CPU mentioned above.
This corresponds to S13, and the regular program is loaded into the sub CPU by these two operations. Then, in judgment S5, when it is judged that the loading of the subprogram is completed (YES), the main program performs normal operation, that is, normal operation processing. For example, this normal processing is terminal processing.

When the sub CPU 27 completes the initial processing, it can input commands from the keyboard, read barcode leagues, and perform basic processing control as a terminal device.

Through the process described above, the program stored in the memory 21 is loaded into the subprogram, and the subprogram executes the loaded program.
For example, by storing the main CPU program, sub CPU program, and loading program in one ROM of the main CPU 20, the system can be started up with one ROM without providing a ROM in the sub CPU. I can do it.

On the other hand, in the process described above, it is assumed that the information is stored in the memory card 23 in advance, but the information is not limited to this. For example, the main CPU's boot R is stored in the memory 21.
Only the OM is stored, and the main CPU program and even the sub-C are stored from the memory card 23 and line interface 24.
The PU boot program or even the sub-CPU regular program may be input. At this time, as shown by the dotted line in FIG. 5, the main CPU reads the vector at the same time as the power is turned on (S7), and then executes the vector from the start address of the main CPU's boot ROM and reads the vector via the memory card 23 and line interface 24. The program to be added is loaded into the memory 21 (RAM) (S9). Further, the sub CPU boot program and the sub CPU program are also stored in the RAM 21 at the same time. and main CPU2
0 is sub-reset and the process starts from the above-mentioned process (Sl).

Through the above processing, for example, R in the memory 21 is
By simply storing a basic boot program to be executed by the main CPU 20 in the OM, programs can be loaded from the outside and all control programs can be loaded.

As described above, according to the present invention, by storing only the boot program in one ROM and loading the program from a memory card or line, it is possible to freely change the control for the user.

〔Effect of the invention〕

As described above, according to the present invention, the sub CPU has RO
Since the system can be started up without providing M, even if a change in specifications etc. occurs, it is possible to easily respond to changes in use. Additionally, users can be handled freely.

[Brief explanation of drawings]

Fig. 1 is a principle block diagram of the present invention, Fig. 2 is a system configuration diagram of an embodiment of the present invention, Fig. 3 is an explanatory diagram of execution processing of each CPU in an embodiment of the present invention, and Fig. 4 is a diagram of the present invention. FIG. 5 is a flow chart of the initial routine of the main CPU, FIG. 6 is a memory map diagram of the sub CPU and main CPU, and FIG. 7 is a flow chart of the boot program of the sub CPU. 1... Main CPU. 2... Sub CPU. 3... first storage means, 4... second storage means, 5... bus.

Claims (1)

[Claims] A main CPU (1) and at least one sub CPU (2
), a first storage means (3) connected to the bus (5) of the main CPU (1) and storing a boot program; and a bus (5) of the main CPU (1). and said sub CPU
a second storage means (4) connected to the bus (6) of (2);
and the main CPU (1) stores the second storage means (
4) Load the boot program into the sub CP
A multi-CPU characterized in that U (2) executes the loaded boot program and loads a program to be executed by the sub CPU (2) into a RAM connected to a bus of the sub CPU (2). Program loading method.