JPS59171237A - Data transfer system - Google Patents

Abstract

PURPOSE:To prevent competition of occupancy and to identify an occupied subordinate device without using a complicated processor by detecting the coincidence between the own identification code transmitted on a data bus and data on the bus and outputting the result. CONSTITUTION:Even if a subordinate device SD1 is started and an SDn is started at the same time and different identification codes are transmitted on the data bus DB, since a bus driver of open collector type is used, the driver is not destructed. Let the identification codes of the devices SD1, SDn be respectively 001 and 111, then the code signal transmitted on the bus DB is 111, it is detected by a coincidence detecting circuit M of the device SDn, transmitted to a control signal input terminal IN1 of a control circuit CT, the circuit CT keeps the starting state to perform the usage statement of a start signal transmission data bus DB of a transmission storage section D. The device SD1 is not detected for coincidence and the circuit CT is restored. Thus, the identification code and data of the device SDn are transmitted to a master device MD.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a data transfer method, and more specifically, to a system having one main device and a plurality of slave devices, each of which is connected by a common bus. , relates to a method for transferring data from a slave device to a master device via a common bus.

Prior Art and Problems In a system that has one main device and multiple slave devices and these devices are connected via a common bus, when data is transferred from the slave device to the main device via the common bus. , according to the prior art, multiple buses/buses can be connected simultaneously to one bus
If a driver is operated, the bus driver may be destroyed, so a bus control circuit is provided to prevent data transfer requests from slave devices from duplicating and multiple bus drivers driving the bus at the same time to prevent collisions. In order to prevent this from occurring, measures have been taken, such as providing separate wiring in addition to the common bus to process bus usage requests, and using a polling method to have the main device control the bus usage requests of slave devices. All of the above-mentioned conventional techniques require signal processing, and have the disadvantage that their devices are quite complex and require wiring in addition to the common bus.

OBJECTS OF THE INVENTION The present invention provides a system that has one main device and a plurality of slave devices, connects these devices via a common bus, and employs an oven collector type as a bus driver. It is an object of the present invention to eliminate the above-mentioned drawbacks of the method of transferring data from a device to a main device via a common bus, and to simplify the structure of the device used for data transfer on both the main device side and the slave device side.

Examples of the invention Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a connection configuration diagram of an embodiment of the present invention.

In the figure, MD is a main device, SD1 to SDn are slave devices, and B is a common bus consisting of a clock bus CLB, a control bus CB, and a data bus DB.

In the main device MD, CL is a clock generation circuit, SD is a control bus state detection circuit, and IDR is a slave device S.
Identification code receiving section of D1 to SDn, DR is slave device SD1
A data receiving unit SEL that receives transfer data sent from a transmission data storage unit D (described later) of ~SDn is a selector.

Since the parts related to data transfer of the slave devices SD1 to SDn have similar configurations, the slave device SD1 will be described in detail. DV1 is an oven collector type bus driver, DV2 is a normal dry-state bus driver, R is a bus receiver, M is a coincidence detection circuit, OG is an OR gate, and D is a transmit data storage unit, such as a shift - What can be configured with a register, ID is the relevant slave device, in this case the identification code sending section of SD1, and CT is the control circuit.

Now, the operation when transferring data from only the slave device SD1 to the main device MD will be explained.

In this embodiment, the clock generation circuit C of the main device MD
A clock is sent from L to each of the slave devices SD1 to SDn via the main device MD and the clock bus CLB of the common bus B, and synchronized operation of each device is performed.

The control bus state detection circuit SD is the control bus state detection circuit SD.
It is configured to detect two types of voltages corresponding to signals "1" and "0" on the bus CB to identify completion of data reception. Also, the voltage on the control bus CB is given as a control voltage to the selector SEL of the main device MD, and the voltage "
1” (+5V), the selector SEL connects the data bus DB to the identification code receiving unit IDR and sets the voltage to “0” (+5V).
0V), the data bus DB is connected to the data receiving section DR.
Connect to. A +5V voltage is connected to the control bus CB via a resistor r1 to maintain the control bus at +5V. Similarly, the data bus DB has a resistance r
+5V voltage is connected through 2f, and data bus DB is +
I try to keep it at 5V.

Slave device SD1 (similar to other slave devices) receives a control signal output terminal O-T1 from control circuit CT in the inactive state.
The voltage of OT2 becomes “0” and the identification code sending unit ID and sending data storage unit D do not send output (output “0”).
), so the output of the OR gate OG is also "0". Therefore, the output transistor of the open collector type bus driver DV1 is in an off state. Also, the control signal output terminal O
Since T2 is at voltage "0", the output of bus driver DV2 is in a high impedance output state.

Note that in each of the slave devices SD1 to SDn, the output transistor of the open collector type bus driver DV1 is in the off state as described above, and the dry state bus driver DV2 is in the high impedance output state. , data bus DB and control bus C
B is maintained at +5V (voltage "1" state) by the power supply of the main device MD.

Assume that in the slave device SD1, data to be transferred to the main device MD is written into the shift register of its transmission data storage section D, and data transfer is ready. This information is given to the multicontrol circuit CT by means not shown and activated. At this time, the control circuit CT detects the voltage "1" on the control bus CB through the control signal input terminal IN2, identifies that the data bus DB is not transferring data, and uses the control signal output terminal OT1 of the control circuit CT to detect the voltage "1" on the control bus CB. First, the identification code sending unit ID is activated, and the identification code 001 of the slave device SD1 held in the identification code sending unit ID is read and reaches the bus driver DV1 via the OR gate OG. When the signal “0” is applied to the bus driver DV1, the output transistor is off and the voltage of the data bus DB is held at +5V, but when the signal “1” is applied, the output transistor is turned on and the data・Bus DB is connected to earth (signal voltage “0”) and becomes voltage “0”. In this way, the identification code of slave device SD1 is sent to data bus DB.

In the activated slave device SD1, the bus driver D
The identification code signal applied to V1 is branched and input to the coincidence detection circuit M, and the identification code signal on the data bus DB is input to the coincidence detection circuit M via the bus receiver R, where it is compared. . In the started slave device SD1, both inputs match, so the coincidence detection circuit M inputs the coincidence output to the control signal input terminal INI, and the control circuit CT uses this signal to determine whether the identification code conflicts with another slave device. It is determined that the data was sent to the main device MD without any error. Next, the control circuit CT stops sending out the identification code through the control signal output terminal OT1, and switches the low voltage "0" outputted from the control signal output terminal OT2 to a high voltage "1".
The voltage "1" on the control bus CB is changed to "0" via the bus driver DV2, and the use of the data bus DB is declared to other slave devices. One control signal output terminal O-T
The output from 2 activates the transmission data storage section D, and the transmission data is sequentially read out from the shift register of the transmission data storage section D and transmitted. The transmission data is sent to the transmission data storage section D.
The output transistor of the bus driver DV1 is reached via the OR gate OG, which is turned on and off to output the data.
Send data to bus DB. When the sending of the transmission data is completed, the control signal output terminal OT2 changes from the high voltage “1” to “
0", stops the transmission data storage section D, and stops reading the transmission data, and at the same time, the bus driver DV2
The low voltage "0" of the control bus CB is changed to "1" to notify other slave devices that the data bus DB is empty. In the main device MD, the identification code of the activated slave device SD1 is received from the data bus DB via the selector SPL into the identification code receiving unit IDR and held therein. As described above, the voltage of the control bus CB changes to "0" by sending the identification code, thereby switching the selector SEL. Therefore, the transmission data sent from the activated slave device SD1 via the data bus DB is input from the selector SEL to the data receiving section DR and is received. The control bus state detection circuit SD monitors the voltage of the control bus CB, and detects the end of data reception when the low voltage "0" on the control bus becomes "1". When the end of data reception is detected, the main device MD reads the contents of the identification code receiving section IDR and data receiving section DR to know the transferred data and the slave device that sent the data. Can be done.

Assume now that one of the slave devices SD1 is activated and at the same time another slave device, for example SDn, is activated and different identification codes are sent to the data bus DB at the same time.

At this time, since an open collector type bus driver is used, the driver will not be destroyed.

When signal 1 is sent from both slaves at the same time, the signal on the data bus is 1; when signal 0 is sent at the same time, the signal on the data bus is 0, and signals 0 and 1 are If they are sent out simultaneously, the signal on data bus DB will be 1.

This is because an open collector type bus driver is used.

Therefore, assuming that the identification codes of slave devices SD1 and SDn are 001 and 111, respectively, when both identification codes are sent out at the same time, the code signal sent out on data bus DB becomes 111 as described above. In the slave device SDn, a coincidence of this identification code is detected by its coincidence detection circuit M, and a coincidence detection signal is transmitted to the control signal output terminal INI of the control circuit CT, and the control circuit CT continues its activated state and performs its processing. That is, the process moves to a declaration of use of the activation signal sending data bus DB of the transmission data storage section D.

However, in the slave device SD1, the coincidence detection circuit M does not detect a coincidence, and therefore the coincidence signal is not sent to the control signal input terminal INI of the control circuit CT, so the control circuit CT detects this, recovers, and stores the transmission data. No flow signal is sent to section D.

Therefore, in the above, the identification code and data of the slave device SDn are sent to the main device MD.

Furthermore, if a meaningless code is generated from the identification codes sent at the same time, no match is detected in any of the slave devices, and therefore no data is transferred.

Figure 2 shows the data bus DB and control bus in Figure 1.
3 is a time chart of voltage change states on bus CB and operations of identification code receiving section IDR and data receiving section DR of main device MD.

In the figure, DB indicates the voltage change state of the data bus DB, and the identification code sending period (ID) and data sending period (DATA) are "1" (+5V) and "0" according to the identification code and data. It shows that it changes between 0V and is at "1" (+5V) during other periods.

Similarly, CB indicates the voltage change state of the control bus CB, and is "1" in the inactive state and when the identification code is being sent.
, indicates that it is "0" while data is being sent.

MD indicates that the identification code receiving section IDR operates when the voltage of the control bus CB is "1", and the data receiving section DR operates only when the voltage of the control bus CB is "0".

Note that during data transfer, that is, control bus CB
During the period when is "0", a voltage "0" is applied to the control signal input terminal IN2 of the control circuit CT, and this is detected and activation of the control circuit CT is blocked.

The present invention is not limited to the above embodiments, and various modifications are possible.

Effects of the Invention According to the present invention, in a system having one main device and a plurality of slave devices connected to each other via a common bus, data is transmitted from the slave device to the main device via the common bus. When transferring data, a simple device has the effect of preventing conflicts in occupying a common bus and allowing a master device to identify a slave device occupying a common bus by simple means without using a complicated processing device. be. According to the present invention, for example, in an information processing system, it is possible to provide a scanning method using a change point sending method with a simple configuration and relatively low speed. This is suitable for inputting keystroke information of a writer into an information processing device). The transfer data storage section can be easily configured with a shift register.

[Brief explanation of the drawing]

Fig. 1 is a connection configuration diagram of one embodiment of the present invention, and Fig. 2 is a connection diagram of an embodiment of the present invention.
Data bus DB and control bus in the embodiment shown in the figure
3 is a time chart of voltage changes with respect to bus CB and operations of identification code receiving section IDR and data receiving section DR of the main device. MD...Main device, SD1 to SDn...Slave device, B.
...Common bus, CLB...Clock bus, CB...
・Control bus, DB...Data bus, CL
... Clock generation circuit, SD ... Control bus state detection circuit, IDR ... Identification code receiving section, DR
...Data receiving section, SEL...Selector, DV1.
・Open collector type bus driver, DV2・
・・Drystito Bus Driver, R・・Bus・
Receiver, M...match detection circuit, OG...OR gate, ID...identification code sending section, D...transmission data storage section, CT...control circuit. Patent applicant: Fujitsu Ltd. Representative Patent Attorney Kugoro Tamamushi (3 others)

Claims (1)

[Claims] In a system having one main device and a plurality of slave devices, each of which is connected by a common bus including one data bus and one control bus, each slave device: An open collector type bus driver for the data bus, detects a match between its own identification code sent to the data bus via the bus driver, and data on the data bus, and detects the match. a coincidence detection circuit that outputs a signal, a control circuit that changes the voltage of the control bus to prevent other slave devices from using the bus, and a transfer data storage section that stores data to be transferred. The device includes an identification code receiving section that receives an identification code sent from the slave device to the data bus, and a transfer data receiving section that receives the transfer data sent from the transfer data storage section of the slave device. Characteristic data transfer method.