JPH08235109A - Transfer controller - Google Patents

Abstract

PURPOSE: To provide the transfer controller which can frequently change a combination of optional devices on a bus for a computer system wherein the address areas of the devices on the bus are arranged successively to an optional position in the address area of the whole system. CONSTITUTION: An address S10 including information showing a transfer destination among plural slave-side devices is sent out of the address sending-out device 10 of a master-side device 1M to the slave side devices. Then when the address S10 is included in address areas allocated to the respective slave-side devices, an address receiving device 40 makes an area decision signal S42 active. At this time, when device information representing slave-side devices corresponds to a combination of plural slave-side devices included in the address S10, the address receiving device 40 makes a select signal S46 active and a storage device 60 transfers data S30 to the master-side device 1M.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transfer control device for improving the degree of freedom of data transfer from a master device on a bus used in a computer system to a plurality of slave devices.

[0002]

2. Description of the Related Art Conventionally, a computer system requires a communication path for executing data transfer between respective constituent devices in the system, and a bus is generally used as this communication path. Generally, a plurality of devices, that is, a processor, a main storage device, or an input / output device are connected to the bus. In such a system, any one device on the bus becomes a bus master (hereinafter referred to as a master) and all other devices become a bus slave (hereinafter referred to as a slave) in one bus transaction. hand,
Data is transferred between the master and the slave selected by the master (that is, the selected slave). When starting up, initializing, or diagnosing the entire system, the master may transfer data to a plurality of selected slaves. A mode in which all slaves on the bus are selected is called broadcast, and a mode in which an arbitrary number of slaves on the bus are combined and selected is called multicast, including a case where no slave is selected.

Futurebus +, which is one of the bus standards, adopts an open collector type bus and a glitch filter to enable the master to receive response signals from a plurality of selected slaves at one time. The connection procedure between the master and the plurality of selected slaves is simplified. Further, since it is defined that the address area for broadcasting is continuously arranged on the address area of the entire system, broadcasting by Futurebus + is possible. Further, it is defined that the address areas of the individual devices on the bus are continuously arranged at arbitrary positions on the address area of the entire system, and it is also permitted that the address areas are arranged so as to overlap each other. Therefore, it is possible to perform multicast that does not frequently change the combination of the selected slaves (which is referred to as “static”) when starting or diagnosing. However, in Futurebus +, all the selected slaves are required to participate in the bus transaction, and it is difficult to change the arrangement of the address area of each device in the address space of the entire system during normal operation of the system frequently. So change the selected slave combination frequently (expressed as "dynamic")
Multicast is not possible.

[0004]

However, the conventional transfer control device has the following problems. That is, for example, in a system that performs parallel processing, a large amount of data is transferred, and thus dynamic multicast may be required. In such a case, it is general to dispose the address area of each device in the address area of the entire system intermittently. However, in a system such as Futurebus + in which the address area of each device is continuously arranged in the address area of the entire system, this intermittent arrangement method cannot be used. The present invention is a computer system in which the address area of each device on the bus is continuously arranged at an arbitrary position on the address area of the entire system, such as the Futurebus +, in an arbitrary number of slave side devices on the bus. It is intended to provide a transfer control device capable of multicasting in which the combination of is frequently changed.

[0005]

According to the present invention, in order to solve the above-mentioned problems, each address area of each device which can be directly used via a bus is continuously arranged at an arbitrary position in the address area which can be used in the entire system. A master side device and a plurality of slave side devices which are selected by an address output from the master side device and transfer data between the master side device and the master side device. In the transfer control device, the following measures are taken. That is, the master-side device includes an address sending device that sends an address including information indicating an arbitrary number of transfer destinations from the plurality of slave-side devices to the plurality of slave-side devices. On the other hand, the slave side device shows the activity to the first determination signal when the address transmitted from the address transmitting device is included in the address area pre-allocated to each slave side device, and when it is not, When the combination of the first determination device indicating inactivity and the device information indicating the slave side device corresponds to the slave side device included in the address, the second determination signal indicates active, and otherwise. A second determination device indicating inactivity, and the master side when the first determination device indicates activity on the first determination signal and the second determination device indicates activity on the second determination signal When data is transferred to and from the device and the second determination device indicates inactivity in the second determination signal even though the first determination device indicates activity in the first determination signal, From the master side device And input and output device is received and discarded over data, are provided.

[0006]

According to the present invention, since the transfer control device is configured as described above, an address including information indicating an arbitrary number of transfer destinations from a plurality of slave side devices is transferred from the address sending device of the master side device. It is sent to the plurality of slave side devices. Next, when the address transmitted from the address transmitting device is included in the address area pre-allocated to each of the slave side devices, the first determining device determines that the first determining device
Indicates the activity. On the other hand, when the device information indicating the slave side device corresponds to the combination of the plurality of slave side devices included in the address, the second determination device indicates the second determination signal to be active. When the first determination device shows the first determination signal active and the second determination device shows the second determination signal active, the input / output device receives data from the master side device. To transfer. On the other hand, if the first determination device indicates the first determination signal is active and the second determination device indicates the second determination signal is inactive, the input / output device is the master side. Discard data from the device. Therefore, in a computer system provided with this transfer control device, dynamic multicasting that frequently changes the combination of slave side devices can be performed. Therefore, the above problem can be solved.

[0007]

[Example] In this example, like Futurebus +,
In a computer system in which the address area of each device on the bus is continuously arranged at an arbitrary position on the address area of the entire system, multicast that frequently changes the combination of an arbitrary number of slave side devices on the bus can be performed. Thus, the slave side device is configured. Figure 1
It is a functional block diagram of a transfer control device showing an example of the present invention. This transfer control device includes a master side device 1M and a slave side device 2S, and the master side device 1M is connected to a slave side device 2S via a bus B. Further, a plurality of slave side devices (not shown) similar to the slave side device 2S are connected in the same manner as the slave side device 2S.
The master-side device 1M includes an address sending device 10, a bus control device 20, and a storage device 30. The address sending device 10 has a function of receiving the timing control signal S20a from the bus control device 20 and outputting the address S10 to the slave side device 2S via the bus B.
The bus control device 20 receives the bus control signal S20b from the slave side device 2S via the bus B, outputs the timing control signal S20a to the address sending device 10 and the storage device 30, and outputs the bus control signal S20b to the slave side device. 2S
And has a function of outputting via the bus B. The storage device 30 receives the timing control signal S2 from the bus control device 20.
It has a function of inputting 0a and outputting the data S30 held in the storage device 30 to the slave side device 2S via the bus B. The slave side device 2S includes an address receiving device 40, a bus control device 50, and a storage device 60.

The address receiving device 40 is a bus controller 5
The timing control signal S50a is input from 0, the address S10 is input from the master side device 1M via the bus B,
It has a function of outputting the area determination signal S42 to the bus control device 50 and outputting the selection signal S46 to the storage device 60. The bus control device 50 receives the area determination signal S42 from the address receiving device 40, the bus control signal S20b from the master side device 1M via the bus B, and the timing control signal S50a with the address receiving device 40 and the storage device 6.
0 and outputs the bus control signal S50b to the master side device 1M
And has a function of outputting via the bus B. The memory device 60 receives the selection signal S46 from the address receiving device 40, and receives the timing control signal S50 from the bus controller 50.
It has a function of inputting a and inputting the data held in the storage device 30 via the bus B. here,
The address transmission device 10 has a function of transmitting an address including information indicating an arbitrary number of transfer destinations from a plurality of slave side devices to the plurality of slave side devices.
In general, an n-bit amount of information is required to represent all subsets (that is, combinations of elements) of a set of n (n; natural number) elements, including the case where no one is selected.

FIG. 2 is a diagram for explaining address allocation in the case where eight slave side devices 7 to 0 are assumed as an example. The 8-bit information representing the combination of the eight slave side devices 7 to 0 can be placed at any position of the address. In this embodiment, (2) in FIG. 2, that is, A [1
5: 8]. In order to represent the entire address area of the entire system, it is assumed that an address of A [31: 0] having a 32-bit width is used. (1) in FIG. 2 indicates the address area A [31: 0] of the entire system.
Represents the beginning of the device address area located at. Since (3) in FIG. 2 is an address area which is not used in this embodiment, it can be used for any other purpose. In this embodiment, 8
In order to identify each slave side device 7 to 0, the bit (2) in FIG. 2 is assigned to each slave side device 7 to 0 one bit at a time as follows.

That is, A [15] (1: selects device 7, 0: does not select device 7) A [14] (1: selects device 6, 0: does not select device 6) A [13 ] (1: select device 5, 0: do not select device 5) A [12] (1: select device 4, 0: do not select device 4) A [11] (1: select device 3) Yes, 0: do not select device 3) A [10] (1: select device 2, 0: do not select device 2) A [9] (1: select device 1, 0: select device 1) No) A [8] (1: Select device 0, 0: Do not select device 0) However, devices 7 to 0; slave devices 7 to 0.

FIG. 3 is a functional block diagram of the address receiving device 40 in FIG. This address receiving device 40 is
It has a register 41 for holding arrangement information representing an address area pre-allocated to a slave side device (hereinafter referred to as its own device) provided with the address receiving device 40. The register 41 has a function of holding the arrangement information of the own device, that is, the address region of the own device continuously arranged at an arbitrary position on the address region of the entire system. In the present embodiment, the arrangement information of the own device is output to the area comparator 42 using the address S41a indicating the beginning and the end address S41b of the address area of the own device. Further, this address receiving device 40 uses the address A [3] received from the master side device 1M.
1: 0] is held in the register 43. The register 43 stores the address S43a (that is, A
[31: 0]) is output to the area comparator 42, and the address S43 representing the combination of the slave side devices 7 to 0 is output.
b (that is, A [15: 8]) is output to an 8-input 1-output selector (hereinafter referred to as an 8-1 selector) 44.

Further, the address receiving device 40 is provided with a register 45 for holding device information indicating its own device. The register 45 holds the device information of its own device, that is, the device number S45 of any one of 7 to 0, and outputs the device number S45 to the 8-1 selector 44. When the address area S43a is included in the address area from the address S41a to the address S41b, the area comparator 42 has a function of activating the area determination signal S42 in synchronization with the timing control signal S50a. The output side of is connected to the bus control device 50 and is also connected to one input terminal of the AND gate 46. The 8-1 selector 44 selects a bit from the address S43b representing the combination of the slave side devices 7 to 0 based on the device number S45 of the own device, and the state of the bit indicates that the own device is selected. In this case, it has a function of activating the combination determination signal S44 in synchronization with the timing control signal S50a. The output side of the 8-1 selector 44 is connected to the other input terminal of the AND gate 46,
The output side of the AND gate 46 is connected to the storage device 60. Including the technology for connecting the master adopted in Futurebus + and a plurality of selected slaves, that is, using an open collector type bus, a glitch filter, and a handshake protocol for the bus B and the bus controllers 20 and 50. Devices other than the above are configured by conventional techniques.

Next, the operation of FIG. 1 will be described. First, the master side device 1M will be described. The bus control device 20 is
According to the handshake protocol of the bus B, the state of the bus B is sequentially determined by the bus control signal S20b, the timing control signal S20a indicates the period during which the address S10 is output to the address sending device 10, and the timing control signal S20a indicates the storage device 30. The period during which the data S30 is output is shown. As the handshake protocol, for example, the technology adopted by Futurebus + is assumed. Storage device 3
0 outputs the data S30 to the slave side device 2S via the bus B in accordance with the timing control signal S20a output from the bus control device 20. In this embodiment, the storage device 30
First, a first-in-first-out (FIFO) is assumed. The memory device 30 sequentially outputs the data S30 each time the timing control signal S20a is activated. The address sending device 10 outputs the address S10 to the slave device 2S via the bus B in accordance with the timing control signal S20a. Here, a case will be described in which dynamic multicasting is performed with the following combinations for three slave side devices (device numbers 0, 1, 2) having the same configuration as the slave side device 2S in FIG.

First time (multicast to device numbers 0 and 1) Address A [15: 8]: 03h Second time (multicast to device numbers 1 and 2) Address A [15: 8]: 06h Third time (device number) Multicast to 2,0) Address A [15: 8]: 05h Three slave side devices 0, 1, 2 to be multicast
Are continuously arranged at the same position on the address area of the entire system, and the value of the address A [31:16] of these three slave side devices 0, 1 and 2 is 0001h. Further, the value of the unused field A [7: 0] in this embodiment is 00h. Therefore, in this dynamic multicast, the address transmission device 10 transmits the addresses shown below. First time address A [31: 0]: 0001-0300h Second time address A [31: 0]: 0001-0600h Third time address A [31: 0]: 0001-0500h Next, for slave side device 2S explain. In general,
By receiving the address, the slave side device determines whether or not the own device corresponds to the selected slave. Therefore, all slave devices on the bus receive the address at the beginning of the bus transaction.

The bus controller 50 sequentially determines the state of the bus B by the bus control signal S50b according to the handshake protocol of the bus B, and the timing control signal S50.
The time a indicates when the address S10 is input to the address receiving device 40. When the address receiving device 40 indicates by the area determination signal S42 that the device itself is the slave selected, the bus control device 50 determines the state of the bus B by the bus control signal S50b according to the handshake protocol of the bus B. Sequentially determined timing control signal S50
The time when the data S30 is input to the storage device 60 is indicated by a. Selection signal S46 output by the address receiving device 40
When the storage device 60 is selected by, the storage device 60 is selected.
Is a timing control signal S output from the bus control device 50.
According to 50a, the data S30 is input from the master side device 1M via the bus B. The storage device 60 includes the storage device 3
Similar to 0, a FIFO (first-in-first-out) is assumed. The storage device 60 sequentially inputs the data S30 therein every time the timing control signal S50a is activated.
The address receiving device 40 uses the timing control signal S50a.
According to the address S10 from the master side device 1M to the bus B
To enter via.

On the other hand, in FIG. 3, the arrangement information of the own device held in the register 41 is the same information in any of the three slave side devices 0, 1, 2. In the case of the present embodiment, the address indicating the beginning of the address area of the own device is 0001-0000h, and the address indicating the end is 0001-FFFFh. The device information of the own device held in the register 45 is different for each of the three slave devices, and device numbers 0, 1 and 2 are given respectively.
Here, the first multicast, that is, device numbers 0 and 1
The operation of the three slave side devices in the multicast to will be described. Three slave side devices 0, 1, 2
Is the first received address A [31:
0]: 0001-0300h are held respectively. Area comparator 42
If the received address S43a is within the address area indicated by the arrangement information of the own device, the timing control signal S5
The area determination signal S42 is activated at a timing based on 0a. Since the address A [31: 0]: 0001-0300h exists in the address area of the own device, the area comparator 42 activates the area determination signal S42 in all the three slave side devices 0, 1, and 2. Indicates.

In all of the slave side devices 0, 1, 2,
The address receiving device 40 is active in the area determination signal S42, and indicates to the bus control device 50 that its own device corresponds to the selected slave. As a result, the bus control device 50
According to the handshake protocol of the bus B, the state of the bus B is sequentially determined by the bus control signal 50b, and the data S30 is stored in the storage device 60 by the timing control signal S50a.
Indicates when to enter. The 8-1 selector 44 activates the combination determination signal S44 at a timing based on the timing control signal S50a when the received address S43b includes the device information of the own device. When the first address is received, the slave side devices with device numbers 0 and 1 operate as described below. Since the received address A [31: 0]: 0001-0300h includes information indicating the combination of the slave side devices having the device numbers 0 and 1, the 8-1 selector 44 sends the combination determination signal S44 to the combination determination signal S44. Shows activity. Area determination signal S42 and combination determination signal S4
Since 4 and 4 are active, the AND gate 46 is active for the selection signal S46. Then, the address receiving device 40
Indicates that the selection signal S46 is active, the storage device 60
The data S30 is input from the master side device 1M via the bus B in accordance with the timing control signal S50a.

On the other hand, in the slave side device having the device number 2, the operation proceeds as described below. Since the received address A [31: 0]: 0001-0300h does not include the information indicating the slave side device having the device number 2, the 8-1 selector 44 indicates the combination determination signal S44 as inactive. . Since the combination determination signal S44 is inactive even when the area determination signal S42 is active, the AND gate 4
6 indicates that the selection signal S46 is inactive. That is, since the address receiving device 40 shows the inactivation of the selection signal S46, the memory device 60 sends the data S30 from the master side device 1M via the bus B even if the timing control signal S50a is given from the bus control device 50. It works without inputting and discarding. The address receiving device 40 sets the second address A
When [31: 0]: 0001-0600h is received and when the third address A [31: 0]: 0001-0500h is received, the operation proceeds in the same manner, and the dynamic multicast shown below is performed. Be implemented.

Input operation Discarding operation First time (multicast to device numbers 0 and 1) Device number 0 and 1 Device number 2 Second time (multicast to device numbers 1 and 2) Device number 1 and 2 Device number 0 3rd time (Multicast to Device Numbers 2, 0) Device Number 2, 0 Device Number 1 As described above, in the present embodiment, when the area determination signal S42 and the combination determination signal S44 are active, the selection signal S46 is set. The activity is indicated, and the storage device 60 inputs the data S30 from the master side device 1M. On the other hand, even if the area determination signal S42 is active, the combination determination signal S44
, The storage device 60 discards the data S30 from the master device 1M. Therefore, in the transfer control device of the present embodiment, it is possible to perform dynamic multicast that frequently changes the combination of a plurality of slave side devices. The present invention is not limited to the above embodiment, and various modifications can be made. The following are examples of such modifications. (A) The address width and address area allocation of the system are arbitrary. (B) Other methods may be used as the method of expressing the combination of the slave side devices and the method of determining the combination.

[0020]

As described in detail above, according to the present invention, each address area of each device that can be directly used via the bus is continuously arranged at an arbitrary position in the address area that can be used in the entire system. In the transfer control device provided in the computer system, the first determination device is the first
Of the first determination device, the input / output device transfers data between the master-side device and the second determination device when the second determination signal is active. Is active in the first determination signal, but the second determination device is inactive in the second determination signal, the input / output device discards the data from the master side device. Therefore, the dynamic multicasting in which the combination of the devices is frequently changed can be performed. Furthermore, since no special bus handshake protocol is required, there is no need to modify the bus control circuit, and furthermore, there is no need to provide a new signal line for multicast on the bus. Therefore, the system configuration can be simplified and the application range can be widened.

[Brief description of drawings]

FIG. 1 is a functional block diagram of a transfer control device showing an embodiment of the present invention.

FIG. 2 is a diagram illustrating address allocation.

FIG. 3 is a functional block diagram of an address receiving device in FIG.

[Explanation of symbols]

 1M Master side device 2S Slave side device 10 Address sending device 42 Area comparator 44 8-1 selector 46 AND gate 60 Storage device S42 Area determination signal S44 Combination determination signal

Claims (1)

[Claims] 1. A computer system in which each address area of each device that can be directly used via a bus is continuously arranged at an arbitrary position in the address area that can be used in the entire system, and a master side device and the above device are provided. In a transfer control device comprising a plurality of slave side devices selected by an address output from the master side device and transferring data to and from the master side device, the master side device includes the plurality of slaves. An address sending device for sending an address including information indicating an arbitrary number of transfer destinations from the slave devices to the plurality of slave slave devices, wherein the slave slave device has the address sent from the address sender device. A first determination device that is active in a first determination signal when included in an address area pre-allocated to each slave device; A second determination device which is active in a second determination signal when the device information indicating the slave device corresponds to a combination of slave devices included in the address, and the first determination device is a first determination device. Data is transferred to and from the master-side device when the second determination device indicates activity and the second determination signal indicates activity, and the first determination device determines that the first determination device An input / output device that discards data from the master side device when the second judgment device indicates inactivity in the second judgment signal even if the judgment signal indicates activation. And a transfer control device.