JPH0926934A - Transfer controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform multi-casting combining slaves such as a FIFO and a RAM, etc. SOLUTION: An address transmitter 3 transmits an address S2 to a bus 5 corresponding to a timing control signal S2-1 outputted from a bus controller 2 and a storage device 4 transmits data S4 to the bus 5 corresponding to the timing control signal S2-2 outputted from the bus controller 2. The bus controller 12b successively determines the state of the bus by a bus control signal and outputs the timing control signals S12b-1 and S12b-2. In an address receiver 13b, when the address S3 is provided in the address space of the present receiver, active is indicated in an area judgement signal S13b-1, the present receiver is specified by the combination information of devices and a selection signal S13b-2 for indicating that the area judgement signals S13b-1 is active is outputted. The storage device 14b inputs the data S4 corresponding to the selection signal S13b-2, the timing control signal and a local address.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transfer controller having an interface mechanism used in computer systems to improve data transfer to multiple devices on a bus. More specifically, the present invention relates to a transfer control device that improves the flexibility of data transfer in multicast.

[0002]

2. Description of the Related Art A computer system requires a communication path for executing data transfer between the constituent devices of the system, and a bus is generally used as this communication path. Generally, a plurality of devices, that is, a processor, a main memory device, or an input / output device are connected to the bus. In such a system, in one bus transaction, one of the devices on the bus becomes a bus master (hereinafter referred to as a master), and all other devices become bus slaves (hereinafter referred to as slaves). Then, data is transferred between the master and the slave selected by this master (selected slave). When starting up, initializing or diagnosing the entire system, the master may transfer data to a plurality of selected slaves. A mode in which all slaves on the bus are selected is called broadcast, and a mode in which an arbitrary number of slaves on the bus are combined and selected is called multicast even when no slave is selected.

In Futurebus +, which is one of the bus standards, an open collector type bus (a driver of an open collector type drives a signal line, and wire or logic is one of its characteristics. ) And a glitch filter (to eliminate wire or glitches associated with driver switching), allowing the master to receive response signals from multiple selected slaves at once, The connection procedure with multiple selected slaves has been simplified. In addition, it is defined that the address space for broadcasting is continuously arranged on the address space of the address space of the entire system, and broadcasting is possible.

Further, since it is defined that the address spaces of the individual devices on the bus are continuously arranged at arbitrary positions on the address space of the entire system, and it is also permitted to arrange them in duplicate. When starting up or diagnosing, it is possible to perform multicast that does not frequently change the combination of addresses (hereinafter referred to as "static"). However, it is difficult for all selected slaves to participate in the bus transaction, and it is difficult to change the address space allocation of each device in the address space of the entire system during normal operation of the system. Change the alignment frequently (hereinafter referred to as "dynamic")
Multicast is not possible.

[0005]

However, the transfer control device in the conventional multicast has the following problems. In a system that performs parallel processing, a large amount of data is transferred, so dynamic multicast may be required. In such a case, it is general to dispose the address space of each device in the address space of the entire system intermittently. However, this method cannot be used in systems such as Futurebus + where the address space of individual devices must be contiguously arranged in the address space of the entire system, and dynamic multicast cannot be performed. There was a problem. An object of the present invention is to frequently combine an arbitrary number of slaves on a bus in a computer system in which the address spaces of individual devices on the bus are continuously arranged at arbitrary positions on the address space of the entire system. An object of the present invention is to provide a transfer control device capable of changing multicast.

Further, depending on the configuration of the computer system and the purpose of the parallel processing executed on the system, the FIFO
Multicast, which combines a storage device having only one address for transferring data, such as O, and a storage device having multiple addresses for transferring data, such as RAM, is required. A further object of this invention is FI
Multicast is possible by combining a slave that has a storage device that does not require updating the internal address of the storage device (such as FO), and a slave that has a storage device that needs updating the local address, such as RAM. Another object is to provide a simple transfer control device.

[0007]

In order to solve the above problems, a first invention comprises a master side transfer control device and a plurality of slave side transfer control devices connected via a bus,
The address space of each slave-side transfer control device that can be directly used via the bus is continuously arranged at an arbitrary position on the address space that can be used in the entire computer system, and the master-side transfer control device and the slave side are arranged. A transfer control device that transfers data to and from the transfer control device includes the following devices. The master-side transfer control device has information indicating a combination of slave-side transfer control devices to be selected from the plurality of slave-side transfer control devices and an address for inputting / outputting data to / from the input / output device of the slave-side transfer control device. And an address transmitting device for transmitting an address including a local address indicating

The slave side transfer control device is
It is determined whether or not the address transmitted from the address transmission device is included in the address space continuously arranged in the slave side transfer control device, and when it is included, the region determination signal indicates activity. If not included, information indicating a combination of the first determination device indicating inactivity in the region determination signal and the slave side transfer control device included in the address transmitted from the address transmission device and the slave side transfer control Based on the identification information for identifying the device itself, it is determined whether or not the device itself is selected, and if it is selected, the combination determination signal is active, and if it is not selected, the combination determination signal is displayed. And a second determination device indicating inactivity. Further, when the register which takes in the address sent from the address sending device and outputs the local address included in the address and the area judging signal and the combination judging signal are active, the master side When the data sent from the transfer control device via the bus is input according to the local address, and the area determination signal indicates the activity, and the combination determination signal does not indicate the activity, the data is received. And an input / output device for discarding.

[0009]

According to the first aspect of the invention, since the transfer control device is configured as described above, the address sending device of the master side transfer control device provides the information indicating the combination of the slave transfer control devices to be selected and the local address. And sends an address including the above to the plurality of slave side transfer control devices via the bus.
In the slave side transfer control device, by the first determination device,
It is determined whether the addresses sent from the address sending device are included in the consecutively arranged address space of the device, and if they are included, the region determination signal is active, and if they are not included, the region determination signal is sent. Shows inactivity. For example, by arranging all the slave-side transfer control devices of the master-side transfer control device in the same address space, all the slave-side transfer control devices show the area determination signal as active or inactive. When the area determination signal indicates activation, the bus control device sets the signal for controlling the bus state to the state of notifying that it is the selected slave. The second determination device compares the information indicating the combination of the slave-side transfer control devices included in the address sent from the address sending device with the identification information for identifying the slave-side transfer control device itself, and then the own device Is selected. If it is selected, the combination determination signal is active, and if it is not selected, the combination determination signal is inactive. When the area determination signal and the combination determination signal are active, the input / output device receives the data according to the local address and receives the data when the area determination signal is active but the combination determination signal is inactive. throw away. Therefore, in the case where it is necessary to allocate consecutive address spaces such as Futurebus +, multicasting becomes possible, and by specifying the local address in the address from the master side transfer control device, the local address of RAM etc. In the slave-side transfer control device having an input / output device that needs to be changed, dynamic multicast can be performed. Therefore, the above problem can be solved.

[0010]

First Embodiment FIG. 1 is a block diagram showing a transfer control device according to a first embodiment of the present invention. The transfer control device of the first embodiment of the present invention is different from the conventional transfer control device in that, in the master side transfer control device 1, combination information of slave side transfer control devices to be selected by the address sending device 3 and slaves are selected. That is, the address S3 including the local address indicating the address input to the input / output device of the side transfer control device is transmitted via the bus 5. Slave side transfer control device 1
In 1a, if the address S3 sent from the address sending device 3 is included in the address space of the device itself,
If the area determination signal S13a-1 is active and is not included in the area determination signal S13a-1, if the area determination device is selected as the first semi-determining device that is inactive in the area determination signal and the device itself is selected in the combination information, If the combination determination signal is active and is not selected, the combination determination signal is inactive. As a second determination device, if the area determination signal and the combination determination signal are active, the selection signal is activated. Is provided, and if not, an AND element showing inactivity in the selection signal is provided,
This means that the input / output device operates so as to input the data when the selection signal indicates the activation and to receive the data when the selection signal indicates the inactivation. In the slave side transfer control device 11b, in addition to the same device as the slave side transfer control device 11a, a register for outputting a local address included in the address to the input / output device is provided, and the input / output device outputs data according to the local address. That's what I entered.

As shown in FIG. 1, the transfer control device of the first embodiment comprises a master side transfer control 1 and a plurality of slave side transfer control devices 11a and 11b which are connected via a bus 5. . The master-side control transfer device 1 is composed of a bus control device 2, an address sending device 3, and a storage device 4. The bus control device 2 sequentially determines the states of the bus 5 and the timing control signals S2-1 and S2-2 indicating the period for transmitting the address S3 and the data S4 of the selected slave-side transfer control devices 11a and 11b to the bus 5. And has a function of outputting the bus control signal S2-3. The address sending device 3 follows the timing control signal S2-1.
It has a function of transmitting the address S3 to the bus 5. The storage device 4 has a function of sending the data S4 to the bus 5 in accordance with the timing control signal S2-2. The slave-side transfer control device 11a includes a bus control device 12a, an address receiving device 13a, and a storage device 14a.

The bus control device 12a receives the bus control signal S2.
-3, it determines the state of the bus 5 and outputs the timing control signals S12a-1, S12a-2 and the bus control signal S12a-3 that specify the timing of receiving the address S3 and the data S4. The address receiving device 13a receives the address S3 and
When 3 is included in the address space S21a of the device itself, the area determination signal S13a-1 indicating the activity and the area determination signal S13a-1 indicate activity, and when the device itself is selected, selection indicating activity is performed. It has a function of outputting the signal S13a-2. The storage device 14a receives the selection signal S13a-2.
And the data S according to the timing control signal S12a-2.
It has the function of inputting 4. Slave side transfer control device 1
1b has substantially the same configuration as the slave side transfer control device 11a, and includes a bus control device 12b and an address receiving device 13.
b, a storage device 14b, and is different from the slave-side control device 11a.
Therefore, the area determination signal S13b-1 and the selection signal S13b-
In addition to 2, the local address S13b-3 is output. The address S3 includes the combination information of the slave side transfer control devices in order to select the slave side transfer device. This assigns a device number to the slave side transfer control device, associates the device number with the bit position of the address S3 in a one-to-one correspondence, and turns on / off that bit.
By turning off, it indicates whether or not the slave side transfer control device is selected. In general, including n
In order to represent all subsets (combinations of elements) of a set of individual elements (here, the transfer control device on the slave side), an information amount of n bits is required. In this embodiment,
The address S3 is assigned assuming a maximum of eight slave side devices.

FIG. 2 is a diagram for explaining address allocation when a maximum of eight slave side devices are assumed. As shown in FIG. 2, in this embodiment, the information F2 indicating the combination of the devices is placed at the positions A [15] to A [8]. For example, in the present embodiment, each 1 bit of A [15] to A [8] is assigned to select the slave side device. That is, A [15] (1: selects device 7, 0: does not select device 7) ... A [8] (1: selects device 0, 0: does not select device 0). A [7] to A [0] in FIG. 2 are information F3 for representing a local address indicating an address for inputting the data S4 in the storage device of the slave side transfer control device,
A [31] to A [16] are information F1 for indicating the address of the device.
It is. In this embodiment, it is assumed that a 32-bit wide address is used to represent the entire address space of the entire system.

FIG. 3 shows a slave side transfer control device 1 of FIG.
It is a block diagram of the address receiving device 13a in 1a. FIG.
As shown in FIG.
1a, 22a, 23a, area comparator 24a, selector 2
5a and an AND element 26a. The register 21a holds arrangement information S21a (address start S21a-1, address end S21a-2) indicating the address space of the own device, and the area comparator 24
a. The register 22a holds the received address S3, outputs the address A [31: 0] to the area comparator 24a, and outputs the address A [15: 8] to the selector 25a.
It has a function to output to. The register 23a has a function of holding the identification information of its own device, that is, the device number S23a of any one of 0 to 7, and outputting the device number S23a to the selector 25a. The area comparator 24a is
According to the timing control signal S12a-1, the address A
It is determined whether or not [31: 0] is included in the address space S21a of the own device, and if it is included, the area determination signal S24 is activated, and if not included, it is inactive.
It has a function of outputting a to the bus control device 12a and the AND element 26a. In accordance with the timing control signal S12a-1, the selector 25a compares the device combination information A [15: 8] included in the received address S3 with the device number S23a. , The combination determination signal S25a indicating inactivity is output to the AND element 26a.
It has a function to output to. The AND element 26a has a function of outputting activation to the storage device 14a when the area determination signal S13a-1 and the combination determination signal S25a are both active, and active otherwise. Have.

FIG. 4 shows the slave side transfer control device 1 of FIG.
It is a block diagram of the address receiving device 13b in 1b. FIG.
As shown in FIG. 5, the address receiving device 13b in the slave side transfer control device 11b is the slave side transfer control device 11a.
The configuration is almost similar to that of the register 22b.
The local address S13b-3 is output from the lower 8 bits of the address, and the storage device 14b outputs the local address S13b-
That is, the data S4 is input in accordance with the address indicated by 3. Technology for connecting the master side transfer control device adopted in Futurebus + and multiple slave side transfer control devices, that is, using the open collector type bus, glitch filter, and handshake protocol for the bus and bus control device Devices other than the above, including the above, are configured by conventional techniques. The operation ((a) to (d)) of the transfer control device of FIG. 1 will be described below.

(A) Operation of the master-side transfer control device 1 The master-side transfer control device 1 uses the handshake
According to the protocol, the state of the bus 5 (bus transaction state, that is, address output state, data output state, idle state, etc.) is sequentially determined by the bus control signal S2-3, and the address transmission device by the timing control signal S2-1. 3 shows the period for outputting the address S3, and the timing control signal S2-2 shows the period for outputting the data S4. Handshaking protocols include, for example, Future.
The technology adopted by bus + is assumed. The storage device 4 stores the data S4 in the slave side transfer control devices 11a, 1a, 1 according to the timing control signal S2-2 output from the bus control device 2.
It outputs to 1b via the bus 5. Here, in order to simplify the explanation, a FIFO (First In First Out)
Assume t). The storage device 4 sequentially outputs internal data S4 (for example, output from a processor (not shown)) each time the timing control signal S2-2 is activated.

The address sending device 3 sends the address S3 shown in FIG. 2 to the slave side transfer control devices 11a and 1a according to the timing control signal S2-1 output from the bus control device 2.
It outputs to 1b via the bus 5. Here, two slave side devices (device numbers 0 and 2) having the same configuration as the slave side transfer control device 11a in FIG. 1 and one slave side having the same configuration as the slave side transfer control device 11b in FIG. A case will be described where a device (device number 1) is subjected to dynamic multicast with the following combinations. 1st time (multicast to device numbers 0 and 1) Address A [15: 8]: 03h 2nd time (multicast to device numbers 1 and 2) Address A [15: 8]: 06h 3rd time (device number 2 and 0) Multicast to address) A [15: 8]: 05h Three slave side devices to be multicast are continuously arranged at the same position in the address space of the entire system, for example. Address of these three slave devices
The value of A [31:16] is 0001h. The value of A [7: 0] is
00h, 01h for the second time, and 00h for the third time. Therefore, in this dynamic multicast, the address sending device 3
Then, the address S3 shown below is transmitted. 1st address A [31: 0]: 0001-0300h 2nd address A [31: 0]: 0001-0601h 3rd address A [31: 0]: 0001-0500h (b) Slave side transfer control device Operation of 11a In general, the slave side device receives the address S3 to determine whether or not the self side device corresponds to the selected slave. Therefore, all slave devices on the bus 5
At the beginning of the transaction, the address S3 is received.
The bus controller 12a uses the bus control signal S2-3 in accordance with the handshake protocol of the bus 5 to send the bus 5 signal.
The states (address output period, data output period, etc.) are sequentially determined, and the timing of inputting an address to the address receiving device 13a by the timing signal S12a-1 is shown. When the address receiving device 13a corresponds to the slave whose device is selected by the area determination signal S13a-1, the bus control device 12a determines the state of the bus 5 by the bus control signal S12a-3 according to the handshake protocol of the bus 5. A period during which the data S4 is sequentially determined and input to the storage device 14a by the timing control signal S12a-2 is shown.

When the storage device 14a is selected by the selection signal S13a-2 output by the address receiving device 13a, the storage device 14a stores the data S4 in accordance with the timing control signal S12a-2 output by the bus control device 12a.
From the master side transfer control device 1 via the bus 5. Here, it is assumed that the storage device 14a is a FIFO whose write address is not changed. The memory device 14a internally stores the data S when the selection signal S13a-2 is activated and the timing control signal S12a-2 is activated.
Enter 4 sequentially. The address receiving device 13a receives the timing control signal S12a- output from the bus control device 12a.
An area in which the address S3 is input from the master-side transfer control device 1 via the bus 5 according to 1 and is active if the address S3 is included in the address space of the own device, and inactive if not included. The determination signal S13a-1 is output to the bus control device 12a, the region determination signal S13a-1 indicates activity, and if the device itself is selected by the information F2 indicating the combination of devices, activity is indicated, and otherwise. , And outputs a selection signal S13a-2 indicating inactivity to the storage device 14a.

(C) Operation of the slave side transfer control device 11b The bus control device 12b operates in the same manner as the bus control device 12a. Selection signal S output by the address receiving device 13b
When the storage device 14a is selected by 13b-2, the storage device 14b inputs the data S4 from the master side transfer control device 1 via the bus 5 in accordance with the timing control signal S11b-2 output by the bus control device 12b. . Here, it is assumed that the storage device 14b is a random access memory (RAM) whose write address can be changed. Storage device 1
4b is the local address A output from the address receiving device 13b every time the selection signal S13b-2 is activated and the timing control signal S12b-2 is activated.
The data S4 is sequentially input according to the address (may be an address address, page address, segment number, etc.) shown on [7: 0]. Address receiving device 13
b, in addition to the same operation as the address receiving device 13a,
The local address S13b-4 is output to the storage device 14b.

(D) Operation of three slave-side transfer control devices in the first time (multicast to device numbers 0 and 1) The arrangement information S21a and S21b of the own device in FIGS.
The same information is used for any of the three slave side devices (device numbers 0, 1, 2). In the case of the present embodiment, the address S21a-indicating the start of the space of the own device.
1, S21b-1 is 0001-0000h, and addresses S21a-2 and S21b-2 indicating the end are 0001-FFFFh. The identification information 23a, 23b of the own device is different for each of the three slave devices, and device numbers 0, 1, 2 are given respectively. In the area comparators 24a and 24b, the received address S3 is the arrangement information S21a and S21b of the own device.
, The timing signal S1
The area determination signals S13a-1 and S13b-1 are active at timings based on 2a-1 and S12b-1. In the case of the address S3, the area determiners 24a and 24b in all the three slave side devices have the area determination signal S13a.
-1, S13b-1 shows activity. In all of the three slave side devices, the address receiving devices 11a and 11b show activity in the area determination signals S13a-1 and S13b-1,
The bus controllers 12a and 12b indicate that the own device corresponds to the selected slave. As a result, the bus control device 1
2a and 12b sequentially determine the state of the bus 5 according to the handshake protocol of the bus 5, and the timing control signals S12a-2 and S12b-2 cause the storage device 14a,
The time when data is input to 14b is shown. Selector 25
When the received address S3 includes the identification information S23a of the own device, the timing control signal S12a-
The combination determination signal S25a is activated at a timing based on 1.

The operation on each slave side is performed by the first address S
The case where 3 is received will be described. In the slave side device having the device number 0, the operation proceeds as follows. In the received address S3, the bit A [8] designating the device 0 is included in the information A [15: 8] indicating the combination of the slave devices.
Is on, the selector 25a indicates that the combination determination signal S25a is active. Area determination signal S13a-1
Since the combination determination signal S25a is active,
The ND element 26a is active in the selection signal S13a-2.
Since the address receiving device 13a is active in the selection signal S13a-2, the storage device 14a transmits the data S4 from the master side transfer control device 1 via the bus 5 in accordance with the timing control signal S12a-2 output by the bus control device 12a. Enter. In the slave side device whose device number is 1,
The operation proceeds as follows. In the received address S3,
Information A [15: 8] indicating the combination of slave side devices includes
Since the bit A [7] designating the device 1 is on, the selector 25b shows the combination determination signal S25b as active. Area determination signal S13b-1 and combination determination signal S2
Since the activity is shown by 5b, the AND element 26b shows the activity by the selection signal S13b-2. The local address S13b-3 of the received address S3 is output to the storage device 14b.

The address receiving device 13b outputs the selection signal S13.
Since the active state is shown in b-2, the memory device 14b outputs the timing control signal S12b-2 output by the bus control device 12b.
And the local address output by the address receiving device 13b (the first time, address 00h, page address 00h, or 00h
(Segment number etc.) Data S according to S13b-3
4 is input from the master side transfer control device 1 via the bus 5. In the slave side device having the device number 2, the operation proceeds as follows. In the received address S3, the information A [15: 8] indicating the combination of the slave side devices is set to the device 2
Bit A [9] that specifies is off, so selector 2
5a indicates that the combination determination signal S25a is inactive. Since the combination determination signal S25a is inactive even when the area determination signal S13a-1 is active, the AND element 26a is inactive in the selection signal S13a-2. Since the address receiving device 13a indicates that the selection signal S13a-2 is inactive, the memory device 14a transmits the data S4 from the master side transfer control device 1 even if the timing signal S12a-2 output from the bus control device 12a is given. It does not input via the bus 5 and operates to be discarded.

The operation proceeds in the same manner from the second time onward,
The slave side device b having the device number 1 operates as follows when the second address is received. Also in the second time, since the multicast to the slave side device having the device number 1 is designated, the address receiving device 13b indicates the area determination signal S13b-1 to be active and selects the signal S13.
The activity is shown in b-2. Since the address receiving device 13b is active in the selection signal S13b-2, the storage device 14b is
Timing control signal S1 output by the bus control device 12b
2b-2 and the local address output by the address receiving device 13b (the second time, 01h address, 01h page address,
Or 01h segment number etc.) According to S13b-3,
The data S4 is input from the master side transfer control device 1 via the bus 5. In this second time, in order to save the first time data S4, the second time local address S13b-4
Is changed from the first local address S13b-4.

When the third address is received, the operation is as follows. Since the received address S2 does not include the information indicating the slave side device having the device number 1, the selector 25b indicates the combination determination signal S26b to be inactive. Since the combination determination signal S25b is inactive even if the area determination signal S13b-1 is active, the AND element 26b shows the selection signal S11b-2 inactive. Since the address receiving device 11b shows the inactive state of the selection signal S11b-2, the storage device 14b is given the timing control signal S12b-2 from the bus control device 12b and the local address S11b-3 from the address receiving device 11b. Also, the data S4 is not input from the master side transfer control device 1 via the bus 5 and operates to receive and discard the data.

Since each slave side device operates as described above, the following dynamic multicast is carried out. Input operation Discard operation 1st time (multicast to device numbers 0 and 1) Device number 0 and 1 device number 2 2nd time (multicast to device numbers 1 and 2) Device number 1 and 2 device number 0 3rd time (device number) (Multicast to 2, 0) Device number 2, 0 Device number 1 As described above, according to the first embodiment, the address space of each device that can be directly used via the bus is an address that can be used in the entire system. In a computer system that is continuously arranged at an arbitrary position in space, it is possible to perform a multicast in which the combination is frequently changed. It does not require a special bus handshake protocol and can be implemented with a conventional handshake protocol, so there is no need to modify the bus controller itself, and in addition, it is necessary to provide a new signal for multicast on the bus. Absent.
Therefore, the structure is simple and the application range is wide. FIFO
Multicast is possible by combining a slave that has a storage device that does not need to update the local address that writes data to a certain address area, and a slave that has a storage device that needs the local address update, such as RAM. Therefore, the degree of freedom of data transfer in multicast can be improved.

Second Embodiment FIG. 5 is a block diagram of a transfer control device according to a second embodiment of the present invention. Elements common to those in FIG. 1 are designated by common reference numerals. The transfer control device of the second embodiment is different from the transfer control device of the first embodiment in that a counter is provided in the address receiving device 13c of the slave side transfer control device 11c.
The counter value of this counter is used as a local address, and the storage device 14c stores the data S according to the local address.
This means that 4 is input. As shown in FIG. 5, the transfer control device includes a master-side transfer control device 1, a slave-side transfer control device 11 a, and a slave-side transfer control device 11.
The transfer control device in FIG. 1 is the address receiving device 13c in the slave side transfer control device 11c.
However, it is different from the address receiving device 13b in the slave side transfer control device 11b.

FIG. 6 shows the address receiving device 13c shown in FIG.
FIG. The address receiving device 13c shown in FIG.
The difference from the address receiving device 13b is that the selection signal S1
2-2 indicates activation and the timing control signal S12-4 indicates activation, an AND element 27c indicating that the update control signal S27c is activated is provided, and the lower 8 bits of the register 22c holding the received address S3 are Update control signal S
27c is configured by a counter that counts up when it shows activity, and the output of the counter is output to the storage device 14c as the local address S13c-3. The lower 8-bit counter of the register 22c and the AND element 27c constitute a local address generator. FIG. 7 is a diagram for explaining the allocation of addresses used in the second embodiment of the present invention.
Differs from that in that the address A [7: 0] is an unused feed. A technology for connecting a master adopted in Futurebus + and a plurality of selected slaves, that is, an open collector type bus, a glitch filter, and a handshake protocol are applied to the bus 5 and the bus controllers 11a and 11c.
A device other than the above, including that used for the above, is configured by the conventional technique.

The operation of the transfer control device shown in FIG. 5 will be described below. The master-side transfer control device 1 operates similarly to the master-side transfer control device 1 of FIG. The address sending device 3
Timing control signal S2-1 output by the bus control device 2
According to the address S3, the slave side transfer control device 11
It outputs to a and 11c via the bus 5. Here, FIG.
The slave side transfer control device 11a has the same configuration as two slave side devices (device numbers 0 and 2) and the slave side transfer control device 11c in FIG. 5 has the same configuration as one slave side device (device number 1). ), A case of performing dynamic multicast with the following combinations will be described. 1st time (multicast to device numbers 0 and 1) Address A [15: 8]: 03h 2nd time (multicast to device numbers 1 and 2) Address A [15: 8]: 06h 3rd time (device number 2 and 0) Multicast to address) Address A [15: 8]: 05h Three slave side devices to be multicast are placed in the same continuous address space. The value of address A [31:16] of these three slave devices is 001h. Also,
The value of A [7: 0] which is not used in this embodiment is 00h. Therefore, in this dynamic multicast, the address sending device 3 sends the address S3 shown below. First time address A [31: 0]: 0001-0300h Second time address A [31: 0]: 0001-0600h Third time address A [31: 0]: 0001-0500h Operation of slave side transfer control device 11a Operates similarly to the slave-side transfer control device 11a in FIG.

The operation of the slave side transfer control device 11c will be described. The bus control device 12c is the bus control device 12a.
In addition to sequentially determining the state of the bus 5 in accordance with the bus control signal S2-3 and outputting the timing control signal S12c-1 to the address receiving device 13c and the timing control signal S12c-2 to the storage device 14c, the burst When a plurality of data are sent out by one address such as transfer, that is, when the local address of the storage device 14c needs to be updated, the timing control signal S12c-4 is activated for each data. And outputs it to the address receiving device 13c. When the storage device 14c is selected by the selection signal S13c-2 output by the address receiving device 13c, the storage device 14c stores the data S according to the timing control signal 12c-2 output by the bus control device 12c.
4 is input from the master side transfer control device 1 via the bus 5. Here, it is assumed that the storage device 14c is a RAM. When selected, the memory device 14c sequentially inputs the data S4 in accordance with the address indicated by the local address S13c-4 each time the timing control signal S12c-2 is activated. The address receiving device 13c
Timing control signal S1 output by the bus controller 12c
According to 2c-1, the address S3 is input from the master side transfer control device 1 via the bus 5. Similar to the first embodiment, the arrangement information of the own device is 0001-0000h for the address S21c-1 indicating the beginning of the address space of the own device,
The address S21c-2 indicating the end is 0001-FFFFh.
Device numbers 0, 1, and 2, which are different for the three slaves, are given to the identification information S23c of the own device.

The operation of the slave side device having the device number 1 will be described for the case where the first address is received. Since the received address S3 includes the information indicating the combination of the slave side device having the device number 1, the selector 25c
Indicates that the combination determination signal S25c is active. Since the area determination signal S13c-1 and the combination determination signal S25c are active, the AND element 26c is active for the selection signal S13c-2. Select signal S output from AND element 26c
Since the activity is shown in 13c-2, the AND element 27
c is activated by the timing control signal S12c-4 output from the bus controller 12c (when a plurality of data are transferred by one address as described above, the activation is shown for each data). Is indicated, the update control signal S
27c shows activity. In the present embodiment, since the lower 8 bits of the register 22c constitute a counter whose content is incremented by 1 each time the update control signal S27c is activated, the local address S13c-3 is set to the update control signal S.
It increases in increments of 1 each time activity is shown at 27c. Since the address receiving device 13c is active in the selection signal S13c-2, the storage device 14c stores data according to the timing control signal S12c-2 output by the bus control device 12c and the local address S13c-3 output by the address receiving device 13c. S4 is input from the master side transfer control device 1 via the bus 5. Therefore, in the case of burst transfer, a plurality of data S4 is transmitted with one address S3,
The local address is incremented by 1 for each data, and the storage device 14c inputs the data S4 accordingly.

From the second time onward, the operation proceeds in the same manner,
When the slave side device with the device number 1 receives the third address, the operation proceeds as described below. Since the received address S2 does not include information indicating the slave side device having the device number 1, the selector 25c indicates the combination determination signal S25c to be inactive. Area determination signal S
13c-1 even if the activity is shown, the combination determination signal S25c
Is shown to be inactive, the AND element 26c shows the selection signal S13c-2 to be inactive. Since the selection signal S13c-2 output from the AND element 26c is inactive, the AND element 27c outputs the timing control signal S12c-.
Even if 4 is active, the update control signal S27c is inactive. Therefore, the local address S13c-3 is not updated. The address receiving device 13c selects the selection signal S13c.
-2 indicates inactivity, so the storage device 14c receives the timing control signal 11c-2 from the bus control device 11c and the local address 13 from the address reception device 11c.
Even if c-3 is given, the data S4 is not input from the master-side transfer control device 1 via the bus 5 and operates so as to be discarded.

As described above, since each slave device operates, the following dynamic multicast is carried out. Input operation Discard operation 1st time (multicast to device numbers 0 and 1) Device number 0 and 1 device number 2 2nd time (multicast to device numbers 1 and 2) Device number 1 and 2 device number 0 3rd time (device number) Multicast to 2, 0) Device number 2, 0 Device number 1 As described above, the second embodiment has the following advantages in addition to the first embodiment. Since the slave device generates a local address, the above multicast can be performed even in the transfer mode (that is, burst transfer) in which one address and a plurality of data are transferred in one bus transaction. The transfer speed can be improved.

The present invention is not limited to the above embodiment,
Various modifications are possible. For example, there are the following modifications. (1) The address width of the address bus and the allocation of address fields are arbitrary. (2) In the first and second embodiments, the method of expressing the combination of slave side devices and the determination method thereof are not limited to this embodiment. (3) In the second embodiment, the slave side device individually determines the initial value of the local address and does not store the lower 8 bits of the address received via the bus 5 in the register, so that different locals are set for each slave. Multicast, which transfers data to an address, is also possible.

[0034]

As described in detail above, according to the first aspect of the invention, the address sending device sends information indicating the combination of the slave side transfer control device to be selected and the address bus including the local address, If the first device includes the address space of its own device in the address, the area determination signal shows activation, and if the second device selects its own device according to the combination information, the combination determination signal shows activation. As shown, when the area determination signal and the combination determination signal are active, the input / output device receives data according to the local address, and the area determination signal is active, but the combination determination signal is inactive. , Operates to receive and discard data. According to the second invention, the local address is generated by the local address generation device. Therefore, even in a slave-side transfer control device having an input / output device such as a RAM that needs to update a local address, and also in a transfer mode in which one address and a plurality of data are transferred (that is, burst transfer), multicasting is performed. It is possible to improve the speed of data transfer in multicast.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a transfer control device showing a first embodiment of the present invention.

FIG. 2 is a diagram for explaining address allocation in the first embodiment of the present invention.

FIG. 3 is a configuration diagram of an address receiving device 13a in FIG.

FIG. 4 is a configuration diagram of an address receiving device 13b in FIG.

FIG. 5 is a configuration diagram of a transfer control device showing a second embodiment of the present invention.

6 is a configuration diagram of an address receiving device 13c in FIG.

FIG. 7 is a diagram for explaining address allocation in the second embodiment of the present invention.

[Explanation of symbols]

1 master side transfer control device 2, 12a, 12b, 12c bus control device 3 address sending device 4, 14a, 14b, 14c storage device 13a, 13b, 13c address receiving device 21a, 21b, 21c, 22a, 22b, 22c, 2
3a, 23b, 23c register 24a, 24b, 24c area comparator 25a, 25b, 25c selector 26a, 26b, 26c, 27c AND element

Claims (2)

[Claims] 1. An address space of each slave-side transfer control device, which comprises a master-side transfer control device and a plurality of slave-side transfer control devices connected via a bus, and which can be directly used via the bus In a transfer control device, which is continuously arranged at an arbitrary position on an address space that can be used in the entire system and performs data transfer between the master side transfer control device and the slave side transfer control device, the master side transfer control The device has information indicating a combination of slave side transfer control devices selected from the plurality of slave side transfer control devices, and a local address indicating an address for inputting / outputting data to / from the input / output device of the slave side transfer control device. And an address sending device for sending an address including It is determined whether or not the issued address is included in the contiguously arranged address space of the slave side transfer control device, and if it is included, the area determination signal indicates the activity, and if it is not included. Includes a first determination device that shows inactivity in the region determination signal, a bus control device that controls a signal that determines the state of the bus in accordance with the region determination signal, and an address transmitted from the address transmission device. Based on the information indicating the combination of the slave side transfer control device and the identification information for identifying the slave side transfer control device itself, it is determined whether or not the own device is selected, and if it is selected, the combination determination signal Is active, and when it is not selected, the second determination device showing inactivity in the combination determination signal and the address sent from the address sending device are fetched and If the register for outputting the local address included in the local address and the area determination signal and the combination determination signal are active, the data transmitted from the master side transfer control device via the bus is stored in the local An input / output device for inputting according to an address, receiving and discarding the data when the area determination signal is active and the combination determination signal is not active. Control device. 2. A master-side transfer control device and a plurality of slave-side transfer control devices connected via a bus, wherein the address space of each slave-side transfer control device that can be directly used via the bus is stored in a computer. In a transfer control device that is continuously arranged at an arbitrary position on an address space that can be used in the entire system, and performs data transfer between the master side transfer control device and the slave side transfer control device, the master side transfer control The device includes an address sending device that sends an address including information indicating a combination of slave side transfer control devices to be selected from the plurality of slave side transfer control devices, and the slave side transfer control device is the address sending device. Whether the address sent from the slave side transfer control device is included in the consecutively arranged address space A first determination device that indicates that the area determination signal is active when included, and inactive when the area determination signal is not included, and determines the bus state according to the area determination signal. Based on a bus control device for controlling signals, information indicating a combination of the slave side transfer control device included in the address sent from the address sending device, and identification information for identifying the slave side transfer control device itself. A second determination device that determines whether or not its own device is selected and, if selected, indicates that the combination determination signal is active, and otherwise indicates that the combination determination signal is inactive. Based on the area determination signal and the combination determination signal,
When the local address generation device that generates a local address that represents an address input / output by the input / output device, and the area determination signal and the combination determination signal are active, the bus is transferred from the master side transfer control device. When the data transmitted via the local address is input according to the local address, the area determination signal indicates the activity, and the combination determination signal does not indicate the activity, an input / output device that receives the data is discarded. A transfer control device comprising: