JPH03228162A - Unit number setting system - Google Patents

Abstract

PURPOSE:To easily set or change a unit number by storing the unit number, which is transmitted with an intrinsic slot number as an address, into a register when the unit is started, transmitting the new unit number when a change request is generated, and holding the new unit number in the register. CONSTITUTION:A slot number setting circuit 1 is provided to generate the slot number intrinsic for the mounting position of the unit. When starting the unit, the first unit number is transmitted from a controller with the intrinsic slot number as the address and by storing the unit number in a register 5, the unit number is set. Afterwards, communication is executed with this unit number as the address and when the change request is generated, the new unit number is transmitted with the unit number held in the register 5 as the address. Then, by holding the new unit number in the register 5, the unit number is changed. Thus, the unit number can be easily set or changed with the small amount of hardware.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a unit number setting method for appropriately setting or changing unit numbers for each of a plurality of units connected to a bus. .

[Prior art 1] Fig. 2 is a block diagram showing the hardware environment of a general computer system, and Fig. 3 is a block diagram showing the hardware environment of a general computer system.
FIG. 2 is a block diagram showing the configuration of a unit that implements the conventional unit number setting method disclosed in Publication No. 2-226255.

The hardware environment shown in this FIG. Five device adapters 200 .
300.400.500 and 600 are bus 1000
It is connected to the. Each of these device adapters 200~
600 is installed in a predetermined position called a slot for each computer system configuration. Next, in FIG. 3 (here, the device adapter 500 is used as a unit).
1 is configured so that the four level lines can be set to a high potential (+5 volts) or a low potential (0 volts) by permanently opening or grounding the external terminal of the slot. 1 of 16 slot numbers SN that can be expressed by the potentials of 4 level lines
The slot number d, υ, 2 that generates one is when the address mode signal AMD generated by the bus control circuit 14 is
”, selector selects the slot number generated by slot number it circuit 1; when address mode signal AMD is “°1°”, selector selects unit number UN held by register 5; 3 selects register 5 and unit number UN; Any one of the contents of the registers in the register group 8 is selected in response to the register selection signal REG generated by the unit control circuit 15.
4 is the slot number SN selected by the selector 2,
Or, by comparing the contents held in register buffer 9,
A comparator which generates a presence signal PRS (to logic ゛°1°゛) when the two match, and 5 is a control signal CNA activated by the bus control circuit 14 when the bus operation is a unit number setting operation. A register 6 is a control signal CNB to which the contents held in the register buffer 9 (unit number UN in this case) are written in response to the signal WRT.
and a register 7 into which the contents held in the register buffer 9 are written in response to the write signal WRT generated by the unit control circuit 15. A decoder 8 indicates which register it points to; 8 is a register group into which the contents held in the register buffer 9 are written, similar to the register 6;
9. IO is address/data line 110 within bus 1000
0, 11 and 12 to control line 1200 in bus 1000, and 13 to presence line 1 in bus 1000.
Register buffers 14 are connected to 300 and hold signals when transmitting and receiving signals between the bus 1000 and the device adapter 500; 14 is a control input signal MDI from the register buffer 11 and a control signal CNLI from the unit control circuit 15; In response to the presence signal PR3 from the comparator 4, an address mode signal AMD is sent to the selector 2, a control signal CNB is sent to the unit control circuit 15 and the register 6, and an enable signal ANS (for unit connection confirmation) is sent to the register buffer 13. By outputting the control output signal MDO to the register buffer 12 (only during bus operation) and the register buffer 12, the bus i
This is a bus control circuit that operates the device adapter 500 in response to each signal on ooo, and this bus control circuit 14 enables the presence signal PRS only when the control input signal MDI instructs the start of bus operation. look at

15 is a unit control circuit that controls the unit (here, the device adapter 500) while generating a control signal CNU, a write signal WRT, and a register selection signal REG in response to the control signal CNB and the contents held in the register 6. .

Next, the operation will be explained.

First, when the device adapter 500 is installed in the slot with the slot number "4", the selector 2 selects the slot number SN (=4) because the address mode signal AMD is initially set to "0". Therefore, if the unit address on the address/data line 1100 is r4J, the comparator 4 generates the presence signal PRS, and the device adapter 500
and operates in response to a signal on the control line 1200.

Now, when the input/output processor 100 wants to check whether or not a unit is mounted in slot "4", it sends a control input signal MDI to the control line that instructs this and leaves the address mode signal AMD at "0". It also outputs "4" to the unit number designation bit on the address/data line 1100.

This selector 2 selects slot number SN, so
Comparator 4 only in device adapter 500 generates presence signal PR5. Therefore, the device adapter 50
A 0-only bus control circuit 14 generates an enable signal ANS in response to a control input signal MDI, and sends a presence signal PR3 to a presence signal 49 via a register buffer 13.
Output to 1300. The input/output processor 100 checks the presence line 1300 at an appropriate timing and determines the slot number by detecting the presence signal PRS.
You can confirm that the unit is installed in slot 4.

Next, the operation when the device adapter 500 is mounted in the slot number "4" and is desired to operate as a unit with a number different from the slot number, for example "6" will be described.

The turnout processor 100 has an address/data line 1100.
"4" is output to the upper unit number designation bit, and data for designating register 5 and "6" as the unit number are output to the other bits. The control signal MDI that the bus master (in this case, the input/output processor 100) outputs to the control line 1200 is the address mode signal AMD.
is kept at "°0°", the above-mentioned data on the address/data line 1100 is transmitted to the unit control circuit 1.
Registers 6 and 5 in response to write signal WRT generated by
will be written to.

After this, the input/output processor 100 will be placed in slot "4".
When performing a bus operation with the unit number UN, selector 2 outputs a control input signal MDI that switches the address mode signal AMD to "1°°." As a result, selector 2 Since the unit number UN (=6) is selected, the device adapter 500 comes to operate as a unit with the unit number "6".

[Problems to be Solved by the Invention] Since the conventional unit number setting method is configured as described above, one unit has multiple unit numbers that should be uniquely assigned. In addition, a control signal for selecting a unit number is required on the bus, and if a failure occurs in this control signal or the unit number setting circuit in the unit, there are problems such as communication being impossible.

This invention was made in order to solve the problems mentioned in the above 2.It is an object of the present invention to obtain a unit number setting method that can be configured with a small amount of hardware and that can easily set or change the unit number indicating the unit. It is an object.

[Means for Solving the Problems] The unit number setting method according to the present invention transmits the first unit number using the unique slot number of each installed slot as an address only when starting up the unit. The unit number is set by storing the unit number in the register. From now on, communication is performed using this unit number as an address. If there is a change request, a new unit number is set using the unit number held in the register as the address. The unit number is changed by transmitting the new unit number and holding this new unit number in a register.

[Operation] The unit number setting method in this invention performs communication using the unit number at startup as a fixed slot number for each slot in which the unit is installed, and after setting the initial unit number, Each time a new arbitrary unit number is transmitted, the unit number is stored in one register (the contents are rewritten) as the current unit number of the unit, thereby easily changing the unit number.

[Embodiments of the invention] An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a unit that implements a unit number setting method according to an embodiment of the present invention.
In the figure, 1 is a slot number setting circuit that generates a unique slot number SN for each mounting position of the unit, and 2 is a control signal CN output from the reception address decoding section 20.
Accordingly, either the slot number SN (corresponding to the unit number) generated by the slot number setting circuit 1 or the unit number UN held in the register 5 is selected, and the address mode signal is selected as the unit number of the unit. A selector 4 outputs the address mode signal AMD (
a comparator 5 which compares the unit number (corresponding to the unit number) and the destination unit number indicated by the received data stored in the register buffer 9, and generates a presence signal PR3 (theoretically becomes "1") when they match; is a register that holds only the latest unit number UN of the unit in question, and 9 is a register that holds only the latest unit number UN of the unit.
000 is a register buffer that temporarily stores the received data, 10 is a register buffer that temporarily stores the transmission data sent from the unit, and 20 is a register buffer that selects the current unit number every time data is received. At the same time as outputting the control signal CN to the selector 2, it decodes the instruction content of the received data for the unit (recognized by detecting the presence signal PR3 output from the comparator 4), and inputs the instruction to the register 5 according to the instruction content. Reception address decoding section 21 outputting write signal WRT
22 is the comparator 4 which generates transmission data (by adding a unit number to the current unit number and detecting the presence signal PRS) and outputs the generated transmission data to the register buffer 10; detecting the presence signal PR3 output from the register buffer 9 and manually inputting the received data temporarily stored in the register buffer 9;
This is a received data processing unit that executes reception processing.

Next, the operation will be explained.

First, when starting up the unit, the management device (not shown)
Data having the first unit number is transmitted using the slot number SN of the first unit as an address. The transmitted data is temporarily stored in the register buffer 9, and the reception address decoder 20 outputs a control signal CN to the selector 2 to output the slot number SN as an address mode signal AMD. The comparator 4 compares this address mode signal AMD (slot number) with the address of the transmitted data, and if they match, the data is for the unit, so the presence signal PR3 is sent to the reception address decoder 20 and the reception data. It is output to the processing section 22. Reception address decoding section 2
0 detects this presence signal PR3, it outputs a write signal WRT to the register 5 to write the unit number of the received data, and at the same time, the received data processing unit 22 temporarily stores the unit number in the register buffer 9. Input received data and perform reception processing. From then on,
In order to communicate with the management device using the unit number UN set in this register 5 as the address of the unit,
The reception address decoding unit 20 inputs the register 5 to the selector 2.
A control signal CN is output to select the contents (unit number UN).

In addition, the transmission data generation section 21 also outputs an address mode signal AMD (unit number) from the selector 2.
Generate sending data using the address as the address.

On the other hand, when a unit number change request occurs, the received address is decoded by detecting the unit number change flag set in a predetermined area of the received data whose address is the Uni-Soto number currently held in register 5. The unit 20 recognizes the change request and outputs a write signal WRT to the register 5 to change the unit number so that the unit number is rewritten with the new unit number included in the received data. The subsequent communication with the management device is as described above.

〔Effect of the invention〕

As described above, according to the present invention, only when the unit is started up, the first unit number is transmitted using the unique slot number of each installed slot as an address, and this first unit number is stored in the register. After setting the unit number, communication will be performed using this unit number as an address, and if a change request occurs, a new unit number will be sent using the unit number currently held in the register as the address, and this unit number will be used as the address. Since the unit number is changed by storing the new unit number in the register, it is possible to easily set or change any unit number without human intervention with a compact amount of hardware, and it also prevents setting errors. This has the effect of reducing the amount of heat generated and providing an inexpensive device.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the hardware configuration for realizing a unit number setting method according to an embodiment of the present invention, FIG. 2 is a block diagram showing the hardware environment of a general computer system, and FIG. 3 is a conventional FIG. 2 is a block diagram showing the configuration of hardware that implements the unit number setting method of FIG. In the figure, l is a slot number setting circuit, 2 is a selector, 4 is a comparator, 5 is a register, 9.10 is a register buffer, 20 is a reception address decoding section, 21 is a transmission data generation section, and 22 is a reception data processing section. It is. In addition, in the figures, the same reference numerals refer to the same or corresponding parts. Diagram

Claims (1)

[Claims] In a unit mounted in a slot at a predetermined position via a bus, a register is provided for each unit to hold the latest unit number of the unit, and when starting up the unit, the slot number unique to the slot is set. By transmitting a desired unit number from the management device as an address and storing the desired unit number transmitted from this management device in the register, the unit number to be used as an address in subsequent communication with the management device is set. At the same time, by sending a new desired unit number using this unit number as an address, and rewriting the contents of the register with this new desired unit number,
A unit number setting method characterized by changing the unit number.