JPS62295157A - Control system for receiving data in communication control equipment - Google Patents

Abstract

PURPOSE:To refer the data of the latest broadcasting by one switching request by making three bank memories correspond respectively to a data receiving bank, a data updating bank and a data referring bank. CONSTITUTION:The three bank memories is provided with memories 31-33, and either one of these memories 31-33 is connected to a communication line 4 according to the receiving timing of the broadcasting data, another one is connected to a CPU7 through a system bus 6, and the remaining one is not connected to any one. The three bank memories 3 correspond to the data receiving bank, the data updating bank and the data referring bank, respectively, and the CPU7 receives and updates the data by using the data receiving bank and the data updating bank which are not referred.

Description

[Detailed Description of the Invention] 3. Detailed Description of the Invention (Field of Industrial Application) The present invention is a communication control device that transmits and receives broadcast data, etc., to and from other communication equipment via a communication line. The present invention relates to a control method for referring to received data in a CPU.

(Prior Art) Conventionally, as a communication control device of this type, one using a 2-punk memory as a transmitting/receiving buffer for broadcast data is known as shown in FIG. That is, in the figure, 1' is a communication control device, 2 is a 2-bank memory including memories 21 and 22, 4 is a communication line, and 5 is a controller, computer, etc. that sends and receives data via this communication line 4. communication equipment (hereinafter referred to as controller), 6
1 is a system bus, 7 is a central processing unit (hereinafter referred to as CPU), 11 is a memory switching control section, 13 is a system bus control section, and 17 is a reception flag. In addition,
In FIG. 6, the means for transmitting and receiving data with the communication line 4 and the means for interfacing with the system bus 6 on the toilet room are omitted.

An overview of the operation of this communication control device 1' when transmitting and receiving broadcast data to and from another controller 5 via the communication line 4 will be explained. First, at the time of transmission, as shown in the figure, the memory 21 connected to the communication line The memory 22 connected to the CPU 6 is used as a work area for the CPU 7 to prepare new transmission data.

Here, as an operation for changing the broadcast data being sent from the communication control device 1' to the controller 5, the CP
U7 sets new transmission data and then outputs a transmission memory switching request.

In the communication control device 1'', the memory connection is switched via the memory switching control unit 11 in accordance with the switching request. That is, the memory 22 is switched to the communication line 4, and the memory 21 is switched to the system bus 6 side. .

On the other hand, when receiving broadcast data, the memory 21 connected to one communication line 4 is used as a reception buffer for the broadcast data, and the memory 22 connected to the system bus 6 side is used as a reference area for the CPU 7.

Communication control device 1' stores broadcast data on communication line 4 in memory 21 only when reception flag 17 is not set. At this time, if the reception of broadcast data has been completed normally, the reception flag is set to 1.
7 is set so that memory switching can be performed immediately in response to a reception memory switching request from the CPU 7 thereafter. Here, memory switching means switching the memory in the 2-bank memory 2 that was previously connected to the communication line 4 to the system bus 6.
This refers to connecting the memory that was previously connected to the system bus 6 to the communication line 4.

The communication control device 1' does not perform reception processing of new broadcast data when the reception flag 17 is already set, but performs memory switching when accepting a reception memory switching request from the CPU 7.

Then, when memory switching is performed, the reception flag 17 is cleared. Furthermore, between the previous reception memory switching request and the current reception memory switching request, either no new broadcast data was received, or even if it was received, none of it was completed normally. In this case, the reception flag 17 is not set, so the communication control device 1' does not perform memory switching, and the CPU 7 continues to refer to the same broadcast data as the previous time.Here, the CPU 7 first switches the reception memory. output the request,
After the communication control device 1'' accepts the data, the broadcast data is referenced by accessing the two-bank memory 2.

According to the above-described operation, when the CPU 7 outputs a reception memory switching request at a certain period, the update state of the broadcast data that the CPU 7 can refer to is represented by the timing chart in FIG. In FIG. 7, if we pay attention to the relationship between the reception timing of broadcast data and the timing at which the CPU 7 can refer to that data, we can see that the data '1Lld2s' was successfully received for the first time after the reception bank switching request was output from the CPU 7.
d4. It is clear that d, , d7 can be referenced by the next reception memory switching request. Note that in the figure, the symbol x indicates data that cannot be referenced.

From this, if the CPU 7 always outputs a reception memory switching request at a fixed period that is not very long with respect to the refresh period of broadcast data, the CPU 7
7 can always refer to almost the latest broadcast data.

(Problems to be Solved by the Invention) Here, in a distributed processing system in which the CPU 7 attached to the communication control device 1' only monitors and controls the operation of the controller 5, the CPU 7 In order to log occurrences and the status of the controller 5, it is only necessary to refer to the broadcast data sent from time to time via the communication line 4, and in this case, the reception memory may be switched only once irregularly as necessary. All you have to do is output the request.

However, in the conventional control method, as mentioned above, C
Unless the PU7 always outputs reception memory switching requests at regular intervals, it is impossible to refer to almost the latest broadcast data. This results in a situation where the CPU 7 can only refer to worthless data from a long time ago.

Therefore, conventionally, even in cases where it is sufficient to refer to broadcast data as needed, such as in the above-mentioned distributed processing system, the CPU 7 constantly switches the reception memory for one communication control device 1' at a fixed period. Unfortunately, the request had to be output, increasing the load on the CPU 7. In addition, in a method that outputs a reception memory switching request twice when referring to broadcast data, one
It is necessary to set a time sufficient for receiving new broadcast data as the interval between the first and second switching requests, which has the drawback of significantly reducing responsiveness.

Furthermore, as another method, a method may be considered in which the communication control device 1'' itself automatically switches the reception memory when the normal reception of the broadcast data is completed.
According to this, it becomes impossible to synchronize with the processing of CPU 7,
CPU 7. A problem arises in that the broadcast data must be read twice on the side.

The present invention was proposed to solve the above-mentioned problems, and its purpose is that if the C and PU output a switching request only once as necessary, the latest broadcast at that time is always available. Make the data visible to the CPU
An object of the present invention is to provide a communication control method that reduces the load and improves responsiveness.

(Means for Solving the Problems) In order to achieve the above object, the present invention first provides a data receiving bank that stores received data within a receiving area in one communication control device, and a data receiving bank that stores received data in a receiving area in one communication control device, and A data update bank that updates the latest received data, and a CP
A data reference bank that is constantly referenced by U is set respectively.

Then, each memory in the 3-bank memory provided as a reception buffer is made to correspond alternately to the data reception bank, data update bank, and data reference bank according to the data reception timing, and receives a reception bank switching request from the CPU. The present invention is characterized in that the memory corresponding to the data update bank is switched to correspond to the data reference bank, and the latest received data stored in the memory is referred to.

(Function) In the present invention, data is always received and updated in two banks that the CPU does not refer to, namely, a data reception bank and a data update bank, so that the latest received data always corresponds to the data update bank. The latest received data can be referenced by making the memory correspond to a data reference bank in response to a receive bank switching request output from the CPU as necessary.

(Example) The present invention will be described in detail below with reference to the drawings.

FIG. 1 shows a conceptual diagram of a communication control device 1 to which the present invention is applied. This embodiment differs from the conventional example shown in FIG. 6 in that a 3-bank memory 3 is used as a reception buffer for broadcast data. There is.

That is, in FIG. 1, the 3-bank memory 3 includes memories 31 to 33, and one of these memories 31 to 33 is connected to the communication line 4, and another one is connected to the communication line 4 according to the reception timing of broadcast data. One is connected to the CPU 7 via the system path 6, and the remaining one is not connected to anything. In the illustrated example, the memory 31 is connected to the communication line 4, and the memory 33 is connected to the system path 6, but these connection configurations are not fixed.

The other configurations are the same as those shown in FIG. 6, and 5 is another controller, 11 is a memory switching control section, 12 is a communication line control section, 13 is a system bus control section, and 17 is a reception flag. ing.

Next, in FIG. 0, which describes the functions of the three-bank memory 3 with reference to FIG. A data reference bank C to which received data is referenced by the CPU 7 is not connected to either the communication line 4 or the system bus 6, and is a data update bank that constantly stores the latest received data in the data reception block A. show. Here, as mentioned above, banks A to C do not correspond to memories 31, 33, and 32 in FIG.

Among these banks A to C, broadcast data on the communication line 4 is always stored in bank A. If data reception is completed normally, the reception flag 17 is set and bank switching 300 is performed between bank A and bank C.

Here, puncture switching refers to switching the memory corresponding to bank A to correspond to bank C, as will be described later.

Thereafter, each time new data is sent over the communication line 4, the data is stored in bank A, and if reception is completed normally, the reception flag 17 continues to be set. Here, if the reception flag 17 has been set in advance, the set state is maintained. In this state where the reception flag 17 is set, broadcast data is always stored in the memory corresponding to bank C.

On the other hand, when a reception bank switching request is output from the CPU 7 to the communication control device 1, the communication control device 1 checks the reception flag 17. At this time, if the reception flag 17 is set, puncture switching 301 is performed between bank C and bank B, and the reception flag 17 is cleared. Through this process, the latest broadcast data stored in the memory corresponding to bank C corresponds to bank B connected to system bus 6, and this data can be referenced by CPU 7.

FIG. 3 corresponds to FIG. 7 described above, and is a timing chart showing the update state of data in each of the memories 31 to 33 of the three-bank memory 3. In the figure, at the timing of receiving broadcast data d, bank A in FIG. 2 is stored in the memory 32, bank B is stored in the memory 31, and bank C is stored in the memory 33.
correspond to each.

When the reception of data d□ is completed normally, the reception flag 17
is set, and the memory 32.3 corresponding to banks A and C
Puncture switching is performed between 3 and 3. Then, a reception bank switching request is output from the CPU 7, and after confirming the set state of the reception flag 17, the memory 3 corresponding to bank C2B
Punk switching is performed between 3.31 and the reception flag 17 is cleared. As a result, CPU 7
The data d1 can be referred to.

Thereafter, in the same way, data d2 sent after data d1
At the timing of receiving data d3, bank A corresponds to memory 33, and at the timing of receiving data d3, bank A corresponds to memory 31, and in the same way, the memories corresponding to banks B and C change sequentially. , in any case C
If there is a receive bank switching request from PU7, the latest data d4. is checked after checking the receive flag 17. d...
. . . etc. can be referred to in Bank B.

Next, the configuration of the communication control device 1 in this embodiment will be explained in detail based on FIG. 4. In the figure, memories 31 to 33 of the 3-bank memory 3 are allocated to the same address, and these are allocated to each bank A-3.
The bank switching control section 11 performs selection control as to which one of C to correspond to, and the communication line control section 12. The system bus control unit 13 and the CPU 7 do not need to be aware of which memory 31 to 33 they are accessing.

When the communication line control unit 12 receives the broadcast data on the communication line 4, the communication line control unit 12 performs exclusive control of the access rights of the system bus control unit 13 and the 3-bank memory 3, and then transmits the received broadcast data to the 3-bank memory 3. Also, 14 is a bank switching unit designation part, and this bank switching unit designation part 14 writes 3.
It is determined from the accessed address of the bank memory 3 which part of the block which is the unit for bank switching is being accessed, and the block number is output to the bank switching information memory 15 so as to prepare the bank switching information of the block. Note that the bank switching unit designation section 14 is not necessary when the entire system is configured by one switching unit as described above.

On the other hand, the bank switching control section 11 includes a communication line control section 12,
It is checked which of the system bus control units 13 is accessing the 3-bank memory 3, and it is also checked whether the reception normal end 100 and the reception bank switching request 101 from the CPU 7 have been output. If reception normal end 100 is detected, a selection signal is sent to any one of the memories 31 to 33 of the 3-bank memory 3. In addition, the reception bank switching request 10 from the CPU 7
If 1 is detected, new bank switching information is created and the contents of the bank switching information memory 15 are updated.

Next, the format of the bank switching information memory 15 is shown in FIG. 31 to 33 each indicate which bank A to C in FIG. 2 corresponds to.

Note that the operation when transmitting data to another communication control device 5 is the same as the control method for the conventional 2-bank memory, assuming that bank C in FIG. 2 does not exist, so the details will not be described. The description will be omitted.

As described above, in this embodiment, the memory capacity is increased by using the 3-bank memory 3 and the bank switching information memory 15, etc., and the operation of the bank switching control section 11 becomes slightly complicated. Due to the decline in the price of , there is no worry that an increase in memory capacity will be a major factor in increasing hardware costs, and the process of updating the bank switching information memory 15 and the selection sequence of the memories 31 to 33 that are actually selected are Since it can be regarded as a type of conversion table and can be easily realized using a ROM or the like, there is no risk of impairing the usefulness of the present invention.

(Effects of the Invention) As described in detail above, according to the present invention, three banks of memory are made to correspond to the data reception bank, the data update bank, and the data reference bank, respectively, and the data reception bank and the data update bank that are not referred to by the CPU are Since data reception and update processing are performed using the data reference bank, the CPU can always refer to the latest received data in the data reference bank by outputting a receive bank switching request as necessary.

Therefore, when one communication control device is used in a distributed processing system, etc., there is no need for the conventional process where the CPU always outputs a switching request, which reduces the load on the CPU.
It is possible to improve processing capacity.

Furthermore, it is possible to shorten the delay time from when data is received until it can be referenced by the CPU as in the prior art, and it is possible to improve responsiveness.

[Brief explanation of drawings]

FIG. 1 is a schematic block diagram showing an embodiment of a communication control device to which the present invention is applied, FIG. 2 is a conceptual explanatory diagram of a 3-bank memory, and FIG.
A timing chart for explaining the data that can be referenced by the PU, Fig. 4 is a program diagram showing the detailed configuration of the communication control device, Fig. 5 is an explanatory diagram of the format of the bank switching information memory, and Fig. 6 is a conventional diagram. FIG. 7, which is a block diagram of a communication control device showing an example, is a timing chart for explaining data that the CPU can refer to depending on the timing of received data. 1...Communication control device 3...3 bank memory 3
1, 32.33...Memory 4...Communication line 7.
...CPU A...Data reception bank B
...Data update bank C...Data reference bank Figure 1 7...-CPLJ Figure 6

Claims (1)

[Claims] In a communication control device that transmits and receives data to and from other communication equipment via a communication line, and that allows the received data to be referenced upon request from a CPU, the received data is stored within a reception area within the communication control device. A data reception bank that stores the latest received data, a data update bank that updates the latest received data according to the reception timing of the received data, and a data reference bank that is constantly referenced by the CPU are respectively set. The three provided memories are made to correspond alternately to a data reception bank, a data update bank, and a data reference bank according to the reception timing, and the memory corresponding to the data update bank is made to correspond to the data update bank according to a reception bank switching request from the CPU. A method for controlling received data in a communication control device, characterized in that the latest received data in the memory is referred to by switching to a data reference bank.