JPH07135688A - Data communication method and information processing system - Google Patents

Abstract

PURPOSE:To store newest data in a memory by detecting whether or not specific digital information from a serial data communication channel has change during data reception and informing the presence of the change to a central processing unit. CONSTITUTION:The system is provided with a CPU 1, a bus 2, a memory 3, a communication control circuit 5 having a conversion circuit 51 and a register 52, a comparator 7 comprising a register 71 and a comparator circuit 72, an address counter 8 and a write circuit 9. While receiving serial bit string data 6 with tap information from a communication channel L, data of a corresponding old data block 3k stored in the memory 3 based on the tag information are latched in the register 71. Furthermore, the data received by the conversion circuit 51 are latched in the register 52 and both data are compared by the use of the comparator circuit 72 and when dissident, the data in the memory are rewritten.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is directed to a plurality of specific digital information which is periodically transmitted and received between information processing devices connected by a communication path and receives data whether or not the information is changed. The present invention relates to a data communication method and an information processing system in which the central processing unit is informed of the change by being detected therein and the latest data is stored and held in a memory.

[0002]

2. Description of the Related Art In recent years, information processing systems have been increasingly decentralized in order to achieve higher functionality and higher reliability. The information processing devices divided into respective functions are connected by a communication path, and individual digital information is obtained from individual information processing devices. Among the digital information, specific digital information predetermined in the system is The information processing apparatuses periodically communicate with each other via the above-mentioned communication path between upper layers, and are shared and utilized as digital information common to the system by each information processing apparatus.

In recent years, the systematization of information processing apparatuses has spread widely to the area of sensors, and field (field)
Digital information is transmitted and received from devices and sensors installed in the field via the field bus. In many cases, digital information from the site to the information processing device is periodically transmitted via the field bus. In the information processing apparatus connected to the information processing system as described above, in the conventional apparatus, the newly received data or the data block as an aggregate of the data is stored in the memory by temporarily storing the entire received data. In the above, the central processing unit (CPU) stores in the memory the new comparison target data of the new comparison target data block and the old comparison target data of the corresponding old comparison target data block received and stored in the memory before the previous time. When the new comparison target data and the old comparison target data do not match, the old comparison target data is rewritten with the new comparison target data.

FIG. 4 is a schematic diagram of a communication path between upper layers of an information processing system in the prior art. In FIG. 4, the system configuration of the information processing apparatus includes an information processing apparatus (A to D in the illustrated example) and a serial data communication path L, and each information processing apparatus A to D has a function assigned to each role ( Display functions, monitoring / control, data logging, etc.) are performed, and the data group shared / used as a system is defined as a plurality of predetermined types of specific digital information data blocks (31 to 3n) and serialized. Data is shared by periodically transmitting and receiving between the information processing devices via the data communication path L.

Each of the information processing devices A to D has a central processing unit (C
PU) 1, an internal bus 2, memories 3, 4, and a communication control circuit 5 are connected to the serial data communication path L via the communication control circuit 5. In the illustrated example, the data of the new comparison target data block is transmitted from the information processing apparatus B to the information processing apparatus A as the serial bit string data 6. In the memory 3, the latest data received before the previous time is classified and stored in a plurality of predetermined data blocks (31 to 3n) of specific digital information. The serial bit string data 6 of the new comparison target data block newly transmitted from the information processing apparatus B is once written in the memory 4, stored and held as a new data block, and then the central processing unit (CPU) 1
The new comparison target data of the new data block of the memory 4 and the old comparison target of the old comparison target data block (for example, 3k) received before the previous time and stored in the memory 3 and corresponding to the new comparison target data block of the memory 4 Data and data are sequentially read out through the internal bus 2 and comparison processing is performed. When the new comparison target data and the old comparison target data do not match, the data is changed and the old comparison target data is rewritten with the new comparison target data. Was there.

[0006]

As described above, according to the conventional technique, the data of the new comparison target data block received from the communication path is first stored in the memory and then the old comparison data in the memory is stored. The comparison processing is performed with the data content of the target data block. For this reason, a time delay corresponding to the new / old data comparison processing time will inevitably occur until the data change is detected by the new / old data comparison after starting data reception from the communication path, and occupying the internal bus. Time also increases,
There is a restriction on the processing capacity of the central processing unit (CPU).

That is, when new data is received from the communication channel, since new and old data are not compared during reception, new comparison target data that has not actually changed from the old comparison target data, All data from the communication path is once written as new data to the memory via the internal bus, and the data of the new comparison target data block once stored in the memory via the internal bus is transferred to the internal bus for comparison. It is necessary to read again via the internal bus, so that the internal bus is additionally occupied for reading and writing via the internal bus, and the central processing unit (CPU) described above is used.
The presence of the comparison processing by the central processing unit (C
PU) operating time was consumed.

The present invention has been made in view of the above points, and an object thereof is to solve the above-mentioned problems and reduce the comparison processing time of the central processing unit (CPU) and the occupation time of the internal bus. An object of the present invention is to provide a data communication method and an information processing system capable of sharing work with higher functionality.

[0009]

In order to achieve the above-mentioned object, in the invention according to claim 1 of the present application, data communication is performed between a plurality of information processing devices connected via a data communication path, and each information is transmitted. In the data communication method, the processing device compares the received new comparison target data with the already stored old comparison target data and, if they do not match, rewrites the old comparison target data with the new comparison target data. Among the data to be communicated, data to be transmitted / received periodically is divided into one or a plurality of types of data blocks, and is stored and held in a memory as old comparison target data, and An information processing apparatus for transmitting and receiving by adding tag information that can identify the type of this data block to the beginning of the data block of the new comparison target data to be transmitted When the tag information is received, the old comparison target data of the data block specified by the tag information is read from the memory, and the read old comparison target data and the received new comparison target data are compared in parallel with the reception. Then, only when the comparison results do not match, the old comparison target data read out is rewritten to the received new comparison target data and stored in the memory.

Further, in the invention according to claim 2 of the present application, in the information processing system for communicating data between a plurality of information processing devices connected via a data communication path, the information processing device is a communication device. Of the data to
The data that is periodically transmitted / received is divided into one or more types of data blocks, and the memory that stores and holds the old comparison target data and the type of this data block at the beginning of the data block of the new comparison target data that is transmitted And a transmitting unit that transmits by adding tag information that can identify the tag information that is transmitted from another information processing apparatus, and stores the old comparison target data of the data block identified by the tag information in the memory. The reading means for reading from the reading means, the comparing means for comparing the old comparison target data read from the memory by the reading means with the received new comparison target data in parallel with the reception, and the comparison result by the comparing means do not match. And a writing unit that writes the new comparison target data received only in the above case to the storage location of the old comparison target data of the memory.

[0011]

With the above structure, in the present invention, the tag information is added to the head of the new comparison target data block transmitted by the information processing device on the transmitting side, so that the information processing device on the receiving side performs comparison based on the tag information. Specify the memory location where the old data block to be compared is stored,
The first data in the old comparison target data block on the memory is sent to the comparator. On the other hand, in parallel, the first data in the new comparison target data block being received is compared with the data of the old comparison target data block sent to the comparator. As a result of the comparison, the old comparison target data on the memory is overwritten by the newly received new comparison target data only when the new and old data are not equal, and when they are equal, the overwrite is not performed.

After this, the next data of the old data block to be compared is read and sent to the comparator. Then, the comparison operation with the next data of the new comparison target data block being received is similarly continued, and the data in the old comparison target data block and all the data of the new comparison target data block being received are processed as the first data. The data is sequentially compared from the beginning to the end data of the block.

As described above, by providing the mechanism for adding the tag information to the head of the data block, the position on the memory of the old comparison target data block to be compared can be specified, and when the old and new data are not equal. Only by having a mechanism to overwrite the old data in the memory, it is possible to respond while receiving the comparison target data of the new comparison target data block without temporarily storing the entire received new comparison target data block in the memory. The comparison target data in the old comparison target data block can be read, the comparison processing can be performed, and the data reception processing from the data communication path and the comparison processing of the old and new data can be simultaneously processed in parallel, and the latest comparison target data can be processed. The contents of the block can be stored and held in the memory.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is an overall configuration diagram of an information processing system for performing high speed comparison of communication data according to an embodiment of the present invention, FIG. 2 is a block configuration diagram of an information processing device of an embodiment, and FIG. 3 is a high speed communication data. The sequence diagram which performs a comparison operation is shown, and the same code | symbol is attached | subjected to the same member corresponding to FIG.

In FIG. 1, the system configuration of the information processing apparatus comprises an information processing apparatus (A to D in the illustrated example) and a serial data communication path L, and each information processing apparatus A to D.
Perform functions assigned to respective roles (display function, monitoring / control, data logging, etc.), and the data group shared / utilized by at least two or more devices as a system is a plurality of predetermined types. It is defined as a data block (31 to 3n) of specific digital information, and is periodically transmitted and received between the information processing devices via the serial data communication path L to share the data.

Each of the information processing devices A to D has a central processing unit (C
PU) 1, internal bus 2, memory 3, communication control circuit 5
And is connected to the serial data communication path L via the communication control circuit 5. The illustrated example shows the case where the data of the new comparison target data block is transmitted from the information processing device B to the information processing device A, and the serial bit string data 6 at this time is stored at the head of the new comparison target data block. The information processing apparatus B adds and transmits the tag information that can identify the old comparison target data block. In the memory 3 of the information processing apparatus A, among the data received before the previous time, the latest data is classified and stored in a plurality of predetermined data blocks (31 to 3n) of specific digital information. .

In the above configuration, the serial bit string data 6 of the new comparison target data block with tag information newly transmitted from the information processing apparatus B is received by the information processing apparatus A. The information processing apparatus A is receiving the serial bit string data 6 for comparison between the serial bit string data 6 of the new comparison object data block and the old comparison object data of the old comparison object data block corresponding to the new comparison object data block. The old data is rewritten with the new comparison target data only when the new and old comparison target data are not equal, and the central processing unit (CPU) is notified that the new and old data do not match, and the information processing device is notified. Efficiently perform predetermined information processing.

FIG. 2 is an internal block diagram of the information processing apparatus A. In FIG. 2, an information processing apparatus A includes a central processing unit (CPU) 1, an internal bus 2, a memory 3, a communication control circuit 5, a comparator 7, an address counter 8 and a write circuit 9 which are objects of the present invention. , And is connected to the other information processing apparatuses B to D via the communication control circuit 5 and the serial data communication path L. For simplification, the communication control circuit 5 is illustrated here with only the receiving side function, and omits the transmitting side function.

Next, the operation will be described. In the serial bit string data 6, the data block is converted into serial bit string data by the transmitting side function of the information processing apparatus B which starts transmission, tag information is added to this serial bit string data, and tag information + new comparison target data block 6, the information processing device A via the serial data communication path L
Sent to. The serial bit string data 6 of the new comparison target data block with tag information is converted into parallel data by the serial input data / parallel output data conversion circuit 51 of the communication control circuit 5. First, the tag information added to the head of the serial bit string data 6 is converted, and thereafter, the data 1, data 2, ...
Is converted into parallel data.

The tag information converted into parallel data by the conversion circuit 51 is set in the address counter 8 via the data line 22. According to the tag information thus set, the memory 3
The start address of the corresponding data block stored in is selected, and the start address of the memory space of the memory 3 (here, the old data block k) is set via the address line 23.

By this address setting, from the memory 3,
The first data 1 stored in the old data block k is set in the register 71 via the bus 2 and the data line 24. On the other hand, during this period, the first data 1 input via the communication path L is converted into parallel data by the conversion circuit 51 after a lapse of a predetermined bit width equivalent time, latched by the register 52, and stored in the register 71. The data and both data in the register 52 are compared by the comparison circuit 72.

When the two data do not match, the data is output to the write circuit 9 via the control line 25. Based on this command, the write circuit 9 outputs the data latched in the register 52 via the control line 26. The data is written to the corresponding position on the corresponding old data block k of the memory 3 via the data line 27 and the bus 2.
Further, when the data is compared by the comparison circuit 72 and the two data do not match, at the same time, an interrupt notification is sent to the central processing unit (CPU) via the interrupt control line 28 to notify that there is a change in the data. Can efficiently perform predetermined information processing.

If the two data match, the control line 2
The processes of 5 and 28 are not performed, and the preparatory operation for the next data comparison is performed. That is, the address counter 8 is incremented from the control line 22, the address data of the old data block k of the memory 3 is counted up, and the process proceeds to the comparison process of the next received bit width data. Hereinafter, the serial bit string data 6 of the new comparison target data block from the communication path L
While receiving the new data, the new data and the old data are compared in sequence for each constant bit width data.If the two data do not match, the old comparison target data is overwritten with the new comparison target data and the central processing unit (CPU) is interrupted. After notifying and comparing all the data of the corresponding new comparison target data block, the corresponding data in the memory 3 is rewritten only in the portion where the data is changed. The dotted line in FIG. 2 indicates the data flow described above.

FIG. 3 shows a sequence diagram for performing a high speed comparison operation of communication data, in which the horizontal axis shows the time axis flow from left to right.
Received serial bit data string on vertical axis, setting of comparison target data to register 52, setting of address counter 8, sending of old comparison target data to register 71, overwriting of new data when comparison result does not match, and central processing unit The operation timing state of each element of (CPU) is described.

In FIG. 3, the received serial bit data string follows the flow on the time axis from left to right, and in the illustrated example, the tag information, data 1,
The data of data 2, data 3, ... Is sequence 0,
It is continuously received corresponding to 1, 2, 3 ... Below, FIG.
The reception / comparison operation will be described together with. During the period of the sequence 0, in Step 1, the tag information portion of the serial bit string data 6 from the serial communication path L is received by the serial input data / parallel output data conversion circuit 51 and converted into parallel data to generate tag information. It is a period.

Next, in the period of sequence 1, first, in step 3, the tag information generated above is added to the data line.
The address counter 8 is set via 22. The setting data of the address counter 8 selects the head address data of the memory 3 in which the data block transmitted from the communication path L is stored, and the set head address data sets the corresponding old address from the memory 3. The top data 1 of the data block 3k is called, and this data 1 is latched in the register 71 in step 41. On the other hand, Step
As 21, the first data 1 of the data block input via the communication path L has a predetermined bit width (8 bits).
After a lapse of a considerable time (the last time of sequence 1), the conversion circuit 51 converts the data into parallel data 1.

Next, when the period of Sequence 2 is entered, Step
The new comparison target data 1 converted into parallel data by the conversion circuit 51 in 21 is latched in the register 52 in Step 5,
In step 6, it is compared with the old comparison target data 1 already latched in the register 71 in step 41. In the illustrated example, the case where the comparison result does not match is shown here. In this case, the write circuit 9 receives the data of the comparison result mismatch in Step 7, and the data latched in the register 52 is set as the content of the new comparison target data 1. As the overwriting on the old comparison target data 1 in the memory 3,
Store and hold the latest data. Then, in Step 9, the address counter 8 is incremented to the address indicating the next old comparison target data, and in Step 42, the next old comparison target data 2 is latched in the register 71 from the memory 3. At the same time, as Step 8, the central processing unit (CP
By making an interrupt notification to U) and notifying that there is a change in the data, the information processing device can efficiently perform the predetermined information processing. On the other hand, in Step 22, the new comparison target data 2 input via the communication path L is converted into parallel data by the conversion circuit 51 after the time corresponding to 8 bits has elapsed.

Then, the period of sequence 3 is entered, and the previous
In step 22, the conversion circuit 51 converts the data into parallel data, and similarly to the previous time, the new comparison target data 2 latched in the register 52 in step 5 and the old comparison target data 2 already latched in the register 71 in step 42 are step 6 Compared with. In this illustrated example, it is shown that the comparison results match. In this case, the processing to the memory 3 and the central processing unit (CPU) is not performed, the process proceeds to Step 9, the address counter 8 is incremented, and in Step 43. , The next old comparison target data 3 from the memory 3 is latched in the register 71. On the other hand, in Step 23, the new comparison target data 3 input via the communication path L is similarly converted into parallel data by the conversion circuit 51.

Hereinafter, similarly, sequence 4 and sequence 5
.. are continuously performed, and the sequence 4 shows the case where the old and new comparison target data 3 are the same as the sequence 3, and the process performed here is the same as the sequence 3. 5 shows the case where the old and new comparison target data 5 do not match as in the sequence 2, and the processing performed here is the same as that in the sequence 2.

The new comparison target data block input in the form of the serial bit string data 6 via the serial data communication path L is sequentially received and compared with the latest old comparison target data block received before the previous time. Then, only the different data portion is rewritten, the information that the data has changed is notified to the central processing unit (CPU) each time, and this comparison operation is executed until the processing of the entire comparison target data block is completed. As a result, when all the serial bit string data 6 are received and processed, any difference in contents between the new comparison target data block and the old comparison target data block is detected, and the contents of the old comparison target data block in the memory are compared with the new comparison target data block. It is stored and held in place of the contents of the target data block, and subsequent comparison processing by the central processing unit (CPU) is not necessary.

As a result, it is not necessary to read the data of the new data block from the memory and to write the new data unchanged from the old data in the memory for comparing the old and new data blocks. As a result, the above-mentioned bus occupation time can be reduced, the comparison processing by the central processing unit (CPU) can be eliminated, and the consumption of the operating time of the central processing unit (CPU) can be reduced.

[0032]

As described above, according to the configuration of the present invention, the tag information is added to the head of the data block, the position on the memory of the old comparison target data block to be compared is specified, and the address counter is used. The information processing device is equipped with the hardware of the comparator and has the mechanism of overwriting the old data on the memory only when the old and new data do not match.
When receiving new data from the communication path, before storing the new data in the memory, at the same time as receiving the new data, comparing with the latest old data stored in the memory before the last time,
If there is a change, the old data is rewritten with the new data and stored, which reduces the comparison processing time of the central processing unit (CPU) and the occupied time of the internal bus, enabling higher-performance work sharing. High-speed comparison of data can be performed.

[Brief description of drawings]

FIG. 1 is an overall configuration diagram of an information processing system for performing high-speed comparison of communication data according to an embodiment of the present invention

FIG. 2 is a block configuration diagram of an information processing apparatus according to an embodiment.

FIG. 3 is a sequence diagram for performing a high speed comparison operation of communication data.

FIG. 4 is an overall configuration diagram of a conventional information processing system.

[Explanation of symbols]

 1 central processing unit 2 bus 3, 4 memory 31,32,33 ... 3k, 3n old data block 5 communication control circuit 51 conversion circuit 52, 71 register 6 serial bit string data 7 comparator 72 comparison circuit 8 address counter 9 write circuit 21 , 22,23,24,27 Data line 25,26,28 Control line A to D Information processing device L Serial data communication path

Claims (2)

[Claims] 1. A data communication is performed between a plurality of information processing apparatuses connected via a data communication path, and each information processing apparatus compares the received new comparison target data with the already stored old comparison target data. In the data communication method in which the old comparison target data is rewritten to the new comparison target data if they do not match, each information processing device has one or more periodically transmitted / received data among the data to be communicated. The information processing device that divides the data block into a plurality of types of data blocks, stores and retains the old comparison target data in the memory, and transmits the new comparison target data is identified at the beginning of the data block of the new comparison target data to be transmitted. When receiving the tag information, the information processing apparatus that transmits by adding the tag information that can be transmitted and receives the tag information has an old ratio of the data block specified by the tag information. Reading target data from said memory, in parallel with the receiving and the new comparison target data received with the read old comparison target data compared,
A data communication method, characterized in that the old comparison target data read out is rewritten to the received new comparison target data only when the comparison results do not match, and is stored and held in the memory. 2. An information processing system in which data is communicated between a plurality of information processing devices connected via a data communication path, wherein the information processing device periodically transmits data to be communicated. / A memory that divides the received data into one or more types of data blocks and stores and holds it as the old comparison target data, and the beginning of the data block of the new comparison target data to be transmitted,
An old comparison of the data block specified by the transmitting means for adding the tag information capable of specifying the type of this data block and transmitting it and the tag information transmitted from another information processing device. A reading means for reading the target data from the memory; a comparing means for comparing the old comparison target data read from the memory by the reading means with the received new comparison target data in parallel with the reception; An information processing system, comprising: a writing unit that writes the new comparison target data received only when the comparison result according to 1. is in the storage location of the old comparison target data of the memory.