JPS59171158A - Semiconductor memory cell - Google Patents

Abstract

PURPOSE:To enable to realize a large memory capacity and a small cell area at the same time by making a three dimensional structure wherein a transistor part and a capacitor part have the same plane region in common. CONSTITUTION:The capacitor is composed of a polycrystalline Si 26 buried in the recess of the surface of an Si substrate, an Si dioxide film 25, and the Si substrate 21. Besides, an FET including a polycrystalline Si 22 connected to a word line as the gate, a re-crystalline Si 24 connected to a bit line as a drain electrode, and a re-crystalline Si 26' connected to an electrode 26 accumulating capacitor charges as a source electrode is formed on the capacitor. By this structure, an MOSFET is formed on the capacitor and thus hardly leads to the increase of the Si surface area. The elements are surrounded by a groove completely covered with the film 25, and accordingly an isolation region is unnecessitated. Thereby, it is possible to reduce the area without reducing the memory capacity of the memory cell.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a structure of a semiconductor memory cell, and more particularly to a structure of a semiconductor memory cell that realizes a larger storage capacity even in a small area.

Semiconductor memory cells that store binary information in the form of charges have a small cell area, making them excellent as highly integrated, large-capacity memory cells. In particular, memory cells consisting of one transistor and one capacitor (hereinafter abbreviated as 1T1C cells) have few components and can have a small cell area, so they are important as highly integrated memory cells and are currently widely used in large-scale dynamic RAM. It is used.

FIG. 1 shows a schematic cross-sectional view of an example of a conventionally widely used 1T1C cell. In Fig. 1, capacitor electrode 1
A storage capacitor is formed between the inversion layer 16 and the inversion layer 16 . Reference numeral 12 denotes a gate electrode of a switching transistor, which is connected to the word line and controls the movement of charges between the diffusion layer 14 and the inversion layer 16, which are connected to the bit line. Further, 17 is an isolation region from an adjacent memory cell.

In this conventional example, the storage capacity is determined by the area of the capacitor electrode 13 on the inversion layer 16 and the dielectric constant and thickness of the insulating film 15 under the capacitor electrode 13.

That is, there are the following three methods for securing a large storage capacity.

(1) Increase the area of the capacitor electrode.

(2) Reduce the thickness of the insulating film.

(3) Use an insulating film with a high dielectric constant.

By the way, high integration of memories has been achieved by reducing the size of memory cells along with advances in microfabrication technology, and in conventional 1T1C cells, the number of capacitor electrodes is reduced. Therefore, in the 1T1C cell, a significant decrease in storage capacity was prevented by reducing the thickness of the insulating film. However, the thinning of insulating films is approaching its limit.
It is also becoming difficult to manufacture them with high precision.

That is, in the conventional 1T1C cell, it is difficult to secure a large storage capacity unless an insulating film with a high dielectric constant is used. Moreover, insulating films with high dielectric constants are currently in the exploratory stage and there is no prospect that they will be put to practical use in the near future.

As described above, the conventional 1T1C cell has the problem that it is difficult to secure a large storage capacity with a small cell area. Due to the recent problem of information destruction caused by alpha particles, it is desired that memory cells have a storage capacity of about 50 fF so that the memory contents will not be destroyed by the incidence of at least one alpha particle. This makes downsizing even more difficult.

The problems of the conventional 1T1C cell described above are the problems of the conventional 1T1C cell.
This is due to the fact that the T1C cell has a planar structure.

That is, as shown in FIG. 1, the transistor section and the capacitor section are formed in separate planar regions. That is, it is thought that the problems of the 1T1C cell can be significantly alleviated by creating a three-dimensional structure in which the transistor section and the capacitor section share the same plane area.

An object of the present invention is to provide a semiconductor memory cell with a novel three-dimensional structure that can improve the drawbacks of the conventional 1T1C cell and have a larger storage capacity even in a small area. .

According to the present invention, there is provided a semiconductor substrate having a recessed portion on its surface, a first insulating material formed at least on the surface of the recessed portion of the semiconductor substrate, and a first insulating material formed on the first insulating material within the recessed portion of the semiconductor substrate. a capacitor made of a conductive material;
a second conductive material that is a gate electrode formed on the first conductive material via a second insulating material; a third insulating material that covers the second conductive material and serves as a gate insulating film; a third electrically conductive material that is a source electrode in contact with the third insulating material and electrically connected to the first electrically conductive material;
a semiconductor material serving as a channel portion formed in contact with the third conductive material and the third insulating material; a fourth material serving as a drain electrode formed in contact with the semiconductor material and the third insulating material; A semiconductor memory cell is obtained, characterized in that it includes a field effect transistor made of a conductive material.

The present invention will be described in detail below with reference to the drawings. Second
The figure shows a schematic cross-sectional view of a typical embodiment of the present invention, in which 21 is a single crystal silicon substrate, 22 and 26 are polycrystalline silicon, and 24, 26', and 28 are polycrystalline silicon substrates. Crystallized material (hereinafter referred to as recrystallized silicon)25
, 30, 29, and 31 indicate silicon dioxide films.

In FIG. 2, a capacitor is formed by polycrystalline silicon 26 buried in a recessed portion on the surface of a silicon substrate, a silicon dioxide film 25, and a silicon substrate 21.

Further, the polycrystalline silicon 22 connected to the word line on the upper part of the capacitor is used as the gate, the recrystallized silicon 24 connected to the bit line is used as the drain electrode, and the recrystallized silicon 26' connected to the electrode 26 that stores the charge of the capacitor. A field effect transistor is formed having the source electrode as the source electrode.

In the embodiment shown in FIG. 2, information on the bit line is transferred from the recrystallized silicon 24 connected to the bit line by turning on the switching transistor connected to the word line. 28
The data is stored in the polycrystalline silicon 26 formed in the substrate via the recrystallized silicon 26' which is the source electrode.

Let us compare FIG. 2, which is an embodiment of the present invention, with FIG. 1, which shows a conventional 1T1C. Let's start by comparing the capacitor part. Capacitor electrode 13 and charge storage region 16 in FIG. 1 correspond to silicon substrate 21 and polycrystalline silicon 26 embedded in the substrate, respectively, in FIG. 2. Therefore, in the semiconductor memory cell of the present invention, the conventional 1T1C
It will be easily understood that it has a much larger storage capacity in the same plane area than a cell. If the silicon surface area is the same, and if the thickness of the silicon dioxide film between both electrodes of the capacitor is the same in the case of the present invention and the conventional 1T1C cell, then the storage capacity of the conventional 1T1C cell is equal to that of the trench bottom of the memory cell according to the present invention. The storage capacity of the cell increases by the capacity of the groove side surface, and the storage capacity can be easily increased by increasing the depth of the groove. Next M
Let's compare OSFETs.

In Figure 1, the MOSFET is placed next to the capacitor, while in Figure 2, the MOSFET is placed above the capacitor.
It can be seen that a FET is formed, resulting in little increase in silicon surface area. In other words, the surface area of the silicon substrate required to store one bit of information is approximately the size of one transistor. In currently produced large-capacity dynamic RAMs using 1T1C cells, the storage capacitor portion accounts for nearly 50% of the cell area including the isolation region, which is larger than the area occupied by the transistor. There is. From this, it will be clear how effective the advantage of the present invention is that the area of the memory cell having a three-dimensional structure can be reduced without reducing the storage capacity.

Furthermore, the conventional 1T1C cell had the problem that the element isolation region occupied a large area, but according to the present invention, as can be easily understood from FIG. 2, the element is completely covered with the silicon dioxide film 25. There is no need for an isolation region. In this respect as well, it can be said that the present invention has a structure suitable for miniaturization. Furthermore, by grounding the silicon substrate 21, the influence of coupling noise via the substrate can be suppressed.

Next, the manufacturing process of the embodiment shown in FIG. 2 will be described. For the capacitor part using a groove, after forming the groove by etching, a silicon dioxide film 25 is formed by a thermal oxidation method.
This can be easily formed by growing polycrystalline silicon 26 and filling the inside of the trench with polycrystalline silicon 26 by CVD or the like. MOSFE
For the T part, after forming the capacitor part, a silicon dioxide film 30 is formed on the entire surface, polycrystalline silicon is further grown thereon, and a gate 22 is formed by photo-etching. Thereafter, a silicon dioxide film 29 is grown again, a hole is made on the capacitor polycrystalline silicon by a photoetching process, and then polycrystalline silicon that will become the source, channel, and drain is deposited. In order to form the source, channel, and drain regions, laser annealing technology and ion implantation technology may be effectively used to recrystallize polycrystalline silicon and form an impurity profile.

Further, the portions to be recrystallized are not limited to the source, gate, and drain, and may be recrystallized from polycrystalline silicon 26.

As briefly described above, the semiconductor memory cell according to the present invention can be manufactured using a MOS manufacturing process that has been commonly used in the past. Further, as described above, according to the present invention, it is possible to simultaneously realize a large storage capacity and a small cell area, and a semiconductor memory cell suitable for high integration can be obtained, which is very effective.

[Brief explanation of the drawing]

FIG. 1 is a schematic cross-sectional view of a conventional 1T1C memory cell, and FIG. 2 is a schematic cross-sectional view of a memory cell according to the present invention. The numbers in the diagram are 11... Silicon substrate, 12...
...Gate electrode connected to the word line, 13...
・・・・・・Capacitor electrode. 14... Diffusion layer connected to the bit line,
15... Silicon dioxide film, 16...
...Inversion layer, 17...Element isolation region, 21...Silicon substrate, 22, 2
6... Polycrystalline silicon, 24, 26',
28・・・・・・Recrystallized silicon, 25, 29,
30, 31... Indicates a silicon dioxide film. Representative Patent Attorney Shinji Hara Figure 1 Figure 2

Claims (1)

[Claims] a semiconductor substrate having a recess on its surface; a first insulating material formed on at least the surface of the semiconductor substrate recess; a first insulating material formed on the first insulating material in the semiconductor substrate recess;
a capacitor made of a conductive material, a second conductive material serving as a gate electrode formed on the first conductive material via a second insulating material, and covering the second conductive material; a third insulating material serving as a gate insulating film; a third conductive material serving as a source electrode in contact with the third insulating material and electrically connected to the first conductive material; A semiconductor material serving as a channel portion formed in contact with a conductive material and the third insulating material, and a fourth conductive material serving as a drain electrode formed in contact with the semiconductor material and the third insulating material. A semiconductor memory cell characterized by comprising a field effect transistor consisting of a field effect transistor.