JPS59171156A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain an I<2>L circuit of a remarkably high speed and less consumed power by a method wherein an insulation layer having an aperture is formed on a semiconductor substrate, a semiconductor layer is provided thereon, and, when a vertical bi-polar transistor performing also reverse directional action is formed therein, the distribution of impurity concentration of the semiconductor layer is made reverse to normal, i.e., high concentration in the substrate side and lower concentrations as it goes away therefrom. CONSTITUTION:The insulation layer 2 having the fixed aperture is adhered on the semiconductor substrate 1, and the N<-> type layer 3 serving as the base of a P-N-P transistor and as the isolation region of an N-P-N element is grown thereon. Then, a P type base region 4 of an N-P-N element constituting the I<2>L is diffusion-formed therein. At this time, the impurity concentration of the region 4 is kept reduced from lower to upper, an N<+> type emitter region 5 is diffusion- formed in the aperture, and an N<+> type collector region 7 is provided in opposition thereto. Thereafter, a P type injector region 8 and an N<+> type base region 9 of the P-N-P element are provided in the layer 3 in adjacency to the region 4.

Description

[Detailed description of the invention]

"Utilization of the invention", F] The present invention relates to a semiconductor integrated circuit device.4.1
．． It is absolutely necessary to partially embed it in the 1'R material base, and this υ
) A 1' heart-body integrated circuit which is based on the idea of having a hole cut out in the insulating material and an electrical conductor part 7 between the conductor part and the conductive substrate. It is related to the device. Of invention! , 7-11] Conventionally, the integrated l) path, especially i I +, , (lnL
Leaf ra1. c, d[n j c c t , i, o
n I, o g, ic ) is called 1 year old 1 i person theory J! l 1111;, lF, 1 has the '11 characteristics of low power consumption and high integration density.
Compared to the 8 circuit, the disadvantage is that it is slow (, 1') + 1! −, N l in the circuit
'> Is the impurity level of the emitter of the transistor low? Electrification is applied to the minority carrier's forward i corner! ('1 and -) te -1, It is easy to achieve low power consumption in

[N l' N l・-
Non-sistor joint capacity steel carving depth tL
, To the other side, Eminta and Koretata side:, Munemono JV
, "e 11.1 should not be affected a little.However, ;4:(Ka'゛)l l L l";it'i:Then, if we lower the impurity concentration, :0・There is a situation in which one hundred and one minute margin is not available.
The 1111 has been upgraded to a high-performance version of the '3 i, with even lower power consumption. [Summary of the Invention] The present invention eliminates the above-mentioned drawbacks and provides a semiconductor integrated circuit that is several times faster than conventional IIL circuits and consumes less power. [Summary of the Invention] The present invention provides an impurity concentration distribution in a region forming a vertical bipolar transistor that also operates in the reverse direction, with the impurity concentration distribution being in the opposite direction from the original, that is, the concentration is high on the substrate side, and the impurity concentration is high on the substrate side. Accordingly, it is constructed to have a low concentration.
□ Also, to increase the injection rate during reverse direction operation, the base
The area of the emitter junction surface and the base/collector junction surface are approximately equal. [Embodiments of the Invention] The undiscovered invention will be described in detail below with reference to Examples. FIG. 1 shows a first embodiment of a semiconductor integrated circuit device according to the present invention. Figure 1 (a,) is a structural sectional view, and (b)
) is its equivalent, the circuit! be. 8 in the first [m(a)
is the injector area, and 101 is its terminal. Reference numeral 9 denotes a high concentration region formed in order to take out the base terminal 102 of a PNI transistor corresponding to an injector. 4. is 1■' N that makes up L
PNI is the base region of the transistor, and 103 is its terminal. This base region is formed so that the impurity concentration decreases from bottom to top and has a uniform distribution. 7 is N, PNl - the collector area of the transistor, and 10
4 is its terminal. 5 is an N P N + - transistor, and l is a semiconductor layer with a low obtuse concentration that makes ohmic contact with this emitter region, and serves as the base region of the P'''N, P transistor, and also serves as the base region of each NPN + - transistor. The layers 6 and 2 are the upper and lower insulating layers, respectively. (1) The emitter of the NPN transistor is impurity!
- is higher, and : is a minority gear. There is almost no dirt on the rear. (,,2), N, P''N Transistor Since the impurity concentration is distributed from the transistor side to the collector side, the electrons injected from the emitter are accelerated by the internal electric field. ( 3) The upper and lower parts of the NPN transistor are in contact with the insulating layer, so the junction capacitance is less than half that of conventional elements.2. It is possible to independently extract and apply any voltage or voltage.In other words, it is possible to apply a voltage such that the junction between the base and collector of the PNP transistor (N, the base of the PN transistor) is always reverse biased. , for this reason, the PNP transistor does not saturate, so the accumulation of minority carriers due to the base saturation of the P N, P transistor is reduced to 91 times. Based on the above principles, the flat PN transistor is better than the conventional sushi circuit. It can be seen that the performance of the NPN transistor according to the present invention has been greatly improved.In particular, the current amplification factor of the conventional inverse p P, N transistor filter was about 10, whereas the current amplification factor of F1 was about 10.
50 or more can be obtained with an I-transistor. Furthermore, the frequency characteristics are also conventional, 1 is:”' 7,719. Wi, H
7, compared to the 1st invention, fTMo 300M
It can be seen that Hz is obtained and clearly improved. Next, a method of manufacturing a structure according to the present invention will now be described. - The figure is a diagram showing the main manufacturing process of ri. In Figure 2 (,1), the substrate 10 has an impurity concentration of
, 't, ``Oio, Clll7'' or more, one product has approximately 5 N-type layers on the lower surface.
It is possible to selectively grow P-type N? Form J4 and 8. Then, six holes are selectively formed in the four oxide circles 2 patterned on the surface. , , 4 are made in the lower surface of the P-type layer 4 . However, this hole should be punched not only on the bottom surface of the P-type layer 4 but also on the bottom surface of the epitaxial layer 3.
, & Touge (Figure (b)), move to the workshop. , (b) shows the diffusion of the nine culms drilled in (a) of the same figure, forming a high N↑-shaped 脣5 in the middle of the half-cinene folklore monument. After that, conductive layer 1 is formed so that the opening and opening portions are exposed. Ru. , this conductor can be formed by depositing N1-doped polysilicon. In addition, when forming the electrocardiographic layer 1, the N-type layer 5 marked 1" is the same as 116.
It is also possible to form j + J. When N-type doped polysilicon is deposited on the Tz plane from the state shown in (d), an N-type layer is formed from the open part of the upper surface due to the thermal process at F'. is deformed at the same time. Next, the process moves to the step shown in FIG. (In step (1), the first substrate 10 is removed. To remove the substrate 10, concentration difference etching using a mixed etchant of hydronic acid, nitric acid, and acetic acid can be used. In the case of concentration difference etching, one side When the impurity concentration of the conductor layer is about 10"cm-1 and the impurity concentration of the other 1 (the impurity concentration of the conductor layer is one order of magnitude lower than that of the other one), the etching speed differs by about two orders of magnitude. Etching occurs quickly.For this reason, even if the substrate 10 has initial thickness variations, the etching stops at the interface with the N-type layer 3 and the P-type layer 4.After this, as shown in FIG. The N layers 7 and 9 are formed by diffusion or other methods from the top surface as described above.Finally, holes are made to count the number of each terminal and the electrodes are spaced by f''.The final result is shown in Figure 1 (a).
) is 3. Figure 3 shows the second embodiment of the present invention.
l*+(a) is a structural cross-sectional view, and ())) is part 1.
It is a monovalent circuit. In Figure 3, the N-type layer 10 shown in Figure 1 is formed 7, and a contact hole 1 is formed between this layer and the electrode so that the output is not handled4.j)'
l:L:, 11 is formed by the N-type semiconductor layer and the metal end r.
, Notoki contact 1 is part 1, like this'so 1
A logic circuit in which a hex diode is formed on the output side has a small logic amplitude, so it can be operated at 6 speeds (1), and the junction capacitance between the base and collector is also reduced, making it faster. The figure shows a third embodiment of the present invention.In this embodiment, F
'N P l-Heath region 5 of transistor] IgNl
Six holes are formed in the upper insulating layer 2 using the same method as the emitter region 1 or 5 of the 'N transistor. This region 9 is electrically connected to the emitter region 5 of the transistor N1)N'1 through the conductive layer 1. The embodiment shown in Fig. 4 has the same circuit (φ'1 configuration) as the conventional IIL circuit.If this configuration is adopted, the power supply voltage applied to the 11 circuit can be made the lowest. It can be done..Also, apply another potential to the base of f]N Pl-transistor!
Since there is no need to increase the circuit configuration, the circuit configuration is very simplej)1. become. FIG. 5 shows a fourth embodiment of the present invention. In the case of this embodiment, the terminal 105 of the conductive layer 1 is taken out through the N1 region 192 which is deeper than the semiconductor layer 1. It has the advantage that it can be used even if the pedestal is not conductive. 6F] (a) and (b) are the fifth embodiments of the present invention. FIG. 6(a) of this embodiment shows the injector 8 and N
A Y) region 13 with a high impurity concentration is formed in the base region 4 of the pN F transistor from the top surface of the semiconductor using the well-known diffusion θ, B) ion implantation method, etc. 3. Such an I1 head region 3? By forming at ℃, it is possible to prevent the 1 inversion layer that is likely to occur at the interface with the insulating layer [), and it is better to use IfJ or omitter contact when taking out the injector terminal 101 or the base end 1'+03. 1
It will be destroyed. Furthermore, the impurity concentration distribution (true Y) region 13 directly under the base terminal 103 of the N P N l- transistor
As a result, the distribution decreases in the depth direction, so the injected resistive current f'(') to the emitter decreases, and the component toward this region 13 increases, and the rate of 1 is It gets colder,
The number of electrons to be accumulated is small and high-speed operation is possible.
It goes without saying that the same figure (1)) has the same advantage as the same figure (,).
) is an exemplary embodiment in which the injector is formed by diffusion or ion implantation method. . In this case, there is a point where it becomes easier to master the horizontal I) N P I- transistors. FIGS. 7(a) and (b) show a sixth embodiment of the present invention. This example shows that a normal N F' N + -runcisor can be easily formed.1. Figure (d) shows the first
I i 1 in the figure. , forming the emitter region 5 of the circuit's N F' N
- The region 5 which becomes the emitter (or collector) of the transistor is separated from the conductive layer 1 by providing an insulating layer. , also JIL
The injector region I of the circuit is used as the injector region I of the normal NPNB transistor. It is used in various ways. FIG. 6(b) shows a method of forming a conventional N P transistor using the shallow P region 13 shown in the embodiment of FIG. An N transistor can also be formed. FIG. 8 shows a seventh embodiment according to the present invention. In this embodiment, the transistors of P N P 1 to J of the 1■L circuit are also vertical.
- It is designed to further improve performance as a transistor. NP in the same figure? ! J Base region of transistor 4. The emitter region 5 is constructed in the same manner as in FIG. In the same figure, a low concentration N region]5 is formed from the top surface, and P
,N,I? +=base area of transistor. Further, a highly concentrated P region 13 is formed in this N region 15 to form an injector. A high concentration N region 9 is formed for taking out the base terminal of P'N'P1~transistor. N-1) N)-Range collectors are P N, I
) can be formed at the same time as forming the base of the transistor. Although not shown in the figure, when forming the collector of an NPN transistor with a low-concentration N region 15, a Schottky contact between this N region and a metal terminal is required.
Form the ta-to and shoot the output to 1 as shown in Figure 3.
It is also possible to take it out via a kidney diode. When the PINP transisister is used as a longitudinal 1-transistor as in the Kinotsu example, the reactive current in the injector becomes extremely small, and it operates with lower power consumption than the conventional i' I '''L circuit. - Figure 9 is an eighth embodiment according to the present invention. In this embodiment, similarly, a vertical I) NI) '-□ transistor is formed. NI) A deep C1N region 1G is formed to isolate the base of the N+-"Jnlister. In such a case, the penile region of the NFiN transition support can be achieved by epitaxial growth using the conductor P''l.
＼I can do something. In the process of taxial growth, low concentrations of
The advantage of forming a □ layer is that it is possible to reduce the junction capacitance of a transistor by an order of magnitude. □For this reason, the non-implemented example group l""rL circuit □ can operate at high speed. 10(a)' and ``('''b) are the ninth embodiment according to the present invention □. Both figures (a)' and '(bjゝ) are examples of □ length 1 using an insulating layer 17'& □ for isolation of transistors. This is an example in which the IIL circuit of the example is separated by an insulating layer 17'. □Thus, this is an example of separation. Figures (a) and (b) show examples in which the transistor is completely surrounded by an insulating layer, as shown in Figures 1 to 9. 1.' The junction capacitance is much smaller than that of the IL circuit.For this reason, the IL circuit of this embodiment has a delay time, which is the performance index of the logic circuit.・The power product is extremely small, and operation is possible with extremely low power consumption. 1. The main points of the present invention and its embodiments are as follows.
,5. ,stomach. 1. Part of the conductive layer 1 is punched in the middle! I-marginal layer 2
Formed through, suspended: 2nd, ■ Conductive, shape saving, semi-conductive layer, 3° in the above r! ＼Distribution such that impurity decreases upward from the marginal layer side, or uniform impurity, substance concentration, degree. After forming at least one semiconductor region 4 of the second conductivity type 1, remove the semiconductor region 5 of the first conductivity type of Takano Maro from the part mentioned above with the conductive layer 1. The form h2 shi is taken as ohmic contact 1~. 6. Insulation, edges, and layers on the upper surface in the fourth semiconductor value range. Open the window. A semiconductor of the first conductivity type, a region @7. It/J>At least 11? The semiconductor region 4 is formed close to, but not in contact with, the semiconductor region 4 . Forming a semiconductor region 8 of a second conductivity type; 1. Use this area as an injector, and use Omitsu and Kukon Takuna from the upper part of the semiconductor area 4! As a power terminal 1. Ohmic contour from semiconductor region 7, Ri1. Alternatively, the conductive layer 1 is used as a medium terminal to form an output p-terminal through a short circuit, a contact, and a contact. , the semiconductor integrated circuit device is characterized by taking it out and applying an arbitrary potential to the terminal 1.
,, ・ □2. The above semiconductor, the semiconductor region 4. in the integrated circuit device. , ,<p,
! Next, a semiconductor region 9 of the first conductivity type with low impurity content is formed from the upper surface 1, and this semiconductor region 9. A semiconductor region 10 of the second conductivity type is formed in the semiconductor region 10 of the second conductivity type. Semiconductor region 8 as described in I.1. A semiconductor integrated circuit 11) characterized in that the ohmic contact is used as an injector, and an arbitrary potential is applied to the ohmic contact from the semiconductor region 9.
1 Circuit device・□, 3. In order to separate each transistor in the semiconductor integrated circuit device 6 described in item 1 above, the upper and lower insulating layers 2,
6, a deep semiconductor region 1 with high impurity concentration
Semiconductor integrated circuit device 3゜4.1. Semiconductor integrated circuit device 5゜5.4-A conductor characterized in that in the semiconductor integrated circuit device described in Item 111, the semiconductor region 8 is used as a 1st layer and 2nd layer to separate each transistor from 1 to 1. A semiconductor integrated circuit device according to claim 1, characterized in that an insulating layer 12 is formed in contact with upper and lower insulating layers 2 and 6 in order to separate the semiconductor integrated circuit device. . 6. In the above-mentioned ``1'' conductor-mounted circuit device, a semiconductor characterized in that a CIM is formed by a process that reaches the insulating layer 2 of the conductor in order to separate the C1-transistor. Integrated circuit REj. [Effects of the invention] As explained in 7 below, according to the present invention, it is possible to reverse the movement of the I r L circuit, and furthermore, the junction capacitance does not decrease. Delay, which is a figure of merit for logic circuits11)
There are many things that can be done, such as reducing the time and power product. In addition, in the embodiments of the present invention, for convenience of explanation 1'1', 11
The conductivity of the body is designated as P type and N type, and the
'1st person is also specified as P N P, Sai I'', N, -
It goes without saying that the present invention is also applicable to the case where all the poles and 11 of (1) are reversed.

[Brief explanation of the drawing]

11th λ1 and 3rd λ1 to 11th λ] J: 'C is a diagram showing an embodiment of a semiconductor integrated circuit device according to the present invention,
Figure 2 is based on the present invention, which uses Figure 1 as a tree.
7 bodies! , 1. 1 for explaining the manufacturing method of integrated circuit device stone
5, in each 131, 1 is a conductive layer, 2 is F
Men no Zetsu, i) ゛, ノ'l'l', go3 is N-shaped! 14 desks・
I/T layer, 4 is [ ) shape) 1', i, 'i conductor layer! 511
j\J type ゛l'' center body N;, [3 is an insulating layer on the −L plane, 71
N-type 7゛1');;I'! 'layer, 8 is 11 + 21
': j, i body layer, ε〕+i N form゛1', do:・body A
'4i, lsu (JN type '1': conductor layer, 1113: N
Shape 1', the contact part formed by the conductor layer and metal end 1', 12 is the N-type body layer, and 13 is the G) shape'!
I4 conductor layer, No. 1/1; i: 1. 'Form 1' tax body jH
'4. i, 15 is N type "1'-conductor layer," 6 is N type "1"
~Cj body layer, I7 is an insulating layer, 101 is an injected end r
-5102 is 1-) 'N p t-Lancisstar's ＼
-S end 1', 10: □3 (MaN PNl-Ran Sista's only lodging 1.
+The emitter end J-1106 of the helangistor is a separated layer;
゛1. Stomach-1107 is N I)
108 is the emitter end γ of the NPNI resistor (or the emitter end γ) of the transistor, and 108 is the emitter end γ of the NPNI resistor.・ '11 (c) 1 Fig. 3 Fig. 1 θ5 (b) ' Fig. 4 Fig. 5 Fig. Otsu 1 (b)/θ5 Fig. 7 Fig. 8/θ5 Fig. 9 Fig. 1 O shi 1

Claims (1)

[Scope of Claims] I HI''i9. an insulating layer having a 1-j portion 4 and an insulating layer 1-j' open from the step to the surface of the semiconductor substrate-1-; The board is equipped with a half-74 body layer and a vertical bipolar transistor which can also move in the opposite force direction and which is provided on the center body layer. In the device 6, the impurity of the semiconductor layer is high in concentration in the part near the 11th layer or the 1st layer, i'fl.
According to L-9, impurity 7 which causes low concentration [σ molecule 1]
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