JPS59168531A - Information memory - Google Patents

Abstract

PURPOSE:To attain various combinations of a host and an output device with an information memory by executing the reset definition processing and the line feed definition processing set by an instruction decoding means and setting an operation mode indicated by a parameter. CONSTITUTION:An information memory 100 receives the information from a host 200 and writes the bit information of a page memory of the memory 100 and gives this bit information to a plotter 300. The host 200 can define the plotter reset (CR) and the plotter line feed (LF) of a function character code with a command. If no definition is given from the host 200, the definition set by the state of a designation switch which decides these definitions.

Description

[Detailed description of the invention] ■Technical field The present invention relates to a computer and a word processor.

Input Board 2 Creates page data of bit information distribution in response to instructions from an information processing device (hereinafter simply referred to as host) such as a plotter, and serves as a plotter.

The present invention relates to an information storage device that outputs to an output device such as a CRT display, and particularly relates to an information processing device that also performs data processing, such as the so-called Intelligent Intern Ace.

■Prior Art Conventionally, the host itself creates bit information and supplies it to the output device, or the output device is equipped with a character generator or the like and a buffer memory, and the output device creates the bit information. Display etc.

Therefore, the processing standards for the host 1 to itself and the processing standards for the output device are strictly determined, and the combinations of host and output device that can be connected to each other are extremely limited, causing various inconveniences. . For example, even if the user wants to change the operating mode, it is impossible because the commands between the host and the output device are limited and fixed, and the degree of freedom of operation for the user is low. Therefore, it is desired that an information storage device, ie, an Intelligent 1 interface, be created that connects the host or output device and changes or expands many processing modes and functions without changing the functions of the host or output device. .

■Purpose The first object of the present invention is to provide an information storage device that enables various host-output device combinations and processing modes without particularly changing the functions of the host and output device. - The second purpose is to provide an information storage device that improves the operability of the combination of output devices, and allows text (text mode), halftone images (halftone The third purpose is to provide an information storage device that creates bit information by selectively or as needed superimposing bit images (bit image modes 1 to 1) and bit images (bit image modes 1 to 1). A fourth object of the present invention is to provide an information storage device in which write area processing for tone images and focus images is relatively simple and consistent.

■Configuration The present invention will be described below based on embodiments shown in the drawings.

FIG. 1 shows a schematic configuration of one embodiment of the present invention.

In FIG. 1, 100 is an information storage device which is an embodiment of the present invention, and receives information from a host 1-200.
Bit information is written into the page memory of the device 100, and the bit information of the page memory is provided to the plotter 300.

The host 200 includes a word processor, a plotting and tabulating device,
Character data and coordinate data from computers, scanners, keyboards, data storage devices, etc.

It inputs, processes, and stores image information such as bit information and density gradation data.

Plotter 300 is a recording device capable of dot recording. In addition to the plotter, the output device may be a CRT display, or may be an information processing device such as a computer, word processor, or data storage device.

The information storage device 100 mainly includes a microprocessor (hereinafter abbreviated as CPU) board 10 and a page memory 2.
0. Pattern memory 30. Interface board 40
and a common bus 50. In initialization immediately after power-on, the control program of the ROM 11 is written into the work memory RAM 1.2.

FIG. 2 shows the configuration of electrical elements of the CPU board 10.

The CPU board 10 is a ROM that stores a control program.
II. RAM12. as working memory. Microprocessor (CPU) 13° Clock pulse generator 14.
Control signal decoding circuit 15. Address latch circuit 16.
Data Noves Driver 17. Data buffer 18. Parity check circuit 19. Address multiplexer 11a
, memory refresh control circuit 12a, bus timing pulse generator 13a, address bus buffer 14a, data bus buffer 15a, read/write control 1
It includes a 6a9 interrupt control circuit 17a, a timer 18a, and a common bus 50.

FIG. 3 shows the configuration of the page memory 20. The page memory 20 consists of 144 64 KB D-RAMs.
Memory unit 21 as a 024 K Byte memory array. Address multiplexer 22. Input/output buffer 23. It is composed of a refresh control circuit 24 and a unit selection circuit 25.

FIG. 4 shows the configuration of the pattern memory 30. The pattern memory 30 stores character patterns (1 character group 48 lines = 48
A memory array 31 is provided for storing bit information of a dot, 38 yt horizontally, e=24 dots) and bit information of a density gradation pattern (one pattern is 8×8 dots). The character pattern includes Japanese characters, alphabets, numbers, and other required characters and symbols, and the density gradation pattern consists of 4 groups with different tones such as contrast and shading, and each group has 64 patterns (64 gradations). Contains 4x64 patterns. The pattern memory 30 is a memory array 3
1, write pattern information in the memory array 31,
For reading pattern information from the memory array 31,
Memory address selector 32. Memory bank selector 3
3. A timing pulse generator 34 and a buffer 35 are provided.

J2 indicates a connection terminal portion.

FIG. 5 shows the configuration of the interface port 40. The interface port 40 is a Centronics interface 41 that is an interface with the host 200.
．． A plotter interface 42 is an interface with the plotter 300, and a serial interface 44 is a serial interface for exchanging data with other external devices.
゜DMA (Direct Memory Acc
ess) controller 43, bus interface 45
It consists of a nine-person output buffer memory 46, an R5232C (parallel interface) 47, and an R542248.

Sen 1 heroin interface 41 is a parallel interface and accepts data from hosts 1 to 200. Plotter interface 42 is an output interface and outputs page data to a plotter. The serial interface 44 is a bidirectional interface, and is used for sending data and receiving numbers. The buffer memory 46 can be used for wavelengths as part of work memory and bit memory (page memory).

Next, the functions of each element will be explained in more detail.

Memories 1 to 21 The memory unit 21 is divided into four subpages based on address classification, and each subpage is further divided into four banks. This situation is shown in FIG.

The numerical representation of the address in FIG. 6 is a hexadecimal notation (usually represented by 11).

When performing DMA transfer, since the DMA controller 43 has the CPU No.
Transfer data is stored in the I10 area corresponding to CPU13.
It inputs AGENo and controls the DMA controller 1-roller 43.

When erasing the memory of the memory unit 21, PAGE
NO is optional, and WRITE L, 64 of 8000H-8FFFFH, MSB bit ON data in I10 area.
Write data to KByte. All memories can be written simultaneously in 64-byte units. When data ("0" for erasure) is written, the same data is simultaneously written in units of 64 bytes in the direction of the arrow in FIG. Therefore, memory erasing time is extremely short.

Interface Port 40 The plotter interface 42 is synchronized with the clock from the plotter 300 and transfers data in the memory unit 30 according to the operation of the DMA controller 43.

The DMA controller 43 performs block transfer in units of 300 bytes, and returns the common bus 50 to the CPU 13 every time a 300 byte transfer is completed. Command 2 to plotter 300 Status from the plotter is read by CPIJ 13.

The sensor 1-ronics interface 41 is the CPU 13
Alternatively, it controls data transfer between the DMA controller 1-roller 43 and the host 200. When the CPU 13 directly reads data, an interrupt is generated by a strobe signal from the hosts 1 to 200, and an acknowledge signal is generated by reading the data from the CPIJ 13. In data transfer by the DMA controller 43, a DMA request is issued to the DMA controller 43 every time a strobe signal is received. Generates an acknowledge signal when data is stored in memory.

The serial interface 44 controls serial transmission and reception of data by the DMA controller 43 or the CPU 13. When using the DMA controller 43, the serial interface 44 outputs the DMA controller when the transmit buffer becomes empty or when data is input to the receive buffer.
Request MA. When the CPU 3 directly handles transmitted and received data, an interrupt is generated and a service request is made to the CPU 13.

The buffer memory 46 has addresses FCOOO to FDF.
It is an FF memory and can be accessed by the CPU 13 and the DMA controller 43. By turning off the dip switch, memory 46 is disabled.

Next, to explain the setting procedure of the DMA controller 43, first, specify the command register, specify the bank number, specify the DMA transfer address, specify the number of DMA transfer yte, specify the mode register, and set the mask register. Reset. This starts DMA. D.M.A.
When finished, set the mask register.

The plotter interface 42 reads the status of the plotter 300, sets the DMA controller 43 if it is a recording cylinder, and specifies and sets a command. When a command is specified, data transfer by interruption is started, and when data transfer for all lines has been completed a number of times equivalent to the set number of sheets, the DMA mask register is set.

During DMA transfer, the Centronics interface 41 sets the DMA controller I-roller 43 to Sera 1, then transfers data using an interrupt, and upon completion, sets the DMA mask register to Sera 1.

During DMA transfer, the serial interface 44
1) Set the MA controller 1-roller 43, set the serial mode, and set the serial command. 29 starts data transfer by interrupt. When the data transfer is completed, the DMA mask register is set.

The page memory hit map, data transfer, command format, etc. are as follows.

(1) Basic form a, page memory bit size! 3296 bits (line) x 2400 bytes horizontally h412bytes
X 300 ByteB/Bitmap writing method Full horizontal sequential scanning (by external clock synchronization) C. Bitmap reading method Full horizontal sequential scanning (by external clock synchronization) d. Data transfer mode (receiving) B) Text mode ) Halftone mode C) Bit image mode e, 4 types (4 groups) of halftone expression, each group has 64 density gradations, one density pattern is 8 x 8 top 1 - square ma I helix f, print area corresponding to bitmap Height: 279 mm x Width: 203 mm (2) Page memory pin 1-map a, horizontally divided into 4 (divided into 4 subpages) 1 subpage: 824 lines (bits) x 2400 bits. Each subpage consists of 4 banks.

b. Addressing method Start position specified relative address (start position is absolute address)
. The coordinate origin is at the top left.

Start a) and response are each motoy) 2 mouths), c) Commonly X (
Horizontal: Horizontal) direction in Byte (8 Byte) units.

The y (vertical: vertical) direction is also Byte (8Bite: 8
1ine) unit.

b, Address unit horizontal direction 11 yte unit (from left to right) vertical direction 1
inine unit (from top to bottom) C0 end address specification The end address is a relative address with respect to the start position, and corresponds to the count number of data.

B) Text 1-mode is unspecified. It is determined by the character size, character pitch, LF amount (line feed amount), and number of lines.

In halftone mode (mouth), the horizontal direction is the number of blocks (iByte
unit), and the number of sections in the vertical direction (81ine: IByte
).

c) In the P1-Image mode, the horizontal Byte
The unit is 1ine (bit) in the vertical direction.

d. Range that can be written in the valid data bit map memory (3296 dots vertically x 2400 dots horizontally). Data (pips I-) that exceed this range (writable area) are invalid.

b) In the case of text mode, the range does not exceed the maximum number of existing addresses.

(3) Data transfer a, character data (character code data) alphabets, numbers, and kana conform to JIS C-6220. Based on 8 unit code. For Kanji mode, JIS C-6226
Compliant.

b, Halftone density data I Byte/section; Binary (0-63) section=
Pattern - 8 x 8 bits There are 32 types of functional character codes from 0 to 31, exclusive of Bynary codes 0 to 31, and 3
Alphabets, numbers, and symbols are assigned to 2 to 120, so to prevent confusion with these, density gradations 0 to 120 are assigned.
The data specifying 63 is a value obtained by adding ]28 to the value indicating the real value, and when decoding it, 128 is subtracted from the content of the gradation data to obtain the actual gradation indication value.

C, bit image data 1 bit/pel; Byte unit MSB...
leftmost pixel) LSB...R (rightmost pixel) d,
Numerical data Binary; Byte unit e unit - data transfer order MSD to LSDΔ (from L to R: transfer the right Byte sequentially from the leftmost IByte).

f, control code JIS C-6220, an extended control code using a function character code based on 8-unit code and an ESC code.

Commands using ESC codes are completed with SP. S
P = 5 paces.

Note that the above functional character codes are 32 types from 0 to 31, and 0 to 31 of the binary codes are exclusive, and letters, numbers, and symbols are assigned to 32 to 120, so please avoid confusion with these. To prevent this, the data specifying density gradations 0 to 63 should be changed to 128 to the value indicating the real value.
When decoding it, 128 is subtracted from the content of the gradation data to obtain the actual gradation indication value.

(4) Control command The contents of the control command are as follows.

a, Command format % expression % b, Area specification command format ESC + (alphabetic character) xI X2 Y1y2 +CI C
2G304 +5PXIX2: Horizontal start address (absolute address) y1y2: Vertical start address (absolute address) C1G2: Horizontal end address (relative address) C3C
4: Vertical end address (relative address) Relative address is a count value from the start address. Each address data is 2 bytes. Alphabetic characters indicate mode specification or command type.

C, Defold The mode is text mode, and the start address is the coordinate origin.

d.Mode specification Text mode ESC+A+xz This always requires a mode specification, so in text mode there is no end address specification number.

Halftone mode ESC+G+n+SP n=O~4; n=o ends halftone mode, n
= 1 to 4 designate each of the four groups of gradation types.

Pi~Image mode ESC+B+xIX2 yIV2 +CI C2C3c
a +SPe, writing format % expression % n=o or 1; n=o is memory clear & insertion.

n = 1 is overwriting (OR of memory data and transfer data)
). The data is "1" when it is recorded and "0" when it is not recorded. n
=2 is the 2-inclusive exclusive OR (exe, OR).

f, Entire page memory erase ESC+E 10SP g, Partial page memory erase ESC+D+x1 x2 yl yz +c1 C2C
The 3C4+sp address is in 81ine units.

h0 Character size specification ESC 10S + n 10SP n = 0 to 5; n = 0 is equal size (reset), n = 1 is #t1x and height 172x, n = 2 is 1x width and 2x height , n=
3 is 2 times the width and 1 time the height, n24 is 2 times the width and 1/2 time the height, n
-5 indicates double width and double height.

n=o instructs to reset the font size, and when reset (default), the characters are set to the same size.

i0 character space ESC+H10n10SP n = 0 to 32, and the space is indicated in units of 1 to 32.

j1 line spacing ESC 10V 10n +SP n is 8], a number with ins as one unit. Default is n
=0°k, print and memory clear ESC+P+n+5P n=0 to 99 represents the number of printouts (number of page memory transfers). If n = 0, it is considered that the number of mouths = 1.

(2) Print & Non-Clear ESC+N +n+5P n=0 to 99 represents the number of print errors 1- (number of page memory transfers). If n=o, it is assumed that n=1.

m, definition of carriage return (CR) ESC + R 10n 15P n=o is only CR, n=1 is only line feed LF without CR,
n = 2 is both CR and line feed LF.

Definition of n, line feed (LP) ESC + F + n 10SP n = 0 is LF only, n = 1 is CR only, n = 2 is C
Both R and LF.

Note that there are dip switches for setting the definitions of CR and LF, and when the above definitions of m, , n are not commanded, the definitions set with the dip switches are followed.

0, return CR P, line feed LF With the above configuration and the control program stored in the ROMII, the information storage device 100 has the following characteristics in general.

(1) The memory unit 21 has a memory (page memory) that is equal to or more than the number of pixels (dot number = bit number) for processing one page of the plotter 300, and (a) converts character codes from the host 200 into character pattern data (bit (pattern: pixels) and written to the area specified by the host 200 of the memory unit 21;
Converting the data into a halftone pseudo halftone pattern (reading the bit information of the halftone pattern corresponding to the halftone data) and writing it into the area specified by the host 200 of the memory unit 21; c) From the host 200 A page memory is created using bits (pixels) in three modes: bit data (pixels) are written directly as bit images into an area designated by the host 200 in the memory unit 21. It is possible to switch between three modes within one page.

(2) Writing to the memory unit 21 is performed by setting the write start position of each mode in units of pixels to the power of 2 (n- in the embodiment).
3). Preferably n=5.

(3) In the above (2), in the p1-image mode (c), the end position designation that defines the end of the specified area is specified by a relative value from the start position in the same address unit as the start position.

(4) In (2) above, if there is no particular designation from the host I~200, the writing start position is immediately after the device 100 is started (when data is received after the power is turned on), the write start position is P1~200. The information is written from the coordinate origin of the memory unit 21, and in other cases, the start position specified immediately before is the return position, and when the previous end mode is the bit image of c), from the return line feed position, and ) character pattern or a halftone pattern (mouth), the specified address is the address following the address that ended immediately before.

(5) The host 200 can specify the number of times one page of memory data from the memory unit 21 is output, and the host 200 can also specify whether to retain or erase the data in memory data 1-21 after outputting the data that number of times. It is possible.

(6) Logical operations instructed by the host 200 can be performed on the data from the 7fX store 200 and memory data in the memory unit 21, and the operation results are updated in the memory area specified by the host 200. Logical operations include logical sum (OR), exclusive logical sum (Exc, OR), priority writing of host data, and inversion writing of host 1 to data 2.
(7) Memory data in the memory unit 21 is transferred to the plotter 300 in synchronization with the speed of the plotter 300.

(8) It has a standard command table that interprets commands from the host h-200 to the device 100, accepts loads from the host 200, rewrites the command table, uses this for command interpretation, and interprets commands from the host h200. It is now possible to change the command table.

(9) In (8) above, the command format is composed of a functional character code, a character code, and a parameter (numeric code), and the number of each used is variable length (not limited).

(10) In (8) and (9) above, the command table is a variable-length matrix, and the lengths of its rows and columns are variable (not limited).

(11) In (8) to (10) above, each command is assigned to each column, and each column includes a line for the number of characters used in the command, a line indicating the end of the character code, and a line for the parameter size. This is the number of lines corresponding to the line indicating the command line and the line indicating the processing routine. Set Tari's ite (function character code string) to "0"
”.

(12) Same-size memory, reduced memo IJ, and enlarged memory for character patterns are possible, and in these modes character patterns (turn data (bits) can be stored in memory according to the character size specified by the host 200. -20: Memory.

(13) Above (12) ↓, the vertical size and horizontal size can be selected separately, and the character (turn data (bit) is stored in the memory unit 21.

(14) The dot matrix structure (bit data force) of the original character pattern is an integral multiple (1 or more) of the address unit when specifying the writing position, and the space between characters is
An integer multiple (including 0) of the address unit and host 2
It can be specified starting from 00.

(15) In (14) above, the dot matrix structure of the character turn is an integral multiple of twice the address unit in the vertical direction, and the space between character lines is an integral multiple of the address unit (
(including 0) and can be arbitrarily specified by the host 200.

(16) There are four types (four groups) of halftone patterns, and each group has 64 pieces (64 gradations). At the beginning of (1) above, the area specified by the host 200 in the memory unit 21 is specified by the gradation data (density data) from the host 200 from among the halftone pattern groups specified by the hosts 1 to 200. Identify the halftone pattern to be used and write that pattern.

(17) In (16) above, when the host 200 notifies (declares) an intermediate tone prior to the transfer of the tone data, the tone data has at least IBij attribute data (gradation data) in a predetermined position. data indicating that
Interpret Byte as gradation data.

(18) In the above (17), the IByte gradation data includes multiple bits of attribute data (data indicating the group) specifying the gradation group.

(19) In (16) above, the host 200 writes the gradation storage write area (closed area: start end address and end address)
Transfer the specified data. When specifying a writing area in this way, the host 200 also transfers attribute data specifying a tone group.

(20) The host 200 can define the functional character codes CR (plotter return) and LF (plotter line feed) using commands.

(21) When there is no definition of CR and LF from the post 200 (default), the definitions according to the state of the designated switch that defines these definitions are followed.

(22) Provided for the DMA controller 43,
Image data (pixels) are transferred from the memory unit 21 to the plotter 300 by a DMA controller 43, and are transferred to an 8-bit buffer, converted into serial data synchronized with the recording operation of the plotter 300, and output to the plotter 300. .

(23) DMAI controller 43 is host 1-200
(7) Data input/output port can also be applied, and data transfer with the host 200 is performed by a CPU mote that takes data into the accumulator of the CPL 113 and then sends it out, and a DMA
Transfer is possible in DMA mode in which the controller 43 transfers.

Table 1 below shows the contents of the standard command table.

A comparison between each of column 1=16 in Table 1 and the contents of the command is shown in Table 2 below.

Specifies that the data is inverted and stored in the update memory. The command is ESC+I+n+SP, where n
=o is a positive image (no memory inversion) instruction, and n=1 is an instruction for inversion (negative image) rewriting.

*** Rewriting the command table instructs to add and change the contents of the table shown in Table 1.

The command is ESC+X+z1z;2 Z324 Z5
Z6 +SP, Zl is data indicating a numerical value specifying column M, and 22 to Z6 are information data to be written in rows N=1 to 4, respectively.

Next, the operation of the CPU 13 based on the control program stored in the ROMII will be explained.

First, reference is made to FIG. 7 which shows an overview. When the power is turned on, the CPU 13 initializes, declares variables, defines subroutines, and proceeds to the main program. In variable declaration, define all variables used in the control program. In subroutine definitions, subroutines that are called from the main program and other subroutines are defined. Each processing part that makes up the program is made into subroutines as much as possible, and data processing is executed by calling these subroutines. The main subroutines are (a) to (ma) shown in FIG. Subroutines include elemental subroutines that perform only one process, and compound subroutines that call these subroutines and perform a set of processes.

The main program calls elemental subroutines or compound subroutines into a process class and repeats them so that a series of data processing is performed.

In the initial setting of the main program, a subroutine (force) is called to set a read/write area (coordinate origin immediately after power is turned on) in the write area setting table. Next, subroutine (d) is called to write standard commands as shown in Table 1 into the command table.

Furthermore, subroutine (a) is called to set initial values (defaults). Then, subroutine (a) is called to erase the entire page memory (31). and the command (
command).

When a command arrives, data processing begins. In data processing, first a subroutine (nu) is called to interpret an instruction (command), and then a subroutine (to) is called to process and set parameters in the command. Next, a subroutine (N) is called to select the processing operation specified by the command. When a processing operation is selected, processing such as memory reading and writing is performed according to a subroutine that executes the processing operation.

When the processing is completed, the process returns to the command waiting state before data processing.

Next, each of the subroutines will be explained with reference to FIGS. 8 to 39.

(a) Initial settings (Figure 8) Start address input register SAX (x coordinate) and S
Clear A'l (y coordinate), clear start address storage registers XADR (x coordinate) and YADR (y coordinate), and clear virtual bitmap space coordinate registers X, Y. Next, character pattern and halftone pattern 1
Set the horizontal (x) of the area (section) to 3 bytes (24 dots),
Set the vertical to 6 bytes (48 dots 1 - = 48 lines),
Set the character spacing to 1 byte (8 dots) and the line spacing to 0, and convert the lowercase English letter code to the uppercase letter code (since the command consists of uppercase letters,
The flag S, which indicates that this conversion is performed for reading purposes even if the input is in lowercase letters, is set to OFF (no conversion), and the pattern table (character character memory &
density gradation pattern memory) can be referenced in text mode (
character specification) and return operation CR to n=
Set only the return CR equivalent to o, and change the action LF to n =
Set only the line feed LF equivalent to 0, and set the font size to n=0
Set the number of copies to the same size, set the number of copies without overwriting (OR writing), and set the number of pages to be printed (the number of times page memory data is transferred to the printer 300) to 1 (below). ” nib fault setting). The write area is set to be outside the actual write area (that is, no writing is performed).

(a) Erasing the entire memory (Figure 9) Set all area simultaneous writing, write 0 (non-recorded data) to the write area start address (byte unit), and sequentially transfer it to the next address.

After performing this transfer 65,535 times (the number of bytes for one bank), erasing of the entire memory is completed. That is, data in all 16 banks are erased simultaneously.

(1) DMA output (Figure 10) When the plotter 300 is ready, clears the subpage counter (register), sets the read line to 1, resets the hardware between the device 100 and the printer 300, Set read bank to 7, set DMA enable and specify DMA operating mode for ports and interfaces, set address to 0, set transfer byte counter to 304, disable interrupts and set subpage to 0. After setting, DMA transfer to the plotter 300 is started. When the content of the transferred byte counter reaches 0, the address is set to 0 again.
and set 304 in the transfer byte counter again.
Start M/.

Thereafter, each time the number of transferred bytes reaches 304 (each time the contents of the transferred byte counter becomes 0), the read line is moved to the next line, and when reading of one bank is completed, reading of the next bank is started. When reading of a page is finished, reading proceeds to the next subpage.

When the number of read lines reaches 3296, DMA is prohibited,
Enable interrupts and end this subroutine.

(1) Print (Figure 11) When the plotter 300 is ready, the above-mentioned (1) DMA
Execute the output, and when it is finished, subtract 1 from the print setting number and if the remaining value is 0, if print 1 ~ memory erase is set, (a) Execute the entire memory erase subroutine, (a) Execute the initial setting subroutine and then return to the main routine. If the memory erase after printing is not set, proceed to (a) the initial value setting subroutine without executing the entire memory erase. This print 1 subroutine can be repeated until the remaining number of prints becomes 0.

(E) Writing area/address setting (Figure 12) If the current writing line is 3296 (this does not exist in the effective address), writing for the entire page has been completed, so the corresponding The value obtained by subtracting 3296 from the number of written lines (0)
Change the writing line to (this returns you to the beginning of writing). If the write line is 3295 or less, continuous writing is possible, so check whether it is necessary to switch banks and subpages, and if necessary, switch banks or subpages. When switching is not necessary, the number of 304 bytes for one line is added to the write absolute address to advance the write position to the next line. Then, the contents of the write line counter (register) are incremented by 1 and this subflow is ended.

(Power) Writing area setting table (bank and subpage settings) (Fig. 13) The number of lines (contents of the line counter) is taken as an argument.

There is a table storing bank numbers and subpage numbers assigned to line numbers, and by referring to this table, the bank number and subpage number are determined, and the bank and subpage to be assigned as the write area are set. FIG. 13 shows the bank and subpage allocation obtained by referring to the table.

(G) Half-width characters (standard) (Figure 14) Character pattern memory (character memory) is 3 bytes horizontally and 48 lines vertically, and all these bits are 24 x 4.
It is stored in the character memory in the form of 8's arranged in a row. This data is the same as the one half-width character B...Nofa.
Stored in a sequence of columns.

The line number counter C is first cleared, the next absolute address YY is calculated, and the value obtained by subtracting 304 ( ) bytes (304 is the number of bytes for one line) from the absolute address YY is set as the absolute address. This subtraction is an element subroutine of this subroutine, in which 304 is added to the absolute address to advance the write area by one line in the third step of (e) write area/address setting, so this is to be corrected accordingly. It is. Subtraction in 304 in other subroutines described below has the same meaning.

When the absolute address VY is set as described above, the process proceeds to (e) write area/address setting, and after exiting therefrom, the half-width character buffer data is memorized in the set bank.

In this memory operation, 3 bytes (24 dots 1-) of the first horizontal column (0th line) of the character pattern are stored in the half-width character buffer as 3 bytes (24 dots 1-) of the first block.
The 3 bytes in the 2nd column (1st line) are the 3 bytes in the 2nd block, and finally the 3 bytes in the 48th column (47th line) are in the 48th block. Therefore, every 3 consecutive bytes are stored in the set bank from the position (0, 3, 6, 9...) where the number of write lines C is multiplied by 3. In other words, the pattern of one column array The data bits are converted into 3 horizontal bytes x 48 vertical lines and written into the page memory.

(ri) Half-width half-length characters (Figure 15) In this case, from the character buffer that stores pattern data of 3 horizontal bytes x 48 lines in one column, write the number of lines C multiplied by 6 (0, 6, 12, 18,...)
Read every 3 bytes from then on and store it in memory in the set bank. That is, the data of even numbered lines of characters is discarded, and the data is converted into 3 horizontal bytes x 24 vertical lines and written into the page memory.

(k) Half-width double-length characters (Fig. 16) In this case, a repeat writing counter CC is used. Set by reading every 3 bytes after the position (0, 3, 6, 9,...) where the number of writing lines C is multiplied by 3 from a character buffer that stores pattern data of 3 horizontal bytes x 48 lines in one column. Then, the write line is changed and the same 3 bytes are written to the next line. That is, when the first write is completed, the counter CC is incremented by 1, the same 3 bytes are written to the write line again, the counter CC is further incremented, and the count value becomes 2, and then the counter CC is cleared. be done.

That is, the data written twice over two lines of data for each line of characters is converted into 3 bytes horizontally x 96 lines vertically and written into the page memory.

(J) Full-width characters (Figure 17) In this case, each bit of each character line is written twice in succession in a double-width character buffer that stores pattern data of 3 horizontal bytes x 48 lines in one row, and the double-width characters are A string of bit information in which two consecutive bits of the same bit information are stored is stored in the buffer. Therefore, the full-width character buffer has twice the number of bits of one character pattern. From the full-width character buffer, every 6 bytes are read from the position where the number of write lines C is multiplied by 6 (0, 6° 12.1g, . . . ) and stored in the set bank. That is, six consecutive bytes (information is the content of one line) are written to the page memory as one line. Therefore, one column of data is converted into 6 horizontal bytes (48 dots) x 48 vertical lines and written into the page memory.

(S) Full-width half-length characters (Figure 18) In this case, as well, each bit of each character line is stored in the full-width character buffer in the (C) full-width character preprocessing that precedes this routine in the same way as for the (C) full-width characters described above. is written twice, and a string of bit information is stored in the full-width character buffer, with the same bit information stored in two consecutive bits. However, since reading from the buffer is performed every 6 consecutive bytes starting from the 12th position of the number of lines, the data on even-numbered lines is discarded and written to the page memory, so it is stored in half-length. .

(C) Full-width double-length character (Figure 19) In this case, as well, in the (C) double-width character preprocessing that precedes this routine, each bit of each character line is stored in the double-width character buffer in the same way as for the (C) double-width character described above. is written twice, and a string of bit information in which the same bit information is stored in two consecutive bits is stored in the full-width character buffer. In addition, as in the case of half-width double-length characters in (ke), the double-write counter CC is used and the same line data (full-width) is written on two consecutive lines, so the page memory has 6 bytes horizontally. X
Character data is stored in 96 vertical lines.

(S) Halftone pattern (Fig. 20) There are four types (groups) of halftones, and each group is assigned 64 gradations, and each gradation is horizontal 1 pie 1 to (8 bits) x gg line (8 bits). (bit)=represented by an 8-byte pattern.

In FIG. 20, patterns 1 to 4 indicate types (groups) of halftones. The halftone data indicates the type of halftone and the density gradation. The data indicating the type of halftone is saved as is.

First, to explain from the beginning of the flow, 1 from the halftone data.
Subtract 28. As explained earlier, the command function character code, alphabetic characters, and symbols with numbers 0 to 120 are based on the JIS C-6220, 8-unit code standard (
ASCII code), and in this embodiment, numbers are assigned to functional character codes, alphabetic characters, and symbols according to this standard. Therefore, if the gradations from 0 to 63 were expressed directly in binary, confusion would occur in identification, so we decided to give the number obtained by adding 128 to the gradation numbers 0 to 63 as gradation data from the host 200 to the device N100. ing. Therefore, in the subflow of this halftone pattern, 128 is subtracted from the gradation data to reproduce data representing the gradations O to 63 themselves. Next, since one minimum pattern is 8 bytes, the data representing the gradation is multiplied by 8 and stored in the gradation pattern read address register F.

Next, identify a read pattern group using the saved halftone type data, read out the Fth to 8 by 1 (64 bits of 1 minimum pattern) of the group in order, and transfer them to the half-width character buffer. Start address”/ADH
(byte) is multiplied by 8 and stored in line register Y, the start address XADR is stored in X register X, the write line register C is cleared, and the absolute address is 1Y=30.
4X(Y MUD 208)+Xtil-calculate. That is, since the X and ■ addresses are consecutive in the memory, divide ■ by 208, take the remainder, multiply it by 304, and add X to obtain the absolute address YY. Next, the value obtained by subtracting 304 from YY is set as yY. Next, it is checked whether or not reverse writing is set, and if it is not set, the process proceeds to normal writing shown in FIG.
Proceed to reverse drawing of the figure.

To explain normal writing with reference to FIG. 21, first, execute the above-mentioned (e) write area/address setting to set the write area of the page memory, and then write to the set area. Each byte of the half-width character buffer is written in association with the line number. Every time one byte is written to one line, the line number counter C is incremented by one count, and when the count value reaches eight, the writing is completed. As a result, writing of 1 horizontal 1 byte of 1 minimum pattern and 1f1B line is performed.

Inversion writing will be explained with reference to FIG. 22. Inverted writing is the same procedure as the normal writing described above, except that each bit of each byte is inverted from ``1'' to ``0'' and from ``0'' to ``1'' and written to the page memory. It's different.

(C) Full-width character preprocessing For (C) Full-width characters, (S) Full-width half-length characters, and (C) Full-width double-length characters, one bit of the character pattern (character) data is horizontally transferred to the full-width character buffer. It is necessary to store two consecutive bits. This storage is performed by this full-width character preprocessing.

In this case, first clear the character read line number counter C, clear the full-width character buffer, and then read the character data (3 bytes of each line are sequentially arranged in one horizontal column; total of 3 x 48 bytes). For every 3 bytes, each bit is written as 2 consecutive bits to the full-width character buffer, and when this is finished, the counter C is incremented by 1,
Next, the next 3 bytes of character data are similarly converted to 6 bytes and stored in the full-width character register. Then, the counter C is incremented by one. The same applies below.

When the contents of counter C reach 144, all the processing of one character's character data has been completed, so when the character specification is referred to and a full-width character is specified, the subroutine for full-width characters (C) described above is executed. When specified (su)
Proceeds to the subroutine for full-width half-length characters, or (b) if full-width double-length characters are specified, then proceeds to the subroutine for full-width double-length characters.

(n) Pattern processing (Figures 24a and 24b) Patterns (fonts) include character patterns and halftone patterns. The character code follows the ASCII code of JIS C-6220, and according to this regulation, functional character codes are assigned to 0 to 31, symbols, numbers, and alphabetic characters are assigned to 32 to 120, 121 to 151 are undefined, and 152
Katakana characters are assigned to ~210, and 211 to 23
0 is undefined. Therefore, symbols, numbers, alphabetic characters, and katakana are assigned codes sequentially starting from 0. However, to prevent confusion with functional character codes, undefined codes, etc., symbols, numbers, and alphabetic characters are The code is made by adding 32, and in katakana, it is made by adding 64.

Therefore, in the case of characters, when the code is 0 to 31 (data <
20) 1), 121 to 151 (7FH<data AOH)
If 121 to 151 (DFH<data), this subroutine is terminated as an error. If the data is in the character allocation range, when data <80H (for symbols, numbers, and alphabets), 32 is subtracted from the data and it is reproduced as character data, and data>9F[(
(katakana), subtract 64 from the data and reproduce it as character data. As a result, the reproduced character data returns to character data in which numbers, symbols, alphabetic characters, and katakana are assigned in continuous codes.

Next, the character code is multiplied by 144 and the stiffness is set as the read address F of the character pattern memory (character memory). This is to specify the start address of the character data since 144 by 1- is assigned to one of the character characters. Next, character data is read from the pattern memory, the start address YADR (byte) is multiplied by 8, and stored in line register y, and the start address
ADR is stored in the X register
Move on to the next leaf.

In the case of halftone mode, its density gradation data is the sum of 128 as already explained, and 128
If ≦data≦191, the above-mentioned halftone pattern subroutine is executed, the start address is updated, and this subroutine is ended. If the data is outside the range, this subroutine is terminated and the halftone pattern subroutine is not executed.

(i) CR (return) operation setting (Fig. 25) This subroutine performs (a) initial value setting (default), (n) instruction decoding, which will be described later, or CR specification data stored in register CR by dip switch reading. Based on this, page memory read/write 71-res are updated. Since 0 in the CR designation data instructs execution of only CR, in that case, the X-axis start address is set to the first start address. Since 1 in the CR designation data instructs execution of only LF, in that case, the Y-axis start address is updated to a value obtained by adding the number of lines corresponding to the character size L and interline space V to the current value. CR specification data 2 specifies both CR and LF, so in that case, set the X-axis star 1-address as the first start address, and set the Y-axis star 1-address as the character size L and line spacing V. Update the number of lines to the current value plus the value.

(H) LF (Line feed) setting (Figure 26) This subroutine performs (A) initial value setting (default), (J) command decoding (described later), or based on LF designation data stored in register LF by dip switch reading. to update the page memory read/write address. L
Since O of the F designation data instructs execution of only LF, in that case, the Y-axis start address is set to the first start address. Since 1 in the LF designation data instructs to execute only CR, in that case, the X-axis start address is updated to a value obtained by adding the number of lines corresponding to the character size L and interline space V to the current value. LF specification data 2 is CR and LF
are specified together, so in that case, set the X-axis star 1-address as the first start address, and update the Y-axis start address to the value obtained by adding the number of lines equivalent to the character size L and line spacing V to the current value. do.

(T) Centronics input (FIG. 28) When the interrupt prohibition is released, a ready (receivable) signal is output to the host 200. When data is received from the host 200, it is imported from the old Centronics interface and sent to the host 2.
Sets busy (reception not possible) to 00 and prohibits external interrupts.

(TE) Bit image processing (Figures 27a and 27b)
Figure) One unit of address and 1 in 8 vertical lines (1 byte)
/, so in order to convert this to an address in line numbers, multiply the Y-axis star 1~address by 8, set ■Koyama line address V, and change the X-axis to star 1~address as it is.
Set address. Then, the width and height J of the area specified by the received data are set as target values. Next, clear the line number counter CC and set the absolute address YY.
The value obtained by subtracting 304 from the stiffness is set as the absolute address YY. Next, the width counter C is cleared and reference is made to see whether or not inversion writing is to be performed, and (n) centronics input is executed to store the received data (bit data) in the 1 minute width pick l-buffer. When reverse writing is specified.

At this time, the data bits "1" and "0" are inverted and stored. When one line of bit data corresponding to the width is stored in pins 1 to buffer, (e) Execute the write area/address setting, check whether writing is to be performed after clearing, and if it is to be written after clearing, set. Writes bit data for one horizontal line of the bit buffer to the bank that has been read, increments the line counter CC by 1, clears the horizontal counter C, receives one horizontal line, and writes the bit data to the pin 1 buffer. Setting the write area address and writing to a predetermined bank of the page memory. The content of line number counter CC is J+1
When this happens, the writing of the vertical J line has been completed, so this subroutine is ended. If write after clear is not specified, after setting the write area address, the width (width) is transferred from the page memory setting bank to the memory buffer.
Read the pit 1-data (1 byte C), clear the bit data counter BC, and when overwriting is specified, logically OR (OR) each bit of the pit buffer and each bit of the memory buffer in the order in which they are arranged. is updated in the pit buffer, and the bit data counter is incremented by 1 for each updated memory of 1 bit. When the contents of the bit counter BC exceed the contents of the width counter C, that is, the logical sum processing for the width of one line is performed. Then, the contents of the pit buffer are written to the setting bank of the page memory, and the line number counter cc is incremented by one count. When exclusive OR is specified, perform the exclusive OR of the bit data in the page memory and the bit data in the pit buffer using the same procedure as for OR, and store it in the pit buffer. Update memory and then write to page memory.

(g) Lower case/upper case conversion (Figure 29) Refer to the command table shown in Table 1.

Commands consist of uppercase letters and numbers. Therefore,
This conversion subroutine is provided so that commands can be interpreted even in lowercase letters.

First, an uppercase English letter is 96〈data〈123, so anything outside of this is a lowercase English letter. Since lowercase English letters have a code 32 greater than uppercase English letters, the code representing the value obtained by subtracting 32 from the input code is corrected to the character code. When the conversion is completed, the flag sw is turned off indicating that the conversion is not required.

(S) Partial erasure (FIGS. 30a and 30b) Partial erasure is equivalent to storing "0" in a designated area in the same way as the above-mentioned (te) bit image processing. Since it is sufficient to store "0" in the entire designated area, partial erasure is performed by writing "0" in the leading bit of each line in the designated area and transferring this along the line.

(d) Command table writing (command table tabulation) (31st
Figure) RAM command table write area address cy=.

~50 (Clear all old data in columns in Table 1.

This is the content from the first step to the seventh step. Next, data is written in each column H and row N and the intersections of their matrices as shown in Table 1.

(J) Instruction decoding (Fig. 32) Clear the row N register Cx and the column N register c■, and receive command data at the aforementioned Centronics input. If it is a command, the beginning of the data must be H3C
Otherwise, it is data indicating 0 or a number of 32 or more. Therefore, if the data is not 0 and is not 32 or more, the lowercase/uppercase conversion flag SW is referred to, and if it is on, conversion is necessary, so the above-mentioned (g) lowercase/uppercase conversion is executed.

If it is off, the conversion has finished, so refer to the data as is and compare the contents of the input data with the data at the matrix intersection specified by the contents of the row N register CX and column N register Cy (Table 1). Then, the contents of registers CX and CY are counted up until data matching the input data is read out.

That is, first, the function character code of the input data is entered in columns 0 to 50 (row N=0 of the command table (Table 1)).
It is possible to write up to M=50, and in the example in Table 1, A=1.
6 has been written, and A = 17 to 50 are empty: "0" is written in all)) and data 1, 2, 3, etc. are compared sequentially from A = 0. and if it matches, H
is fixed, row N is sequentially increased by 1, and the data at the matrix intersection specified by N and N are compared with the data below the functional character code of the input data.

If the data of row N=3 is read and compared and is not the same, A is incremented by 1 and the same data comparison is performed.

When the data in N=O~3 of row N and the input data completely match, the value in column H at that time is the input command No., and the data in row N=4 in column N is specified by the command. Indicates a subroutine. Since the default is text mode, the function character code part of the command is "0".
'', 0 instructing pattern processing (font processing) is stored in the processing instruction register OP. In other cases, the data in row N=4 of the column that has data that matches the input command data is stored in the instruction register OP.
to memory.

(v) Processing operation selection (Fig. 33) In this subroutine, a subroutine is set according to the contents of the processing instruction register OP. The content of 0 in the processing instruction register OP indicates pattern processing (font processing) as described above.
Therefore, in this case, (n) pattern processing is set. 0P=2 performs (TE) bit image processing, 0P=
4 performs (S) partial erase, 0P-5 performs (B) entire memory erase, 0P=14 performs (1) print, 0P=1
6 also has (1) print, 0P = 27 (evening) CR operation setting, OP = 28 (ch) LF operation setting,
Further, when 0P=24, (e) instruction rewriting is set.

()) Parameter calculation (1) (Fig. 34) When there are four parameters in the command: Xi, X2, yl, y2, these indicate the start address. Xl is X
The upper 8 bytes of the address + X2 are the lower 8 bytes, and yl is the second 8 bytes of the X address.

Since y2 is the lower 8 bytes, 256Xx1 +x2
into star 1 hair address register SAX, 256Xyl
+y2 is stored in the start address register SAY.

(c) Parameter calculation (2) (Figure 35) Command parameters are Xi X2 YIY2 rCi C2C3C
4, 256Xx1 +x2 is stored in the start address register SAX, 256Xyz +y2 is stored in the start address register SAY, and 01 to c4 indicate the end position (relative address) from the start address, so 256Xcl +c2 is stored in the X address byte counter XADC, 256XC3+c4 is stored in the y address byte counter VADC, XADC is stored in the target byte register, and the value obtained by multiplying the contents of YADC (novate) by 8 and further adding 7 is added. Store in target line number register J. By the way, let's count 7 in Calo, Y.
When the ADC is 0, it indicates the area from 0 to 7 in terms of line number, so it is set to 7 at the end.

(H) Parameter setting (1) Start address (Figure 36a)
Execute the above parameter calculation () and store the calculated address in the X address register (currently the device register)
ADR and y address register; store. (b) The deviation is also data in units of by-1.

(2) Pi1~Image No. (Rameter (Figure 36b)) Perform the above-mentioned (c) parameter calculation (2) by <5. The X direction is byte units, and the X direction (line unit).

(3) Partial erasure parameter (Figure 36c) (c) mentioned above
When the parameter calculation (2) is actually performed, the X direction is in units of bytes, and the X direction is in units of bytes.

(4) LF operation parameters (Figure 36e) Register LF
The value of parameter n of one of the LF operation designation commands is stored in .

(5) Halftone mode parameter (Figure 36d) Pattern table selection register PTE stores the value of parameter n in the halftone mode command.

Tokishiko (well, the horizontal V of the font size
is 3 bytes (half-width), the height is 61 bytes (48 lines double-byte), the space between characters is 1 noheight, and 'ti' is 3 bytes (half-width).
Set ftU space V to 0 (default). N
=O, and when it is 1 (halftone instruction), the nozzle turn size profit 4ν is 1 byte, and the vertical is 1 by 1- (8 lines).
, Nope Turn 11] Set both the horizontal H and vertical V of the space to 0.

(6) Intercharacter space <-2 meter (Fig. 36f) Character space parameter register H1 stores the value of parameter n of the character interval designation command.

(7) Reversal@Write Parameter (Figure 36g) Memory Data Innobase Designation Command 1 This (reverse the value of parameter n) Write instruction register RE&'0-Write also.

(8) Number of blank sheets when holding memory after printing (
(Figure 36h) Store the value of the parameter n of the print non-clear command in the print number register CN.

(9) Memory after printing) Number of copies to be printed (Fig. 361) The value of the parameter n of the print clear command is stored in the number of copies to be printed register CN.

(10) CR operation parameters (Figure 36j) Register C
The value of the harameter n in the CR operation designation command is stored in R.

(11) Character size selection parameter (Figure 36) Store the value of parameter n of the character size specification command in the character size register S, and when the stored value (n) is 0, the width W is 3 bytes (half-width ), set the length to 6 bytes (48 lines). When it is 1, the lever is 3 bytes, and the L is 3.
When the byte is 2, the axle is 3 bytes, and the L is 12 bytes.
hen, when 3, the lever is 6 bytes, L is 6 bytes, 4
When , set the beam to 6 bytes and L to 3 bytes; when set to 5, set the beam to 3 bytes and L to 12 bytes.

(12) Line spacing parameter (Figure 361) Set the value of the parameter n of the line spacing command to the line spacing register V
Store in.

(13) Overwrite parameter (Figure 36n+) Write the value of parameter n of the write specification command to the write specification register R
Store in O.

(14) Instruction rewrite parameters (Figure 36n) Clear the row N counter C and write the column data to the 1st 0 position of the rewrite register EX, and the position 1 corresponding to row N = 0° 1.3.4. 2, 3 and 4, sequentially the command N=
0. N=1. Store data (parameters) for N=3 and N=4.

()) Parameter setting selection (Fig. 37) Similar to the above-mentioned (v) processing operation selection, the content of the processing instruction register OP is referred to in (j) instruction decoding, and the above-mentioned ((v)) is selected according to the contents of OP.
h) Execute the subroutine for parameter setting (Figures 36a to 36n).

(v) Parameter processing (Figure 38) Refer to the data stored in the processing instruction register OP in the above-mentioned (v) instruction decoding, and if it is 0, it is text mode, and if it is 27 or 28, CR (return) or LF (line feed), this routine ends. In other cases, clear the counter C, read the parameters one by one using the Centronics input, and set the counter to 1.
The count is up and the number of reads is the command row N =
The number P of the parameter 3 is the number specified in advance, and the Centronics input data indicates 32 (0 indicates the end, but the function character code is 0 to 32, so
0+32 indicates the end (0) indicates the end of the command, so ()) executes parameter setting selection and ends this subroutine.

(E) Instruction rewriting In the above-mentioned (14) instruction rewriting parameters, change data (parameters) in the command are transferred to the rewriting register EX in column, row N==0 data, N=1 data, N=3
and N=4 data, therefore, set the first 0 data of EX, that is, the column data, in the command table column address register CV, and set the row N=0.. of the specified column of the command table. N21. N
The data of EX No. 2 No. 1 to No. 4 No. 3 are written in EX=3 and N=4, respectively.

FIG. 40 shows the output timing of page memory data of the device 100. When outputting to the plotter 300,
Data WDATA is provided to the plotter 300 line by line in synchronization with the gate signal LGATE from the plotter 300.

By executing each of the above subroutines, the start address immediately after the power is turned on will be as shown in Table 3 below, and the subsequent start address will be as shown in Table 4 below. The rest is as shown in Table 5 below.

Table 4 (Immediately after turning on the power) Table 5 Processing before: Processing after text Text secondary address Halftone Secondary address Pi to 1 Image: Wait for designation. If not specified, it will remain stopped.

Previous processing: Post-halftone processing Text Secondary address Halftone Secondary address Bit Image: Waiting for specification. If not specified, it will remain stopped.

Previous processing: bit image Post processing Text l-: Position after CR or LF operation.

Halftone mode bit image: Wait for CR or LF and subsequent designation. If not specified, it will remain stopped.

Note that the address data given from the host 200 to the device 100 is in byte units, and in text mode and halftone mode, the write start address is set in ()) parameter calculation (1), and in bit image mode, (c) parameter calculation In (2), a write start address and a write end address are set. These addresses are in bytes.

As explained above, immediately after the power is turned on, the initial settings [(1) writing area setting table, (d) command table writing and (
b) Erase entire memory] and is waiting for command input. When an external interrupt occurs, (nu) executes instruction decoding,
(v) Execute parameter processing, (v) Execute processing operation selection, and execute the selected process.

Next, several types of processing operations in response to commands will be described.

(1) Rewriting the command table When a command to rewrite the command table arrives from the host 200, (n) decodes the command and sets the number of parameters 5 to parameter register P from cell 1 to processing operation register OP.
is set to 24, and then in (to) parameter processing, five parameters are transferred from the host 200 through Centronics input. Then, proceed to ()) parameter setting selection, and since 0P = 24, execute (14) instruction rewrite parameters (Figure 36n), store 5 parameters in conversion register EX, and then (n) perform processing operation. The process proceeds to selection, and since OP=24, the process proceeds to (e) instruction rewriting. In this subroutine, the contents of the column specified by the first parameter of the command table (Table 1) are rewritten. Note that if a column that has already been written to is specified, it is literally a rewrite, but if a column that has not been written to (a column in which 0 is written to row N = 1) is specified, a new command is executed. will be written.

In this way, command rewriting (and writing) is performed on the host h20.
Since this can be done with a command table rewrite command of 0, the host 200 can change the commands (standard commands) set in the control program and add new commands to the device 100. That is, it is possible to change command definitions and create new commands.

(2) A text mode processing start address specification command is sent from the host 200 to the device 10.
If given 0, this is text mode since it specifies only the starting address. In halftone mode and bit image mode, an end address is always specified.

Upon receiving the start addressing command, the device 100 (
n) Set the number of parameters to 4 in the parameter register P by decoding the instruction, set 1 to the processing operation register OP,
Next, in parameter processing, four parameters are transferred from the host h200 via Centronics input. Then, proceed to ()) parameter setting selection, and since 0P=1, proceed to (1) address parameter to star 1 (Figure 36a), ()) execute parameter calculation (1), and set the start address to the start address register. XADR and Y
ADR is set to complete the setting of the start address of the text 1-mode.

After that, when the host 200 sends the character code, (
N) Set 0P=0 when decoding the instruction, and since 0P=0, pass through the parameter processing as is, and then (N)
Select the processing operation to proceed to pattern (font) processing, convert the character code, read the character pattern data from the pattern memory (character memory), store it in the character buffer memory, and convert the character code according to the set character size. ) half-width characters, (ri) half-width half-length characters, (ke) half-width double-width characters, or (
C) Proceed to full-width character preprocessing.

When proceeding to one of the first three methods, address calculation is performed, and (e) writing area/address setting is executed, character pattern data is subjected to predetermined character size processing, and is written to the page memory. (C) When proceeding to full-width character preprocessing, the character pattern data in the character buffer memory is enlarged from 1 bit horizontally to 2 bits horizontally to create character pattern data in the double-width character buffer. )Double-byte character.

(i) Proceed to full-width half-length characters or (shi) full-width double-length characters, calculate the address there, and then (e) execute write area/address settings to apply the specified character size processing to the character pattern data. and write it to page memory.

Note that the default is text mode, so if a character code is sent from the host 200 from the beginning after the power is turned on, 0P=0 is set in (nu) instruction decoding, and OP
Since it is 20, it passes through the parameter processing as it is, and then proceeds to (v) pattern (font) processing by selecting the processing operation (v), converting the character code, and converting the character code from the pattern memory (character memory). Reads the pattern data and stores it in the character buffer memory, and prints half-width characters according to the set character size.

Proceed to (ri) half-width half-length characters, (k) half-width double-length characters, or (c) full-width characters preprocessing. The operation is the same as when receiving the character code data described above.

(3) Halftone mode Halftone mode specification command is sent from the host 200 to the device 10
When given to 0, the device 100 sets the number of parameters to 1 in the parameter register P by (nu) instruction decoding, sets 7 to the processing operation register OP, and then sets the number of parameters to 1 by (to) parameter processing. The parameters are transferred from the host 200 via Centronics input. Then, proceed to ()) parameter setting selection, and since 0P=7, proceed to (5) halftone mode parameter (36d), where depending on the value of parameter n, if N=0, this means the end of halftone. Set the writing format to the default (standard) of Cheest mode. Since N=1 to 4 designate the type of gradation, at this time, a writing format of continuous bit writing is set. Next, (v) processing operation selection is 0P=7, so it passes through as is.

After that, when the host 200 sends the halftone code,
(J) When decoding the instruction, set op=o to 1-shi, and since it is 0P-0, (J) Pass the parameter processing as is, and then (
(4) Select the processing operation to proceed to (4) pattern (font) processing, then proceed to (1) halftone pattern to write to the page memory. Since the pattern area is predetermined in the text mode and the halftone mode, the subroutines are shared in this way.

(4) Bit image mode When the bit image mode designation command arrives, the device 10 () decodes the command to set P=8, 0P=2, and then (go) sets the parameters to 8. Receive the parameters from the host 200, ()) Since 0P = 2 in parameter setting selection, proceed to (2) bit image mode parameters (Figure 36b), and (c) parameter calculation (2).
) is executed, and by selecting (v) processing operation, the process proceeds to (t) bit image processing, where the p1-data is received at the centronics input and written to the page memory.

(5) Print non-clear or print & clear When these commands arrive, the device 100 sets P=1, 0P=10 or 11 in (n) command decoding, and (v) sets parameter (n) in parameter processing. It receives the Centronics input from the host 200, then passes directly through () parameter setting selection, proceeds to (1) print 1- in (ne) processing operation selection, and executes the number of printouts indicated by parameter n there. , holds or clears the page memory depending on whether it is non-cleared or cleared.

(6) Logical operations Logical operations include (S) inversion writing in the halftone pattern subroutine in halftone mode, and inversion writing 2 overwriting (OR) in (te) bit image processing in bit image processing. ) or exclusive OR writing is selectively performed as specified in advance by the parameters of the command.

When other commands arrive, data processing [(v) command decoding - (v) parameter processing - (v) processing operation selection] is similarly executed to execute a predetermined subroutine.

In the above embodiment, only the write start address is specified with the halftone mode command, but similarly to the bit image mode command, four parameters indicating the end address are added. Similarly to the bit image mode, the end address may be set together with the start address.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an overview of the configuration of an embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of the cPU board 10 shown in FIG. 1, and FIG. 3 is a block diagram showing the configuration of the cPU board 10 shown in FIG. 1.
4 is a block diagram showing the structure of the pattern ROM shown in FIG. 1, and FIG. 5 is a block diagram showing the structure of the interface port 40 shown in FIG. 1. FIG. 6 is an explanatory diagram showing memory divisions of the page memory 2o. FIG. 7 is a flowchart showing an overview of the operation of the device 100;
Fig. 8, Fig. 9, Fig. 10, Fig. 1f. FIGS. 12, 13, 14, and 15. FIGS. 16, 17, 18, and 19. FIGS. 20, 21, 22, and 23. Figures 24a, 24b, 25, and 26. Figures 27a, 27b, 28, and 29. Figures 30a, 30b, 31, and 32. Figures 33, 34, 35, and 36a. Figures 36b, 36c, and 36c1. Figures 36e, 36f, and 36g. Figures 36h, 36i, and 36j. Figure 36, Figure 361, Figure 36m. 36n, 37, 38, and 39 are flowcharts showing the operation flow of the subroutine, respectively. FIG. 40 is a time chart showing the data transfer timing when data is transferred from the device 100 to the plotter 300. 100: Information storage device 11: ROM12:
RAM 13: CPU31: Pattern memory common log Figure 6 48'/7 Figure 11 Figure 12 Procedural amendment (voluntary) May 26, 1980 Mr. Kazuo Wakasugi, Commissioner of the Patent Office ■, Indication of the case 1981 1958 Patent Application No. 042586 2
, Title of the invention Information storage device 3, Relationship with the case of the person making the amendment Patent applicant address 1-3-6 Nakamagome, Ota-ku, Tokyo Name
(674) Ricoh Co., Ltd. Representative Hama 1
) Hiro 4, Agent 103 Telephone 03-864-60
52 Address: 2-27-6-5, Higashi-Nihonbashi, Chuo-ku, Tokyo, Subject of amendment 6. The incorrect part in line 9 of the following page of the statement of contents of the amendment is corrected to the correct content.

Claims (13)

[Claims] (1) Page memory in which one bit corresponds to each pixel of one page; Pattern memory that stores at least one of character pattern data and density gradation expression pattern data; Input/output interface; A command decoder that decodes and sets processing and parameters; A return (CR) operation mode that executes the return (CR) definition process and line feed (LF) definition process set by the command decoder and is instructed by the parameter indicating the instruction content. and line feed (LF
) return and line feed mode setting means for setting an operation mode; writing means for writing bit information into a predetermined area of a page memory; and page memory output means for outputting page memory data a predetermined number of times; . (2) The return/line feed mode setting means sets return to a predetermined return operation mode when return processing is not set, and sets line return to a predetermined return operation mode when line return processing is not set. Claim No. (1)
Information storage device described in Section 1. (3) The information storage device according to claim (2), wherein the predetermined return operation mode and changeover operation mode correspond to the open/closed states of the dip switch. (4) The predetermined return operation mode and changeover operation mode are:
The information storage device according to claim 2, wherein the information storage device is determined by data of a control program at initialization. (5) The information storage device according to claim (1), wherein the predetermined area is an area set by instruction decoding means. (6) The writing means is a text mote writing means for converting the input character code into character pattern data represented by the code and writing the pattern data into a predetermined area of the page memory; , converts the data into gradation pattern data specified by the code, and stores the pattern data in a predetermined area of the page memory. Halftone mode writing means for writing into the area; and input pitch I/
The information storage device according to claim 1, further comprising: bit image mode writing means for writing image data into a predetermined area of the page memory. (7) The information storage device according to claim (6), wherein the bit image writing means determines the end of the write area by a relative value from the start position in the same address unit as the start position. (8) The text mode writing means is the first two after turning on the power.
The starting point for the ζ-writing area is the writing start end of page memory, and after executing any write mode, the starting point of the character writing area is used, and when the previous process is in text mode, the start point is the end of the previous writing process. point, and when the previous processing is in halftone mode, it is next to the end point of the previous write processing, and when the previous processing is in bit image mode, it is the position after return or line feed processing. The information storage device described in (6). (9) The halftone mode writing means starts the first write area after power is turned on at the write start end of the page memory, and after executing any write mode, starts the halftone pattern' write area. point after the end point of the previous write operation when the previous operation is in text mode, after the end point of the previous write operation when the previous operation is in halftone mode, and after the end point of the previous write operation when the previous operation is in halftone mode. The information storage device according to claim 6, wherein the information storage device takes the position after return or line feed processing when in the mode. (10) The bit image writing means waits for a specification to determine the first writing area after power is turned on, and after executing any of the writing modes, the starting point of the bit image writing area is When the mode is 1-mode, it is determined after waiting for the designation, when the previous processing is in halftone mode, it is determined after waiting for the designation, and when the previous processing is in the bit image mode, it is determined after waiting for the designation as return or line feed processing. An information storage device according to claim (6). (11) The information storage device according to claim 1, wherein the page memory output means outputs the data of the page memory a number of times set by the instruction decoding means. (12) The information storage device according to claim 1, wherein the page memory output means clears or holds the page memory in accordance with a post-output memory processing instruction set by the instruction decoding means. (13) The page memory output means is configured so that the external output device is
The information storage device according to claim 1, wherein the data of a predetermined section of the page memory is outputted to an output device in synchronization with the applied signal. (], 4) The input/output interface is equipped with a DMA controller, and the page memory output means transfers the page memory data to the output device using the DMA controllers 1 to 1.
The information storage device according to claim 1, wherein the information is transferred to the parallel-in-serial-out buffers 1 through 1 by rollers and serially output in synchronization with the operation of the output device.