JPS59167748A - Information storage device - Google Patents

Abstract

PURPOSE:To extend many functions by connecting a hose and an output device without changing specially their functions. CONSTITUTION:An information storage device 100 receives information from a host 200 and writes bit information in a page memory of the device 100 and gives bit information in this page memory to a plotter 300. A host 200 inputs, processes, and accumulates picture information such as character data, coordinate data, bit information, density gradation data, or the like of a word processor, plotting and tabulating device, computer, scanner, keyboard, data accumulating device, etc. The plotter 300 is a recorder capable of dot recording. The plotter is provided as the output device, and the information storage device 100 consists essetially of a microprocessor board 10, page memory 20, pattern memory 30, interface board 40, and a common bus 50. In the initialization just after power-on, a control program in an ROM11 is written in a work memory RAM12.

Description

[Detailed description of the invention] ■Technical field The present invention relates to a computer and a word processor.

Input board 9 Creates page data of bit information distribution in response to instructions from an information processing device (hereinafter simply referred to as host) such as a plotter, and serves as a plotter.

The present invention relates to an information storage device for outputting to an output device such as a CRT display, and particularly relates to an information processing device, also called an intelligent interface, which also performs data processing.

■Prior art In the past, the host itself created bit information!
Alternatively, the output device may be equipped with a character generator or the like and a buffer memory, and the output device may generate bit information for printing, display, etc.

When it comes to output power, the processing standards of the host itself and the output device are strictly determined, and the combinations of host output devices that can be connected to each other are extremely limited, resulting in various inconveniences. There is. For example, even if you wanted to change the operating mode, it would be impossible, and although it is possible to concentrate text and graphs in a concentrated manner, it is not possible to concentrate images in focus. There are inconveniences such as being able to collect bit images and halftone images, but not writing text. Therefore, there is a desire for an information storage device, ie, an intelligent interface, that connects the host or output device and expands many functions without significantly changing the functions of the host or output device.

■Objective The first object of the present invention is to provide an information storage device that enables various combinations of host and output device without particularly changing the functions of the host and output device.
The second purpose is to provide an information storage device that expands the functionality of the Bost-output device combination. The third objective is to provide an information storage device that creates bit information by selectively or as needed superimposing a focused image (halftone mode) and a focused image (bit image mode). A fourth object of the present invention is to provide an information storage device in which processing of corrupted areas of tone images and bit images is relatively simple and consistent.

・Constitution The present invention will be explained below based on embodiments shown in the drawings.

FIG. 1 shows a schematic configuration of one embodiment of the present invention.

In FIG. 1, an information storage device 100 is an embodiment of the present invention, which receives information from a host 200, writes bit information to a page memory of the device 100, and writes bit information to a plotter 300 in the page memory. give information.

The hosts 1 to 200 are character data and coordinate data of word processors, plotting/tableting devices, computers, scanners, keyboards, data storage devices, etc.

Input image information such as bit information, seismic intensity gradation data, etc.
It performs processing, storage, etc.

The plotter 300 is a recording device that can perform one-drum recording.

Note that the output device can be used in addition to a plotter.

It may be a CRT display, or it may be an information processing device such as a computer, word processor, or data storage device.

The information storage device 100 mainly includes a microprocessor (hereinafter abbreviated as CPU) board 10 and a page memory 2.
0. Pattern memory 30. Interface board 40
and a common bus 50. At initialization immediately after power-on, the ROMII control program is written into the work memory RA'M12.

FIG. 2 shows the configuration of electrical elements of the CPU board 10. The CPU board 10 is an RO that stores a control program.
MII, RAM12 as work memory. Microprocessor (CPU) 13° Clock pulse generator 14.
Control signal decoding circuit 15. address launch circuit 1G,
Data bus driver 17. Data buffer 18. Parity check circuit 19. Address multiplexer 11aJ
It includes a k memory refresh control circuit 12a, a bus timing pulse generator 13a, an address bus buffer 14a, a data bus buffer 15a, a read/write 1-control 1'6a, an interrupt control circuit 17a, a timer 18a, and a common bus 50.

FIG. 3 shows the configuration of the page memory 20. The page memory 20 includes a memory array 1-2 consisting of 144 64K13it D-RAMs as a 1024K13yt, e-memory array, an address multiplexer 22. Input/output banofer23. It is composed of a refresh control circuit 24 and a UNISO 1 to selection circuit 25.

FIG. 4 shows the configuration of the pattern memory 30. The pattern memory 30 has 5 character patterns (1 character 48 vertical lines = 48
Dot, horizontal 3 Bytes == 24 dots) Bin 1~
Information and density gradation pattern (■pattern 8 x 8 dots)
A memory array 31 is provided for storing bit information.

The character pattern is Japanese characters, Alphabella 1~. Contains numbers and other required characters and symbols, and the density gradation patterns are 4 groups with different tones such as contrast 1-, 11 light, etc., and each group has 64 patterns (64 gradations).
Includes a total of 4 x 64 patterns. The pattern information 30 is
In addition to the memory array 3j, there is also a memory address selector 32 for writing pattern information into the memory array 31 and reading pattern information from the memory array 31. Memory bank selector 33. A timing pulse generator 34 and a buffer 35 are provided.

J2 indicates a connection terminal portion.

FIG. 5 shows the configuration of the interface board 210. The interface port 40 is a Centronics interface 41 that is an interface with the host 200.
．． A plotter interface 42 is an interface with the plotter 300, and a serial interface 44 is a serial interface for exchanging data with other external devices.
゜DMA (Direct Memory Acc
ess) controller 43, bus interface 45
It consists of a two-person sofa memory 46, an R5232C (parallel interface) 47, and an R54224,8.

The centro interface 41 is a parallel interface and receives data from the host 200. Plotter interface 42 is an output interface and outputs page data to a plotter. The serial interface 44 is a bidirectional interface, and allows data to be sent and received. The buffer memory 46 can be used for wavelengths as part of the work memory, p1-memory (page memory).

Next, the functions of each element will be explained in more detail.

Memory Unit 21 The memory unit 21 is divided into four subpages based on address classification, and each subpage is further divided into four banks. This situation is shown in FIG.

The numerical representation of the address in FIG. 6 is in hexadecimal notation (usually represented by H).

When performing DMA transfer, since the DMA controller 43 has the CPU No.
Transfer data P is placed in the 110 area corresponding to CPU] 3.
AGENO is controlled by IIIRITIEL, and the DMA controller 1-roller 43 is controlled.

When erasing the memory of memory unit 2J, PAGE
NO is optional, and the MSB bit ON data is set in the I10 area.
Write data to 64KByte. All memories can be written simultaneously in 64-byte units. Data (delete “0”
"), 64 bytes are written in the direction of the arrow in Figure 6.
The same data is written to the unit at the same time. therefore,
Memory erasing time is extremely short.

Interface Port 40 The plotter interface 42 is synchronized with the clock from the plotter 300 and transfers data in the memory unit 30 according to the operation of the DMA controller 43.

The DMA controller 43 performs block transfer in units of 300 Byje, and returns the common hash 50 to the CPU 3 every time the transfer of 300 Byje is completed. Commands to the plotter 300 and status from the plotter are read by the CPU 13.

The Centronics interface 41 is the CPU 13
Alternatively, it controls data transfer between the DMA controller 43 and the host 200. When the CPU 13 directly reads data, an interrupt is generated by a strobe signal from the host 200, and an accrual signal is generated by the CPU 13 reading the data. Data 1 of DMA controller 43
In the transmission, a DMA request is issued to the DMA controller 43 every time a strobe signal is received. When data is stored in the memory, an accross signal is generated.

The serial interface 44 controls serial transmission and reception of data in the DMA controller 43 or CI"'U1'3. When using the DMA controller 1 to roller 43,
The serial interface 44 requests DMA when the transmit buffer is empty or when the receive buffer is filled with data. [CPU], 3 directly handles transmitted/received data, generates an interrupt and requests service from the CPU 13.

The buffer memory 46 has addresses FCOOO to F D
memory of F F t;, CPU]3 and DM
It can be accessed by A controller 1-roller 43. By turning off the dip switch, memory 46 is disabled.

Next, I) MA controller] ~ To explain the setting procedure of the roller 43, first specify the command register, specify the bank number, specify the DMA transfer address, and then specify the DMA transfer address.
, specify the number of e, specify the mode register, and reset the mask register. This starts DMA.

When DMA is finished, the mask register is set.

The plotter interface 42 reads the status of the plotter 300, sets the DMA controller 43 if recording is possible, and specifies and sets a command. When a command is specified, data transfer by interrupt is started, and when the data transfer for all lines has been completed a number of times equivalent to the set number of sheets, the DMA mask register is set.

The Centronics interface 41 sets the DMA controller 43 at the time of DMA transfer, then transfers data using an interrupt, and when completed, cents the DMA mask register.

During DMA transfer, the serial interface 44
Set the DMA controller 43, set the serial mode, and set the serial command. This starts data transfer by interrupt. When the data transfer is completed, the DMA mask register is set.

The page memory focus map, data transfer, command format, etc. are as follows.

(1) Basic form a, page memory bitmap, size 3296 bits (vertical) x 2400 bins (horizontal) 1-4V 2 Bytes
X 300 Byteb, Pip 1 - Map rejection method Full horizontal sequential scanning (by external clock synchronization) C. Hitmap read method Full horizontal sequential scanning (by external clock synchronization) d. Data transfer mode (receiving) A) Text ( Text) Modero) Halftone mode C) Bin 1 to Image mode e, 4 types of halftone expression (4 groups) Each group has 64 density gradations One density pattern is 8 x 8 dot square matrix f, bitmap compatible Print area: 279 mm long x 203 mm wide (2) Page memory bit map a, horizontally divided into 4 (divided into 4 subpages) 1 subpage 824 lines (bits) x 2400 bits. Each subpage consists of 4 banks.

b. Addressing method Start position specified relative address (start position is absolute address)
. The coordinate origin is at the top left.

The starting address is common to each motoy) and c) in the X (horizontal) direction in Byte (8 Byte) units.

The y (vertical: vertical) direction is also Byte (8Bite: 8
1ine) unit.

b, Address unit horizontal direction Byte unit (from left to right) vertical direction 1i
ne unit (from top to bottom) C3 end address specification The end address is a relative address with respect to the start position, and corresponds to the count number of data.

In the text mode 1 of b), there is no specification. It is determined by the character size, character pinch, LF amount (line feed amount), and number of lines.

In the halftone mode of (mouth), the horizontal direction is the number of wards (], 13
yLe unit), the vertical direction is also the number of sections (81j, ne: J
[1yte).

In the P1-Image mode 1 of c), the horizontal Byte
, e unit, vertical direction is 1ine (bit) unit.

d. Range that can be written in the map memory (3296 dots vertically x 2400 dots horizontally) to valid data pin 1. Data (bits) that exceed this range (writable area) are invalid.

In the case of text mode (a), the range does not exceed the maximum number of existing a1 (responses).

(3) Data transfer a, alphanumeric characters of galactor data (character code data),
Numbers, based on Kanaha JIS C-6220. 8
By unit sign. In Kanji mode, JTS C-
6226 compliant.

b, halftone density data 1 Byte/block; Binary (0-63
) Ward = pattern = 8 x 8 bits Note that there are 32 functional character codes from 0 to 31, which occupy binary codes 0 to 31, and 3
2γ120 is assigned alphabetical characters, numbers, and notations, so to prevent confusion with these, density gradations 0 to 120 are assigned.
The data specifying 63 is a value obtained by adding 128 to the value indicating the real value, and when decoding it, 128 is subtracted from the content of the gradation data to obtain the actual gradation indication value.

C, bit dog data 1 pint/pel; Byte unit MOB...
L (leftmost pixel) LSB...R (rightmost pixel) d,
Numerical data Binary; ByIZe unit e, data transfer order from MSD to LSD (From the bottom to R: transfer the right Byte sequentially from the leftmost IBy shee).

f, control code JIS C-6220, an extended control code using a function character code based on 8-unit code and an ESC code.

Commands using ESC codes are completed with SP. S
l'=Space.

Note that the above functional character codes are 32 types from 0 to 31, and 0 to 31 of the binary codes are exclusive, and letters, numbers, and symbols are assigned to 32 to 120, so please avoid confusion with these. To prevent this, the data specifying density gradations 0 to 63 should be changed to 128 to the value indicating the real value.
When decoding it, 128 is subtracted from the content of the gradation data to obtain the actual gradation indication value.

(4) Control command The contents of the control command are as follows.

a, Command format % expression % b, Area specification command format F, SC+ (charcoal) +xlx2 yl y2 +cIC
2C3C4+5pxIx2: Horizontal start address (absolute address) y1y2: Vertical start address (absolute address)
CIC2: Horizontal end address (relative address) C3C4
: Vertical end address (relative address) Relative address is
Count value of starting address force 1 et al. Each address data is 2 Novates. The alphabetic character I indicates mode designation or command type.

C. Default mode is text mode, start address is the origin of the seat fence.

d, Mode specification text, tomo, -do ESC+A+xl Since there is no need to specify the end address in text mode.

Halftone mode ESC+G+n+5P n=o~4; n=o ends halftone mode, n=
1 to 4 designate each of the four groups of gradation types.

Bit image mode ESC+B+xl x2 y1y2 +cIC2C3C
4+5PC1 writing format % expression % n:! :0 or 1; n=o is memory clear & write.

n = 1 means overwriting (memory data and transfer data O
R). The data is "1" for recording and r]4 for non-recording.

n = 2 is exclusive OR (exe, OR) writing.

f, Entire page memory erase ESC+E+SP g, Partial page memory erase [ESC+D+x+xy'! +3'2 +CI
The C2C3C4+SP address is in 81ine units.

b, Specify font size ESC + S + n 10SP n = n = 5; n = 0 is equal size (reset), n = 1 is 1x width and 1/2x height, n = 2 is 1x width and 1/2x height. 2x, n=3
is 2 times the width and 1 time the height, n=4 is 2 times the width and 172 times the height, n=
5 indicates double width and double height.

n=O instructs to reset the character size, and is set to the same size by 1 noset (default).

i1 character space ESC+H+n+5P n=o to 32, and spaces are shown in dots.

j0 line simple space ESC+V 10n + SP n is a number with 81ine as one unit. Default number
= 0°k, print & memory clear ESC 10P+n+SP -20 to 99 represents the number of printouts (number of page memory transfers). Carrier n = O1, t n =
It is considered as 1.

(2) Print & Non-Clear ESC 1N + n 1SP n = 0 to 99, representing the number of printouts (number of page memo transfers). Carrying n = Ofyo n =
It is considered as 1.

m, definition of carriage return (CR) ESC + R + SP n = 0 is CR only, n = l is line feed L without CR
F only.

n = 2 is both CR and line feed LF.

n, definition of line feed (LF) [ESC + F + SP n = 0 is only F, n = 1 is only CR, n =
2 is both CR and LF.

Note that there are dip switches for setting the definitions of CR and LF, and when the definitions of n), , n, above are not commanded, the definitions set by the dip switches are followed.

0, return ゛CR P, line feed LF With the above configuration and the control program stored in the ROMII, the information storage device 100 has the following characteristics.

(1) The memory unit 21 has a memory (page memory) that is equal to or more than the number of pixels (dot number = bit number) for processing one page of the plotter 300, and (a) converts character codes from the host 200 into character pattern data (bit (pattern: pixels) and written in the area specified by the host 200 of the memory unit 21;
Converting the data into a halftone pseudo halftone pattern (bit information of the halftone pattern corresponding to the halftone data continues) and writing it into the area specified by the host 200 of the memory unit 21; c) From the host 200 A page memory is created using bits (pixels) in three modes: bit data (pixels) are written directly as bit images into an area designated by the host 200 in the memory unit 21. It is possible to switch between 3 modes and 1- within one page.

(2) Writing to the memory card 21 is performed by setting the writing start position of each mode to the nth power of 2 in pixel units (n in the embodiment).
= 3). It is preferable that n≦5. 1
(3) In the above (2), in the bit image mode (c), the end position designation that defines the end of the specified area is specified by a relative value from the start position in the same address unit as the start position.

(4) In (2) above, the write start position is immediately after the start of the device 1θ0 (when data is received for the first time after the power is turned on), especially when there is no specification from the host 1 to 200. The focus information is imported from the coordinate origin of the memory unit 21, and in other cases, the start position specified immediately before is the return position, and the previous end mode is C). In the case of a character pattern (A) or a halftone pattern (A), the address following the address that ended immediately before is designated as the designated address.

(5) Outputting one page of memory data from memory data 1 to 21 (The number of outputs can be specified from host 1 to 200, and the data in memory unit 21 may be retained or deleted after the data output for that number of times. It can be specified from the host 200.

:6) Data from host 200 and memory unit 21
It is possible to perform logical operations instructed by the host 200 on the memory data of the host 200, and update the result of the operation from the host 200 to a predetermined area. Logical operations include logical sum (OR), exclusive OR (Exc, OR), priority writing of host data, and inverted writing of host data.

These are inversion writing of memory data and memory erasing.

;7) Memory data in the memory unit 21 is transferred to the plotter 300 in synchronization with the speed of the plotter 300.

18) It has a mark and a command table for interpreting commands from the host 200 to the device 100, accepts loads from the host 200, rewrites the command table, uses this for command interpretation, and reads the command table from the host 200. allowed for changes.

19) In (8) above, the command format consists of a functional character code, a character code, and a parameter (numeric code), and the number of each used is variable length (not limited).

[10] In (8) and (9) above, the command table has a variable length of 71-x, and the lengths of its rows and columns are variable length (IIIN undefined).

(11) In (8) to (10) above, each command is assigned to each column, and each column includes a line for the number of characters used in the command, a line indicating the end of the character code, and a line for the parameter size. The number of lines corresponds to the line indicating the command line and the line indicating the processing routine, and the line indicating the end of the character code of each column is set to 0, and the end of the used column string (command string) is the first column. The line (function character code string) is determined as "0".

(12) Character pattern equal size memory 2 Reduced memory and enlarged memory are possible, and character pattern data (bits) are stored in the memory unit 21 in these modes according to character size specification from the host 200.

(13) In (12) above, the vertical size and horizontal size can be selected separately, and character pattern data (bits) are set in vertical and horizontal sizes according to instructions from the host 200.
is stored in memory bits 1 to 21.

(14) The dot matrix structure (bit data distribution) of the original character pattern is an integral multiple (1 or more) of the address unit when specifying the writing position, and the space between characters is
An integer multiple (including 0) of the address unit and host 2
It can be specified starting from 00.

(15) In (14) above, the dot matrix structure of the character pattern has an integral multiple of twice the address unit in the vertical direction, and the space between character lines is an integral multiple of the address unit (0
), you can arbitrarily specify the host 200 force N etc.

(16) There are 4 types of halftone patterns (4 groups), LJ, and each group has 64 patterns (64 gradations). Said (1
), the host 2 of the memory unit 21
In the area specified by 00, specify the halftone number (turn) specified by the host 200 with the tone data (# degree data) from the host 200 from the turn group, and write the pattern. Write.

(17) In (16) above, the transfer number of gradation data;
When the host 200 first notifies (declares) a halftone, the tone data includes at least IBit attribute data (data indicating that it is tone data) at a predetermined position]Byl;e as tone data. Interpret.

(18) In (17) above, the IByte gradation data includes multiple bits of attribute data (data indicating the group) that specifies the gradation group.

(19') In the above (J6), the host 200 transfers the data specifying the write area (closed area: start end address and end address) of gradation storage.

When specifying the write area in this way, the host 200
also transfers attribute data specifying the ffI tone group.

(20) The host 200 can define the functional character codes CR (plotter return) and LF (plotter line feed) using commands.

(21) If there is no definition of CR or LF from the host 200 (default), the definitions according to the state of the designated switch that defines these definitions are followed.

(22) Equipped with a DMA controller 43, image data (pixels) are transferred from memory units 1 to 21 to the plotter 300 by the DMA controller 43 to an 8-bit buffer, and synchronized with the recording operation of the plotter 300. The data is converted into serial data and output to a plotter.

(23) The DMA controller 43 can also be applied to data input/output with the host 200, and when transferring data with the host 200, the data is transferred to the accumulator number of the CPU 13;
Transfer is possible in the CPU mode in which the data is captured and then sent out, and in the DMA mode in which the data is transferred by the DMA controller 43.

Table 1 below shows the contents of the standard command table.

A comparison between each of columns 1 to 6 of Table 1 and the contents of the command is shown in Table 2 below.

Table 2 **Memory data inversion specifies that the data in the page memory is inverted and updated. The command is ESC+I+n+SP, where n=0 is a positive image (no memory inversion) instruction, and n=1 is an inversion (negative image) instruction for rewriting.

*** Rewriting the command table instructs additions and changes to the contents of the table shown in Table 1.

The command is ESC+X+z1z2 Z3 Z4 z5
25 +spte, Zl is data indicating a numerical value specifying column M, and 22 to Z6 are information data to be written in rows N=1 to 4, respectively.

Next, the operation of the CPU 13 based on the control program stored in the ROMII will be explained.

First, reference is made to FIG. 7 which shows an overview. When the power is turned on, the CPU 3 undergoes initialization, declares variables, defines subroutines, and proceeds to the main program. In variable declaration, define all variables used in the control program. In subroutine definitions, subroutines that are called from the main program and other subroutines are defined. Each processing part that makes up the program is made into subroutines as much as possible, and data processing is executed by calling these subroutines. The main subroutines are (a) to (ma) shown in FIG. Subroutines include elemental subroutines that perform only one process, and compound subroutines that call these subroutines and perform a set of processes.

The main program calls elemental subroutines or compound subroutines into a process class and repeats them so that a series of data processing is performed.

In the initial setting of the main program, a subroutine (force) is called to set a read/write area (coordinate origin immediately after power is turned on) in the write area setting table. Next, subroutine (d) is called to write standard commands as shown in Table 1 into the command table.

Furthermore, subroutine (a) is called to set initial values (defaults). Then, subroutine (a) is called to erase the entire page memory (31). and the command (
command).

When a command arrives, data processing begins. In data processing, first a subroutine (nu) is called to interpret an instruction (command), and then a subroutine (to) is called to process and set parameters in the command. Next, a subroutine (N) is called to select the processing operation specified by the command. When a processing operation is selected, processing such as memory reading is performed according to a subroutine that executes the processing operation.

When the processing is completed, the process returns to the command waiting state before data processing.

Next, each of the subroutines will be explained with reference to FIGS. 8 to 39.

(A) Initial settings (Figure 8) Clear start address input register SAX (x coordinate vA) and 5xy (y coordinate), clear start address storage register xAo+t (x coordinate) and VADR (y coordinate), and set virtual Clear bitmap space coordinate registers X and ■. Next, the character pattern and halftone pattern]
Set the horizontal (x) of the area (section) to 3 bytes (24 dots),
Set the vertical height to 6 heights (48 toso h = 48 lines), set the character spacing to 1 by 1- (8 doso 1-), set the line spacing to 0, and change the lowercase alphabetic character code to uppercase alphabetic characters by 1-.
(Since the command consists of uppercase letters, this conversion is performed for the purpose of reading even if the input is in lowercase letters.) Turn off (no conversion)
Then, set the pattern table (text character memory & density gradation pattern memory) reference to text mode (text character specification), set the return action CR only to the return CR corresponding to n = O, Kai action LF
Set only the line feed LF equivalent to n = O, set the font size to the same size as n = 0, and overwrite (OR writing)
Set it to none, set it to no rewriting, and set the number of prints (number of times page memory data is transferred to the printer 300) to 1 (default settings). The writing area is outside the actual writing area (that is, no writing)
Set to .

(b) Erase the entire memory (Figure 9) Set simultaneous writing to all areas, write 0 (non-recorded data) to the first address (in bytes) of the writing area5, and sequentially transfer it to the next address. .

After performing this transfer 65,535 times (the number of bytes for one bank), erasing of the entire memory is completed. That is, data in all 16 banks are erased simultaneously.

(1) DMA output (Figure 10) When the plotter 300 is ready, clears the subpage counter (register), sets the read line to 1, resets the hardware between the device 100 and the printer 300, Set read bank to 7, set DMA enable and specify DMA operating mode for ports and interfaces, set address to 0, set transfer byte counter to 304, disable interrupts and set subpage to 0. and starts DMA transfer to block 300. When the contents of the transfer byte 1-counter become 0, the address is set to 0 again, the transfer byte counter is set to 304 again, and the DMA is activated.

□Every time the number of transferred bytes reaches 304 (transfer bytes 1-
(Each time the contents of the counter becomes 0), the read line is moved to the next line, and when reading of one bank is completed, reading of the next bank is proceeded, and when reading of a subpage is completed, reading is started to the next subpage. Proceed.

When the number of read lines reaches 3296, DMA is prohibited,
Enable interrupts and end this subroutine.

(1) Printing (first construction drawing) When the plotter 300 is ready, the above-mentioned (1) DMA
Execute the output, and when it is finished, subtract 1 from the set number of prints for print 1, and if the remaining value is 0, if memory erase after printing is set (a) Execute the subroutine for erasing the entire memory (a) Execute the initial setting subroutine and then return to the main routine. If memory erasure after printing is not set, proceed to the (a) initial value setting subroutine without executing the entire memory erasure. This print 1 subroutine can be repeated until the remaining number of prints reaches 0.

(E) Writing area/address setting (Figure 12) If the current writing line is 3296 (this does not exist in the effective address), writing for the entire page has been completed, so the corresponding The value obtained by subtracting 3296 from the number of written lines (0)
Change the writing line to (this returns you to the beginning of writing). If the write line is 3295 or less, continuous writing is possible, so check whether it is necessary to switch banks and subpages, and if necessary, switch banks or subpages. When switching is not necessary, the number of 304 bytes for one line is added to the write absolute address to advance the write position to the next line. Then, the contents of the write line counter (register) are incremented by 1 and this subflow is ended.

(Power) Writing area setting table (bank and subpage settings) (Figure 13) Bank No. and subpage N assigned to the line number, with the line number (contents of the line counter) as an argument.
There is a table in which the number o is stored, and by referring to this table, the bank number and subpage number are determined, and the bank and subpage to be allocated as the write area are set.

FIG. 13 shows the bank and subpage allocation obtained by referring to the table.

(g) Half-width characters (standard) (Fig. 14) Character pattern memory (character memory) is 3 by 1 horizontally.
-1 vertical 48 lines, all of these lines are in focus 24
It is stored in the character memory in the form of 4B arranged in a row. This data is stored in a single column in the same half-width character buffer.

First, the line number counter C is cleared, and the value obtained by calculating the next absolute address y and subtracting 304 (bytes, 304 is the number of bytes for one line) from the absolute address vv is set as the absolute address. This subtraction is done by adding 304 to the absolute address and advancing the write area by one line in the third step of the above-mentioned (e) Write area/address setting, which is an element subroutine of this subroutine, so correct it by that amount. It's for a reason. Subtraction in 304 in other subroutines described below has the same meaning.

When the absolute address yy is set as described above, the process proceeds to (e) write area/address setting, and after exiting there, the half-width character buffer data is memorized in the set bank.

In this memory operation, the half-width character buffer contains the 3 bytes (24 dots) of the first column (line 0) of the character pattern as the 3 bytes of the first block, and the second
The 3 bytes of the column (first line) are stored as the 3 bytes of the second block, and finally the 3 bytes of the 48th column (47th line) are stored as the final 48th block, so the write The position where the number of lines C is multiplied by 3 (0,
3, 6, 9, . . . ), every 3 consecutive bytes are stored in the set bank. That is, the pattern data pin 1 arranged in one column is converted into 3 horizontal bytes x 48 vertical lines and written into the page memory.

(ri) Half-width, half-length characters (Figure 15) In this example, from the character buffer that stores pattern data of 3 horizontal bytes x 48 lines in one column, write the number of lines C multiplied by 6 (0, 6 ,1,2,+8...
) and stores it in the set bank. That is, the data obtained by discarding the data of even numbered lines of characters is converted into 3 horizontal bytes x 24 vertical lines and written into the page memory.

(g) Half-width double-length characters (Fig. 16) In this case, a repeat writing counter cc is used. Read every 3 bytes from the character buffer that stores the pattern data of horizontal 3 bytes h x 4g lines in one row starting from the position (0, 3, 6, 9, ...) where the number of lines to write is multiplied by 3. The data is stored in the bank set by , and the write line is changed and the same 3 bytes are written to the next line as well.

That is, when the first write is completed, the counter CC is incremented by 1, the same 3 bytes are written to the write line again, the counter CC is further incremented, and the count value becomes 2, and then the counter CC is cleared. be done.

That is, data written twice over two lines of data for each line of characters is converted into 3 bytes horizontally by 96 lines vertically and written into the page memory.

(J) Full-width characters (Figure 17) In this case, each bit of each character line is written twice in succession into a full-width character buffer that stores pattern data of 3 horizontal bytes x 48 lines in one column, and then A string of focus information in which two consecutive bits of the same bit information are stored is stored in the character buffer. Therefore, the full-width character buffer has twice as much bit information as the number of bits of one character pattern. From the full-width character buffer, every 6 bytes from the position (0, 6° 1248, . . . ) where the number of write lines C is multiplied by 6 are read and stored in the set bank. That is, 6 consecutive bytes (information is the contents of 1 line) are written to the page memory as one line. Therefore, one column of data is converted into 6 byes horizontally (48 dots 1-) by 48 vertical lines and written into the page memory.

(S) Full-width half-length characters (Figure 18) In this case, as well, each bit of each character line is stored in the full-width character buffer in the (C) full-width character preprocessing that precedes this routine in the same way as for the (C) full-width characters described above. is written twice, and a string of bit information in which two consecutive bits of the same bit information are stored is stored in the full-width character buffer. However, since reading from the buffer is performed every 6 consecutive bytes starting from the 12th position of the number of lines, the data is written to the page memory with the data of even numbered lines discarded, and is therefore stored in a half-length memory.

(C) Full-width double-length character (Figure 19) In this case, as well, in the (C) double-width character preprocessing that precedes this routine, each bit of each character line is stored in the double-width character buffer in the same way as for the (C) double-width character described above. is written twice, and a string of bit information in which the same bit information is stored in two consecutive bits is stored in the full-width character buffer. Also, as in the case of half-width double-width characters in (e), the double-write counter CC is used and the same line data (full-width) is written on two consecutive lines, so the page memory has 6 horizontal heights. ,
×Character data is stored in 96 vertical lines.

(S) Halftone pattern (Figure 20) There are four types (groups) of halftones, and 64 gradations are assigned to each group. Each gradation is 1 byte (8 bits) horizontally x 8 lines vertically ( 8 bits) = 8 byte pattern.

In FIG. 20, patterns 1 to 4 indicate types (groups) of halftones. The halftone data indicates the type of halftone and the density gradation. The data indicating the type of halftone is saved as is.

First, to explain from the beginning of the flow, 1 from the halftone data.
Subtract 28. As explained earlier, the command function character code, alphabetic characters, and symbols with numbers 0 to 120 are based on the JIS C-6220, 8-unit code standard (
ASCII code), and in this embodiment, numbers are assigned to functional character codes, alphabetic characters, and symbols according to this standard. Therefore, if the gradations from 0 to 63 are expressed in binary as they are, confusion in identification is expected, so the number obtained by adding 128 to the gradation numbers 0 to 63 is given to the post-200 system [100] as the gradation data. I have to. Therefore, in the subflow of this halftone pattern, 128 is subtracted from the gradation data to reproduce data representing gradations 0 to 63 themselves. Next, since the l minimum pattern is 8 bytes, the data representing the gradation is multiplied by 8 and stored in the gradation pattern read address register F.

Next, identify a read pattern group using the saved halftone type data, read out the 8 bytes (64 bits of the minimum pattern) from the Fth of the group one by one, transfer them to the half-width character buffer, and start. 1~Address VADR
Multiply (pi 1-) by 8 and store it in line register y,
Store address XADR to star 1 in X register X,
Clear Rakugo line register C and absolutely 71'less YY
Calculate =304X(1/MOD 20g)+X.

That is, since the X and Y addresses are consecutive in the memory, the absolute address YY is obtained by dividing ■ by 208, taking the remainder, multiplying it by 304, and adding X. Next YY
The value obtained by subtracting 304 from the above is set as Y'V. Next, it is checked whether or not reverse writing is set, and if it is not set, the process proceeds to normal writing shown in FIG. 21, and if it is set, the process proceeds to reverse writing shown in FIG. 22.

To explain normal writing with reference to FIG. 21, first, execute the above-mentioned (e) write area/address setting to set the write area of the page memory, and then write to the set area. Write each byte of the half-width character buffer in correspondence with the line number. Every time you write 1 byte to 1 line, line number counter C is incremented by 1, and when the column 1 value becomes 8, write is started. 1 Finish. As a result, 8 vertical lines have been written in 1 horizontal 1 by 1 minimum pattern.

Inversion writing will be explained with reference to FIG. 22. The inversion write is the same procedure as the normal write described above, but the difference is that each bit of each byte is inverted from "1" to "0" and "0" to rlJ and written to the page memory. There is.

(C) Full-width character preprocessing For (C) Full-width characters, (S) Full-width half-length characters, and (C) Full-width double-length characters, one pixel of the character pattern (character) data is stored in the double-width character buffer. - sideways 2
Bits must be stored consecutively. The reason for this storage is this full-width character preprocessing.

In this case, first, the character read line number counter C1 is cleared, the full-width character buffer is cleared, and then the character data (3 bytes of each line are sequentially arranged in one horizontal column; a total of 3 x 48 Write each filler 1- to the full-width character buffer in consecutive 2 bits 1 for each 3 bytes of the byte), and when this is completed, the counter C is set to 1 Kan 1-.
Upload it, and this time write the next 3 bytes of character data,
Similarly, convert it to 6 bytes and store it in the double-byte character register. Then, the counter C is incremented by one.

The same applies below.

When the content of counter C reaches 144, all character data processing for one character has been completed, so if a full-width character is specified by referring to the character specification, the above-mentioned subroutine for full-width characters (C) is executed. When specifying long characters (su)
In the subroutine for full-width half-length characters, and when specifying full-width double-length characters, (C) full-width double-length sentences (X) pattern processing (second
4a and 24b) The pattern (font) includes:
There are character patterns and halftone patterns. The character code 1 follows the ASCII code of JIS C-6220,
According to this regulation, the functional character code is 0-31, 32
Symbols, numbers and letters are assigned to ~120, and 12
1 to 151 are undefined, 152 to 210 are assigned katakana characters, and 211 to 230 are undefined. Therefore, symbols, numbers, alphabetic characters, and katakana are assigned codes sequentially starting with O, but in order to prevent confusion with undefined codes, etc., symbols, numbers, alphabetic characters, and is a code with 32 added, and katakana is a code with 64 added.

Therefore, in the case of characters, when the code is O・~31 (data < 208), 121~151 (7FH < data A 0
+1) and 121 to J51 (DFH<data), this subroutine is terminated as an error. If the data is in the character allocation range, when data < 80H (symbols, numbers, and alphabets), 32 is subtracted from the data and it is reproduced as character data, and data > 9F.
When the number is 11 (katakana), 64 is subtracted from the data and the result is reproduced as character data. This results in
The reproduced character data returns to character data in which numbers, symbols, two alphabetic characters, and katakana are assigned in consecutive codes.

Next, the character code is multiplied by 144 and this is set as the read address F of the character pattern memory (character memo). This is to specify the start address of the character data since 144 by 1- is assigned to one of the character characters. Next, read the character data from the pattern memory, multiply the start address VADR (by 1-) by 8, store it in the line register Y, store the address XADR for star 1 in the λ register X, and specify it by referring to the character designation. The process proceeds to the subroutine for the various character sizes described above for the selected character size, and upon exiting therefrom, the star 1-address XADR is advanced to the next step.

In the case of halftone mode, its density gradation data is the sum of 128 as already explained, and 128
If ≦data≦191, the above-mentioned halftone pattern subroutine is executed, the start address is updated, and this subroutine is ended. When the data is outside the range, this subroutine is terminated and the halftone pattern subroutine is not executed.

(i) CR (return) operation setting (Fig. 25) This subroutine performs (a) initial value setting (default), (n) instruction decoding, which will be described later, or register CR stored in register CR by reading the tesops inch. Update the page memory read/write address based on specified data. Since 0 in the CR designation data instructs execution of only CR, in that case, the X-axis start address is set to the first start address. Since 1 in the CR designation data instructs execution of only UF, in that case, the y-axis start address is updated to a value obtained by adding the number of lines corresponding to the character size L and interline space V to the current value. CR specification data 2 specifies both CR and LF, so in that case, set the X-axis star door 1-less as the first start address, and set the Y-axis star door 1-less as the character size I2 and line spacing. □Update the number of lines equivalent to V to the current value.

(H) LF (Line feed) setting (Figure 26) This subroutine performs (A) initial value setting (default), (J) command decoding (described later), or based on LF designation data stored in register LF by dip switch reading. to update the page memory read/write address. LF
Since the specified cheater O instructs execution of only LF, in that case, the V-axis start address is set to the first start address. Since 1 in the LF designation data instructs to execute only CR, in that case, the X-axis start address is updated to a value obtained by adding the number of lines corresponding to the character size L and interline space V to the current value. LF specification data 2 is CR and LF
are specified together, so in that case, set the X-axis star 1-address as the first start address, and update the Y-axis start address to the current value plus the number of lines equivalent to the character size L and line spacing ■. do.

(T) Centronics input (Figure 28) When the interrupt prohibition is canceled, a ready (receivable) signal is output to the host 200. When data is received from the host 200, the data is taken in from the Centronics interface 41, the host 200 is set to busy (reception not possible), and interrupts from outside are prohibited.

(TE) Bit image processing (Figures 27a and 27b)
Figure) Since one unit address is 8 vertical lines (1 byte), in order to convert this to an address in line numbers, multiply the ■axis start address by 8 and set the Y-axis in-address■. Set the start address on the X-axis as is. Then, the horizontal width 1 and vertical width J of the area specified by the received data are set as target values. Next, clear the line number counter CC and read the absolute address YVt! : The value obtained by subtracting 304 from it is the absolute address ■v
As a Seno 1-. Next, clear the width counter C, refer to the inversion write or distortion force 1, and (2) execute the centronics input to store the received data (pitch 1-data) in the 1-minute width pit nozzle. Reverse writing is specified)N
It's Sakuko's turn. At this time, the data bit rLJ and "
0" is inverted and stored. When one line of bit data corresponding to the width is stored in the pino 1 buffer, (e) the write area
Execute the I-less setting, check whether writing after clearing is performed or not, and if it is writing after clearing, write the bit data for one line width of the bit buffer to the set bank, and write the bit data of one line width of the bit buffer to the set bank, and cc is incremented by 1, and the horizontal counter C is cleared to receive 5 signals of one horizontal line, write to the pit buffer, set a write area address, and write to a predetermined bank of the page memory. When the contents of the line number counter cc reach J+1, writing of line #J has been completed, so this subroutine is ended. If writing after clearing is not specified, after setting the write area address, read bit data for the width (c+1 pie 1-) from the set bank of the page memory to the memory buffer, and set the bit data counter BC. When cleared and overwriting is specified, each bit of the pit buffer and each bit of the memory buffer are logically summed (OR)ed in the order in which they are arranged, and updated memory is stored in the pit buffer. The pinot l-data counter is incremented by 1 for each update memory, and when the contents of the bit counter BC exceed the contents of the width counter C, that is, when the logical residue for one width line is processed, the contents of the pit buffer are paged up. Write to memory setting bank, line number counter C
Increase C by 1 count. When exclusive OR is specified, perform the exclusive OR of the bit data in the page memory and the bit data in the pit buffer and update the memory in the focus buffer using the same procedure as for logical OR. then write it to page memory.

(g) English/IX character/capital character conversion (Figure 29) Referring to the command table shown in Table 1, commands are composed of uppercase English letters and numbers. Therefore, a broutine for this conversion is provided so that commands can be interpreted even if they are in lowercase letters.

First, an uppercase English letter is 96〈data〈123, so anything outside of this is a lowercase English letter. Since lowercase English letters have a code 32 greater than uppercase English letters, the code representing the value obtained by subtracting 32 from the input code is corrected to the character code. When the conversion is completed, the flag SW is set to OFF, indicating that conversion is not required.

(S) Partial erasure (FIGS. 30a and 30b) Partial erasure is equivalent to storing rQJ in a designated area in the same manner as the above-mentioned (te) bit image processing. Since it is sufficient to store "0" in the entire designated area, partial erasure is performed by writing "0" in the leading bit of each line in the designated area and transferring this along the line.

(d) Command table writing (command table tabulation) (31st
Figure) RAM command table write area address CV=O~
50 (column M in Table 1) is cleared.

This is the content from the first step to the seventh step. Next, write data as shown in Table 1 into each column A and row N and their 71-rix intersections.

(J) Instruction decoding (Fig. 32) Clear the row N register Cx and column H register C■, and receive command data at the aforementioned Centronics input. If it is a command, the beginning of the data must be ESC.
Otherwise, it is data indicating O or a number of 32 or more. Therefore, if the data is not 0 and is not 32 or more, the lowercase/uppercase conversion flag 5Ill is referred to, and if it is on, conversion is necessary, so the above-mentioned (g) lowercase/uppercase conversion is executed.

If it is off, the conversion has finished, so refer to the data as is and compare the contents of the input data with the data at the matrix intersection specified by the contents of the row N register CX and the register CY in the column (Table 1). Then, the contents of registers Cx and CY are counted and amplified until data matching the input data is read out.

That is, first, enter the function character code of the input data in the command table (Table 1), row N = ¥), columns 0 to 50 (
It is possible to write up to M=50, and in the example in Table 1, A=1.
Up to 6 has been written, and N=17 to 50 are empty: "0" is written in all) data and M=0, sequentially 1, 2, 3, etc. Compare and if it matches, H
is fixed and the row N is sequentially increased by 1, and the data at the matrix intersection specified by H and N is compared with the data below the functional character code of the input data.

If the data of row N=3 is read and compared and is not the same, A is incremented by 1 and the same data comparison is performed.

If the data in row N = 0 to 3 and the input data match exactly, the value in column A at that time is the input command number, and the data in row N = 4 in column A is the one specified by the command. Indicates a subroutine. Default is text 1
~ mode, the function character code part of the command is r.
At the time of OJ, 0, which instructs pattern processing (phono 1 to processing), is stored in the processing instruction register OP.

In other cases, the data matching the input command data is
The data of row N=4 of the column having the following values is stored in the instruction register OP.

(v) Processing operation selection (FIG. 33) In this subroutine, a subroutine is set according to the contents of the processing instruction register oP. The content of 0 in the processing instruction register OP indicates pattern processing (font processing) as described above.
Therefore, in this case, (n) pattern processing is set. When 0P=2, (TE) bit image processing is performed as 0P-
4 performs (su) partial deletion, 0P=5 performs (b) entire memory deletion, 0P=14 performs (1) pudding 1-, 0P=
At 16, (1) print, at 0P=27 (evening) CR
When 0P=28, set (H) LF operation setting, and when 0P=24, set (E) instruction rewrite.

()) Parameter calculation (1) (Figure 34) The parameters in the command are XI X2 y+! In the case of four Y2, these indicate the start address. Xl is the upper 8 bytes of the X address + X2 is the lower 8 bytes ryl
is the upper 8 bytes of the y address.

Since y2 is the lower 8 bytes, set 256Xx1+x2 to the start address register SAX, 256 x y
1 and y2 are stored in the start address register SAY.

(c) Parameter calculation (2) (Figure 35) Command parameters are XI X2 :Y'l V2rCI C2C
In the case of 8 pieces of 3C4, 256Xx1+x2 is the start address register SAX2, 256Xy, +y2
is stored in the start address register SAY, and C1 to c
4 is the end position from the start address (relative address)
, so 256Xc]+c2 is the X address.
Add 256Xc3 + c to the byte counter XADC.
Store address byte counter YADC, XADC to target byte register 1, contents of YADC (bytes)
The value obtained by further adding 7 to the number obtained by multiplying 8 by 8 is stored in the target line number register J. In addition, adding 7 is VA
When DC is 0, it indicates an area of 0 to 7 lines, so it is set to 7 at the end.

(H) Parameter setting (1) Start address parameter (Figure 36a) Execute the non-parameter calculation described above and store the calculated address in the X address register (current position register) XA'DR
and stored in the X address register. All data is in bytes.

(2) Bit image parameters (Figure 36b) Execute the above-mentioned (c) parameter calculation (2). The X direction is in byte units, and the X direction is in line units.

(3) Partial erasure parameter (Figure 36c) (c) mentioned above
Execute parameter calculation (2). The X direction is in hide units, and the X direction is in line units.

(4) LF operation parameters (Figure 36e) Register LF
The value of parameter n in the LF operation designation command is stored in .

(5) Halftone mode parameter (FIG. 36c1) Store the value of parameter n in the halftone mode command in the pattern table selection register PT.

When n=0 (end of halftone mode: return to default, same as specifying text mode), set the width W of the font size to 3.
Byte (half-width), vertical byte 6 bytes (48 lines two full-width)
, set the character space H to 1 byte and the line space ■ to 0 (default). When N is not 0 (halftone instruction), the pattern size is set to 1 byte horizontally, 1 byte vertically (8 lines), and 1 horizontally to the space between patterns.
Set both 1 and vertical ■ to O.

(6) Character spacing parameter (Figure 36f) Store the value of parameter n of the character spacing designation command in the character spacing parameter register H.

(7) Reverse write parameter (Figure 36g) Write the value of parameter n of the memory data inverse designation command to the reverse write instruction register RE.

(8) Number of prints when memory is retained after printing (Fig. 36h) The value of the parameter n of the print non-clear command is stored in the print number register CN.

(9) Number of prints when clearing pudding 1 to bag memory (
(FIG. 36i) The value of parameter n of the print clear command is stored in the print number register CN.

(10) CR operation parameters (Figure 36j) Register C
The value of parameter n in the CR operation designation command is stored in R.

(11) Character size selection parameter (Figure 36) Store the value of parameter II of the character size specification command in the character size register S, and when the stored value (,,) is 0, the pattern is set to 3 bytes ( Half-width layer, vertical 6 by 1-(
48 lines). When it is 1, W is 3 high 1
-1L to 3 by 1, when 2, the needle is 3 by 1-1
L becomes 12 by 1-, when 3, ν becomes 6 bytes, L becomes 6 bytes, when 4, lll becomes 6 by 1, L becomes 3
Bye I-.

When it is 5, set the lever to 3 bytes and L to 12 by 1-.

(I2) Line spacing parameter (Figure 361) Set the value of parameter n of the line spacing command to the line spacing register ■
Store in.

(13) Overwrite parameter (Figure 36m) Parameter [1] of the write designation command is stored in the write designation register RO.

(14) Instruction rewriting parameters (Figure 36n) Row N
Clear the force change register C and enter the first O of the change register EX.
Column data at the position, and row N=0゜1.3,4
In the corresponding positions 1, 2. 3 and 4, sequentially the command N
=O, N=1. Store data (parameters) for N=3 and N=4.

()) Parameter setting selection (Fig. 37) Similar to the above-mentioned (v) processing operation selection, the content of the processing instruction register OP is referred to in (j) instruction decoding, and the above-mentioned ((v)) is selected according to the contents of OP.
h) Execute the subroutine for parameter setting (Figures 36a to 36n).

(v) Parameter processing (Figure 38) Refer to the data stored in the register after instructing the process by decoding the command (v) above. If it is 0, it is text mode, and if it is 27 or 28. CR (return) or L
Since it is F (line feed), this routine ends. In other cases, clear the counter C, read the parameters one by one using the sensor 1 to ronix inputs, and set the counter to 1.
Count 1-up, the number of reads is the row N of the command
The number of parameters P = 3 is the number specified in advance, and the Centronics input data indicates 32 (the end is set to 0).
However, since the function character code is 0 to 32, 0+32 is used to indicate the end of 0), which indicates the end of the command. End the subroutine.

(e) Instruction rewriting In the above-mentioned (14) instruction rewriting parameters, change data (parameters) in the command are transferred to the rewriting register EX in the column, row N=O data, N=1 data, N=3 data. and N = tI data, so EX is stored in the command table column address register CV.
The first 0 data, that is, the column data, is transferred to the row N=O, N= of the specified column of the command table.
1. N=3 and N=・1, respectively, the second number 1 of EX
~Write the data of No. 4 and 3.

FIG. 40 shows the output timing of page memory data of the device 100. When outputting to the plotter 300,
Plotter 3 outputs data W DATA for each line in synchronization with the signal QLGATE from plotter 300.
Give to 00.

By executing each of the above subroutines, the start address immediately after the power is turned on will be as shown in Table 3 below, and the start address thereafter will be as shown in Table 4 below.
Thereafter, after executing either mode, the results will be as shown in Table 5 below.

Table 5 Previous processing: Text (- Later processing Text 1-: Next address Halftone: Next address Pino 1-Image: 1 Wait for affirmation. If not specified, it will remain stopped.

Previous processing: Processing after halftone Text 1-: Next address 1-Address halftone secondary address Pi 1-Image: Waits for designation. If not specified, it will remain stopped.

1) Processing of i: Bino 1-Image Post processing Text: Position after CR or LF operation.

Halftone: Same as above Pino 1 - Image: Wait for CR or 1, F and subsequent designation. If not specified, it will remain stopped.

Put 24 in the operation register OP to the sensor 1, and then (to) parameter processing to receive the 5 gB parameter from the host h200 at the sensor 1 input. Then, proceed to ()) parameter setting selection, and since 0P = 24, execute (14) instruction rewrite parameters (Figure 36n), store 5 parameters in conversion register EX, and then (n) perform processing operation. Proceed to selection, where OP = 24 (e)
The program advances to the command style, and in this subroutine, the contents of the column specified by the first parameter of the command table (Table 1) are rewritten. Note that when a column that has already been written to is specified, it is literally a rewrite, but when a column that has not been written to (a column in which 0 is written to row N = 1) is specified, it is rewritten. This will write a new command.

In this way, command rewriting (and writing) is performed by the host 20.
Since this can be done with an instruction to change the command table of 0 to 1, the host 1-200 can change commands (standard commands) set in the control program and add new commands to the device 100. In other words, changes in command definitions, new commands, and host l-200
The address delta given to the device lOO is in bytes, and in text mode and halftone mode, the writing start address is set in ()) parameter calculation (1),
In bit image mode (c) Parameter calculation (2)
The Δinclude start address and the Δinclude end address are set. These addresses are bil, ,! It is IL rank.

As explained above, immediately after the power is turned on, the initial settings [(power) budding area setting table, (d) command table writing, and (
b) Erase entire memory] and wait for command. When an external interrupt is received, (nu) executes instruction decoding,
(v) Execute parameter processing, (v) Execute processing operation selection, and execute the selected process.

Next, several types of processing operations in response to commands will be described.

(1) Rewriting the command table When a command to rewrite the command table comes from fiI to host 1 from 200, (parameter L is
-Set the number of parameters 5 to register P, and perform the processing operation (
2) A text mode processing start address specification command is sent from the host 200 to the device 10.
If given 0, this is text mode since it specifies only the starting address. In halftone mode and bit image mode, an end address is always specified.

Upon receiving the start addressing command, the device 100 (
n) Set the number of parameters to 4 in the parameter register P by decoding the instruction, set 1 to the processing operation register OP,
Next, select the four parameters using parameter processing.
Receives transfer from the host 200 by -onics input. Then, proceed to ()) parameter setting selection, and since 0P=1, proceed to (1) start address parameter (Figure 36a), ()) execute parameter calculation (1), and start 1.
-Start Address Regis',! 9XADR
and YADR to complete the text mode start address setting.

After that, when the host 200 sends the character code, (
N) Set op=o by decoding the instruction, and since 0P=0, pass through the parameter processing as is, and then (N)
Select the processing operation to proceed to pattern (font) processing, convert the character code, read the character pattern data from the pattern memory (character memory), store it in the character buffer memory, and convert the character code according to the set character size. ) half-width characters, (ri) half-width half-length characters, (ke) half-width double-width characters, or (
C) Proceed to full-width character preprocessing.

When proceeding to one of the first three methods, address calculation is performed, and (e) writing area/address setting is executed, character pattern data is subjected to predetermined character size processing, and is written to the page memory. (C) When proceeding to full-width character preprocessing, character pattern data in the character buffer memory is expanded from 1 horizontal bit to 491.2 bits to create character pattern data in the full-width character buffer, and according to the character service specification. te (ko) Full-width characters.

Proceed to (ri) full-width half-length characters or (shi) full-width double-length characters, perform the arithmetic operation there, and then (e) write area.
Execute address setting, perform predetermined character size processing on character pattern data, and store in page memory.

Note that the default is text mode, so when the character code is sent from the host 200 from the beginning after the power is turned on, 0P=0 is set in (nu) command decoding, and 0P
= 0, so it passes through parameter processing as it is, and then proceeds to (n) pattern (font) processing by selecting (n) processing operation, converts the character code, and reads characters from pattern memory (character memory). Reads the pattern data and stores it in the character buffer memory, and prints half-width characters according to the set character size.

Proceed to (ri) half-width half-length characters, (k) half-width double-length characters, or (c) full-width characters preprocessing. The operation is the same as when receiving the character code data described above.

(3) Halftone mode Halftone mode specification command is sent from the host 200 to the device 10
0, the device 100 sets the number of parameters to 1 in the parameter register P and 7 in the processing operation register OP in (C) instruction decoding, and then sets one parameter in (C) parameter processing. Receives transfer from host 200 through Centronics input. Then, proceed to ()) parameter setting selection, and since it is 0P-7, proceed to (5) halftone mode parameter (No. 36d), where depending on the value of parameter n, N = O, and 1 is halftone. The writing format is set to text 1-mode default (
Standard). Since N21-4 designate the type of gradation, at this time a writing format of continuous focus writing is set. Next, (v) processing operation selection is 0P=7, so it passes through as is.

After that, when the host h200 sends the halftone code,
(J) Set 0P=0 by decoding the command, and since op=o, (J) directly pass through the parameter processing, then (J) select the processing operation and proceed to (G) pattern (phono 1~) processing. Then, the program proceeds to the (S) halftone pattern and writes to the page memory. Since the pattern area is predetermined in the text mode and the halftone mode, the subroutines are shared in this way.

(4) Pi1-Image Mode When the focus image mode designation command arrives, the device 100 decodes the (nu) command and sets P=8,0P=2 to
-C, then (to) Receive 8 parameters from the host 200 in Parameter Settings, and ()) Select 0 in Parameter Settings.
Since P=2, proceed to (2) bit image mode parameter (Figure 36b) and (c) parameter calculation (2)
) and proceed to (te) focus image processing by selecting (ne) processing operation, where the data to pin 1 is received by the centronics input and written to the page memory.

(5) Print & Non-Clear or Print Clear When these commands arrive, the device 100 sends P=L, 0P=10 or 11 by (nu) command decoding, and (g) host parameters (,) by parameter processing. Receive from 200 with Centronics input, then ()) Pass through the meter setting selection as it is, and select (1) in the processing operation selection.
The process proceeds to printing, where the number of printouts indicated by the parameter n is executed, and the page memory is held or cleared depending on whether it is non-cleared or cleared.

(6) Logical operation In the halftone mode, the logical operation is the inverted writing residue in the (S) halftone pattern subroutine, and in the focused image, the inverted writing 2 overwriting (OR) in the (TE) pit image processing. ) or exclusive OR writing is selectively performed as specified in advance by the parameters of the command.

When other commands arrive, data processing [(v) command decoding - (v) parameter processing = (v) processing operation selection] is similarly executed to execute a predetermined subroutine.

In the above embodiment, the command 1-' in the halftone mode specifies only the write 1717 start a1-'response, or the command 1-' in the halftone mode specifies only the command 1717 in the image mode.
Furthermore, four parameters indicating the end 71-address are added, and the end address is set to Ij as in the bit image mode.
n! It may be revised together with the lfj address.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an outline of the configuration of an embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of the CPU board 10 shown in FIG. 1, and FIG. 3 is a block diagram showing the configuration of the CPU board 10 shown in FIG. 1.
1 is a block diagram showing the structure of the pattern area 84 shown in FIG. 1, and FIG. 5 is a block diagram showing the structure of the interface board 40 shown in FIG. 1. FIG. 6 is an explanatory diagram showing the memory divisions of the page memory 20. FIG. 7 is a flowchart showing an overview of the operation of the device 100;
FIGS. 8, 9, 10, and 11. FIGS. 12, 13, 14, and 15. No. L6121. Figures 17, 18, and 19. Figure 2Q, Figure 2], Figure 22, Figure 23; Figure 24 a
Figures 24b, 25, and 26. Figures 27a, 27b, 28, and 29. Figures 30a, 30b, 31, and 32. Figures 33, 34, 35, and 36a. Figures 36b, 36c, and 36d. Figures 36e, 36f, and 3Gg. Figures 36h, 36i, and 36j. Figure 36, Figure 361, Figure 36n]. 36n, 37, 38, and 39 are flowcharts showing the operation flow of the subroutine, respectively. FIG. 40 shows time charts 1 to 1 showing data transfer dynamics when data is transferred from the device 100 to the plotter 300.
It is. 100: 'RFI information memory HW I]: R
OM12 2 RAM
13: CPtJ31 Two-Pattern Memory Patent Applicant Ricoh Co., Ltd. Figure 11 Figure 712 Procedure 10 Official (spontaneous) Commissioner of the Japan Patent Office Kazuo Wakasugi 1. Indication of the case 1982 Patent Application No. 0425819 2. Title of the invention Information storage device 3, relationship with the person making the amendment Patent applicant address 1-3-6 Nakamagome, Ota-ku, Tokyo Name/
('674) Ricoh Co., Ltd. Representative Hama 1) Hiro 4, Agent 103 Telephone 03-864-60
52 Address: 2-27-6-5 Higashi Nihonbashi, Chuo-ku, Tokyo, Column 6 of the detailed explanation of the invention in the specification subject to amendment, and the 9th line of the following page of the specification of contents of the amendment, are correct. Correct the content. that's all

Claims (10)

[Claims] (1) Page memory in which one bit corresponds to each pixel of one page; Pattern memory that stores character pattern data and density gradation expression pattern data; Input/output interface; Command decoding means for setting processing operations and parameters; Text mode writing means for converting an input character code into character pattern data represented by the code and writing the pattern data into a predetermined area of the page memory; halftone mode writing means for converting the gradation code into gradation pattern data specified by the code and writing the 4-bit pattern data into a predetermined area of the page memory; An information storage device comprising: focused image mode writing means for writing into the area; and page memory output means for outputting page memory data a predetermined number of times. (2) The information storage device according to claim (1), wherein the predetermined area is an area set by instruction decoding means. (3) The bit image writing means marks the end of the writing area as
The information storage device according to claim 1 or 2, wherein the information storage device is determined by a relative value from the start position in the same address unit as the start position. (4) The text mode writing means uses the writing start end of the page memory as the starting point for the first writing area after power is turned on, and after execution of either writing mode, the starting point of the character writing area.
When the previous process is in text mode, it is next to the end point of the previous write process, when the previous process is in halftone mode, it is next to the end point of the previous write process, and when the previous process is in pit image mode, it is next to the end point of the previous write process. An information storage device according to claim 1 or 2, which performs positioning after return or line feed processing. (5) In the halftone mode writing means, the first write area after the power is turned on starts at the write start end of the page memory, and after execution of any write mode, the start point is the start point of the halftone pattern write area. point after the end point of the previous write operation when the previous operation is in text mode, after the end point of the previous write operation when the previous operation is in halftone mode, and after the end point of the previous write operation when the previous operation is in halftone mode. The information storage device according to claim 1 or 2, wherein the information storage device uses the position after backward, return, or line feed processing when in mode. (6) The focus image writing means determines the first writing area after the power is turned on, and after executing one of the writing modes, the starting point of the bit image writing area is determined by the previous process. When in 1-mode, it waits for the specification, and when the previous process is in halftone mode, it also waits for the specification, and when the previous process is in pitch image mode, it specifies return or line feed processing. Claim No. 1 (1)
) or (2). (7) The information storage device according to claim (1), wherein the page memory output means outputs the data of the page memory a number of times set by the instruction decoding means. (8) The page memory output means clears or holds the page memory according to the post-output memory processing instruction set by the instruction decoding means, as described in claim (1) or (7) above. information storage device. (9) The page memory output means is configured to output data of a predetermined section of the page memory to the output device in synchronization with a signal provided by an external output device. information storage device. (10) The input/output ink-face is equipped with a DMA controller, and the page memory output means transfers the data in the page memory to the output device by the DMA controller, which transfers the data to a parallel-in-serial-out buffer. An information storage device according to claim 1 or 7, which serially outputs data in synchronization with the operation of an output device.